Lecture-1

Introduction to Test Fault Models Fault Coverage Yield Introduction to Automatic Test Pattern Generation (ATPG)

Manuel dAbreu Santa Clara University

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Manufacturing Test Vs Silicon Verification

Manufacturing test validates that the hardware matches the final implementation

Hardware = final implementation!

Silicon verification validates that the hardware operates according to the design intent

Hardware = design intent!

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Introduction to the testing of Integrated Circuits

Why Test ?

Testing provides a means of ensuring that a product design is correct. When a product is fabricated, there is a need to test the product in order to ensure that faulty products are not delivered to the customer. Testing of products also provides important feedback about the design and fabrication of the product in order to improve the product quality.

There is a cost associated with testing and this has to be minimised.

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The rule of 10
If it costs 1 cent to locate an Integrated Circuit fault at wafer level.

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Introduction to the testing of Integrated Circuits

The testing of Integrated Circuits

has become increasingly important,

With ever increasing requirements for; Placement of more circuitry on the silicon die, Finer device geometries/nanotechnology, Higher device reliability, Lower overall production costs (including test costs)

Processor

Year of Production
1993 1997 1999 2000

No. of Transistors
3,100,000 7,500,000 24,000,000 42,000,000

Pentium Pentium II Pentium III Pentium 4

Over the past twenty years transistor design, fabrication and

manufacture costs have reduced, but the cost to test a transistor has remained roughly the same.
This is a major problem.
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MOORES LAW

(Gordon Moore, Intel)

Moore predicted that the number of transistor per Integrated Circuit would doubling of transistors every 18 months.

(Source: Intel)
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A Predication By the International Technology Roadmap For Semiconductors

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A Predication By the International Technology Roadmap For Semiconductors

The Cost to Test a single transistor must be made to track Moores Law.
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Metallization Structure

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Source of Defects

Metal Stack (Backend) Implant (Front end) Silicon Wafer

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Metallization CU, CMP (Chemical Mechanical Polishing)

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Metallization Issues
Large topographical variation caused by soft pad and mechanical properties

Isolated Transistor

Dense Array

CMP, SOG

Contact Overetch causes leakage

RIE

Etc.
Source: R. Pack, Cadence

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M1-M2 Metal Particle - Bridge

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Tools of the Trade - TESTERS

Main Frame

Sophisticated Machines

Expensive Big Driven by software Test programs Data-logging Complex logistics

Test Head

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Wafer, Die, and Pads

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Interface to the Wafer Wafer Probe

Probe card

Connects test head to chip pads on wafer Custom design for each new chip type Different technologies depending on pad-count, pad-spacing, and speed requirements

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What a Wafer Prober Looks Like

Handles wafers for test

Holds wafer Motion stage for indexing (moving to next chip/group of chips on wafer) Facilitates touch down

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Chip Packages

Containers for diced chips

Many different technologies and form factors, e.g., Pin-through-hole Solder balls Etc., etc., etc.

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Package Handler

Handles packaged chips

Yet another big, expensive machine

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Tools of the Trade - TESTERS

Main Frame

Sophisticated Machines

Expensive Big Driven by software

Test programs

Data-logging Complex logistics

Test Head

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Test Quality

Yield loss increases the product price

Fewer good chips per wafer

Test escapes can cause product fails at the customer

Defect-Level: percentage of defective chips shipped as good Measured in ppm (parts per million) Increases down-stream costs (scrap, repair, product delays, etc.) To minimize escapes, the test program ideally has to detect all defects

How can we estimate ahead of time how good the test program is?

Need a quality measure for the test data supplied from design!

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Why do we need Faults?

Faults

Netlist

ATPG /FaultGrading

Test Data

Fault Coverage

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The Test Challenge

Design Fab Defects

Faults

Correlation?

ATPG /FaultGrading

Wafers

Netlist

Test

Fault Coverage

Correlation?

Escapes/ Yield Loss

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What/How are Fault Models Used?

Fault-Grading

Criteria to be used for calculating fault coverage Conditions to be generated by Automatic Test Pattern Generation (ATPG) locally in the netlist to excite and propagate fault effects Establish link between netlist locations and fail behavior

Test Generation

Guide for Diagnosis

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Fault Grading
Netlist

Test Patterns

Fault Simulation

Fault List

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Coverage Reports

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Netlist and Fault Lists

ATPG/Fault-grading use a gate-level structural netlist of the network under test

Some circuit-level elements (transistors, resistors, etc.) may be allowed but only sparingly The design flow must produce an accurate gate-level netlist Specially generated for test, if not needed otherwise

Faults are attached to pins, nets, or paths in the netlist

Most commonly individual faults are attached to the input/output pins of the logic gates in the netlist The collection of all individual faults defined for a netlist is called the fault list

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Fault Simulation
Fault-free network Good Machine

Stimulus data

Response comparison

Coverage Report

Network with fault Fault Machine

Fault List
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Fault Coverage

Fault coverage

Percentage of faults detected by the tests Information about individual faults or groups of faults, e.g., By which test a fault is first detected Sub-module I/O faults versus module-internal faults

Fault statistics

Fault dictionary (optional)

More detailed information about how each individual fault is detected Used for diagnostics

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Fault Models

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Outline

Fault models

Stuck-at faults Excitation Propagation (sensitization) Equivalence Dominance Fault collapsing

Fault coverage Model accuracy, other fault models Accidental fault detection

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Simple Example
Single 2-input AND gate ATE can stimulate (control) the 2 inputs i1 , i2 ATE can measure (observe) the output o1

To test a defect it is necessary find input values for which the behavior at o1 with defect differs from the behavior without defect

Faults are logic-level models of defective behavior

i1 i2 o1

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Classical Fault Model

Stuck-at-Faults

Attached to each input/output pin of each logic gate in a structural netlist Stuck-at-1 (sa1)

Respective pin permanently stuck at logic 1 Respective pin permanently stuck at logic 0

Stuck-at-0 (sa1)

Single fault assumption

Only one fault is active and affects the value of the respective pin All logic gates (including the one with the faulty pin) and all other nets/pins are fault free

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Fault Generation Example

Good Machine i1 o1 i2 i1 i2 o1

00 01 10 11
i1 i2 ab

0 0 0 1
o1

Fault Machine, i1-sa1 i1 i2 1 a o1 b

00 01 10 11

10 11 10 11

0 1 0 1

test for i1-sa1

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Fault Excitation/Propagation Example

Example fault i1-sa1

Fault excitation requires gm-value of 0 at i1 Fault propagation requires non-controlling value at i2

1 for an AND gate, 0 for an OR gate Sensitizes a fault propagation path through the gate

i1 i2 i1 i2 1 a o1 b

ab

o1 gm/fm

00 01 10 11

10 11 10 11

0/0 0/1 0/0 1/1

Fault Machine, i1-sa1

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More Faults

A 2-input, 1-output gate has 6 possible stuck-at faults

i1 i2 o1

i1 i2

i1 sa1

i1 sa0

i2 sa1

i2 sa0

o1 sa1

o1 sa0

00 01 10 11

0/0 0/1 0/0 1/1

0/0 0/0 0/0 1/0

0/0 0/0 0/1 1/1

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0/0 0/0 0/0 1/0

0/1 0/1 0/1 1/1

0/0 0/0 0/0 1/0

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Fault Equivalence

If AND THEN

fault-a-tested <=> fault-b-tested fault-a-tested <=> fault-b-tested faults a and b are equivalent

2-input AND: i1-sa0, i2-sa0, o1-sa0 are equivalent The 3 faults form a fault equivalence class
i1 sa1 i1 sa0 i2 sa1 i2 sa0 o1 sa1 o1 sa0

i1 i2

00 01 10 11

0/0 0/1 0/0 1/1

0/0 0/0 0/0 1/0

0/0 0/0 0/1 1/1

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0/0 0/0 0/0 1/0

0/1 0/1 0/1 1/1

0/0 0/0 0/0 1/0

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Fault Collapsing

The fault behavior of all faults in a fault equivalence class is indistinguishable Fault Collapsing: Select one equivalent fault to represent all faults in the class Reduces the number of faults to be explicitly considered for fault simulation, ATPG E.g., reduces the 6 possible faults for the 2-input AND gate to 4 independent faults

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More Equivalence Rules

sa0 sa1 sa0 sa1 AND sa0 sa1 sa0 sa1 sa0 sa1 sa0 sa1 sa0 sa1 NAND sa0 sa1 sa0 sa1 NOR sa0 sa1 sa0 sa1 sa0 sa1 sa0 sa1 FANOUT
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sa0 sa1 WIRE

sa0 sa1 OR sa0 sa1

sa1 NOT sa0

sa0 sa1 sa0 sa1

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Equivalence Example
sa0 sa1 sa0 sa1 sa0 sa1 sa0 sa1 sa0 sa1 sa0 sa1 sa0 sa1 sa0 sa1 sa0 sa1 sa0 sa1 sa0 sa1 20 Collapse ratio = ----- = 0.5 40
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Faults in tan removed by equivalence collapsing sa0 sa1 sa0 sa1 sa0 sa1

sa0 sa1 sa0 sa1 sa0 sa1 sa0 sa1

sa0 sa1

sa0 sa1

Fault Dominance

If BUT THEN

fault-a-tested => fault-b-tested fault-b-tested > fault-a-tested fault b dominates fault a

2-input AND: o1-sa0 dominates i1-sa0, i2-sa0 Detection of i1-sa0 or i2-sa0 implies detection of o1-sa0 E.g., used in sorting fault lists for fault simulation, ATPG

i1 i2

i1 sa1

i1 sa0

i2 sa1

i2 sa0

o1 sa1

o1 sa0

00 01 10 11

0/0 0/1 0/0 1/1

0/0 0/0 0/0 1/0

0/0 0/0 0/1 1/1

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0/0 0/0 0/0 1/0

0/1 0/1 0/1 1/1

0/0 0/0 0/0 1/0

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Test Patterns Vs. Fault Detection

Some patterns detect multiple faults E.g., i1i2=11 detects 3 faults, 01, 10 detect 2 faults Not all patterns are needed for detecting all faults E.g., i1i2=11, 10, 01 detect all 6 faults, 00 is not necessary

i1 i2

i1 sa1

i1 sa0

i2 sa1

i2 sa0

o1 sa1

o1 sa0

00 01 10 11

0/0 0/1 0/0 1/1

0/0 0/0 0/0 1/0

0/0 0/0 0/1 1/1

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0/0 0/0 0/0 1/0

0/1 0/1 0/1 1/1

0/0 0/0 0/0 1/0

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Fault Coverage Example

2-input AND example, test patterns 00,01,10

6 faults of which 3 (i1/i2/o1-sa1) are tested, 3 (i1/i2/01-sa0) are untested 3/6=50% fault coverage 2 (i1/i2-sa1) are detected once, 1 (o1-sa1) 3 times, 3 (i1/i2/o1sa0) 0 times
i1 sa1 i1 sa0 i2 sa1 i2 sa0 o1 sa1 o1 sa0

i1 i2

00 01 10 11

0/0 0/1 0/0 1/1

0/0 0/0 0/0 1/0

0/0 0/0 0/1 1/1

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0/0 0/0 0/0 1/0

0/1 0/1 0/1 1/1

0/0 0/0 0/0 1/0

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More on Faults
R A S 1 Q

2
Faulty Response
A/0 S/0 R/0 A/1 S/1 R/1

Inputs
SR

Response 0 0 1 0

FF

01 00 10 11

0 1 1 0

0 0 0 0
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X X 1 1

0 1 0 1

0 0 1 1

1 1 1 1
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Yet More on Faults

A C S B
Reconvergent

A C S B (b)

D F (a)

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Redundant Faults

A C S B SA1 (a) D E F G Z a c Redundant Line b a (b) 1 z 2

Redundant Gate

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Transistor Level Faults

Logic level interpretations:

Stuck-at-1
Broken (change of the function) Bridging Stuck-open (change of the number of states) Stuck-on (change of the function) Short (change of the function) Stuck-off (change of the function)

Stuck-at-0
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Transistor Stuck-on Faults

NOR gate Stuck-on

VDD x1 x2

VDD x1 x2

x1

x2

RN
Y x2 VSS

Y x1 x2 VSS x1

0 0 1 1

0 1 0 1

y yd 1 1 0 0 0 VY/IDD
Q

RP

Conducting path for 10

VDDRP VY = (RP + RN )
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Transistor Stuck-off Model

NOR gate Stuck-off (open) VDD x1 x2 Y x1 x2 VSS x1 x2 VSS x1 x2 Y VDD

x1

x2

0 0 1 1

0 1 0 1

y 1 0 0 0

yd 1 0
Y

Test sequence is needed: 00,10

No conducting path from VDD to VSS for 10

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Bridging Faults
Wired AND/OR model x1 x2 W-AND: x1 & x2 W-OR: x1 1 x2 x2 x1 x2 x1 x1 x2

Fault-free

W-AND x1 0 0 0 1 x2 0 0 0 1

W-OR x1 0 1 1 1 x2 0 1 1 1
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x1 0 0 1 1
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x2 0 1 0 1

Bridging Fault Model

Dominant bridging model x1 x2 x1 dom x2: x1 x2 x2 dom x1: x1 x2 x1 x2 x1 x2 x1 x2

Fault-free x1 dom x2 x2 dom x1

x1 0 0 1 1
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x2 0 1 0 1

x1 0 0 1 1

x2 0 0 1 1

x1 0 1 0 1

x2 0 1 0 1
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Transistor Level Vs. Gate Level

Function:

y = x1x2 x3 x4 x5

y x1 x2 x4 Short

Faulty function: x5

y d = ( x1 x4 )(x2 x3 x5 )

x3

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Functional Fault Vs. Stuck at Fault

Full 100% Stuck-at-Fault-Test is not able to detect the short:

y = x1x2 x3 x4 x5
Full SAF-Test

y d = ( x1 x4 )(x2 x3 x5 )
Test for the defect Functional fault
The full SAF test is not covering any of the patterns able to detect the given transistor defect
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N o 1 2 3 4 5

x1 x2 x3 x4 x5 x1 x2 X x4 x5
3

1 0 0 1 1

1 1 0 1

1 1 1 0

0 1 0 1 0

1 1 0 -

1 1 0

0 1

- 0 0 0 1 1

1 1 0

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Delay Fault Models

Transition faults Each gate input and output can be slow-to-rise or slow-to-fall Conditional, temporary stuck-at faults Assumption: defective delay is long enough to be detected at given strobe timings (model itself includes no timing)
Stuck-at fault model Transition fault model

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More on Delay Faults

Path delay faults

Timed edge propagation along signal path(s) Typically applied to small subset of all possible paths
Useful for characterization, process window, speed binning (paths with representative cross-section of function elements) Not generally useful for random defects (too many paths)

Small delay faults

Include timing information and fault size (defective delay adder) of detectable delay faults Can be used with node- and path-oriented models Mostly useful for calibrating delay test generation effectiveness
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Other Relevant Fault Models

E.g., IDDq

IDDq is observed through power supplies connected to all design cells (not only scan cells)

Very high observability

Typically use pseudo-stuck-at faults Fault propagation to design cell output is sufficient
Much easier than propagation to scan cells or POs Few tests achieve high coverage

IDDq testing detects can detect many delay-type defects

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Dynamic Defects: The Issue

Signal transitions are delayed

Require transitions for testing (two or more test patterns) May escape detection in test if strobed too late (DC test)

logic

system cycle X Y defect system fails

test strobe test passes

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Dynamic Defects: What they do

Generate tests with transitions

Needs appropriate fault models Move strobe as close to product limits as reasonably possible

Tighten test timing

system cycle X Y

test strobe

test fails

defect

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Fault Grading and Quality

Quality

of tests influence the quality of shipped

product
If

Y is the manufacturing yield (the probability that a manufactured circuit is defect-free, DL the defect level (the probability of shipping a defective product) and d the defect coverage of the test(s) used to screen manufacturing defects, then the relationship between these variables is given by

DL = 1 (Y )1-d
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(Williams & Brown 1981)

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Defect Level Vs. Defect Coverage

1.0
y = 0.01

0.8 Defect Level

y = 0.1 y = 0.25

0.6
y = 0.5

0.4
y = 0.75

0.2
y = 0.9

0 0

y = 0.99

20

40 60 Defect Coverage (%)

80

100

Ex: if process yield = 0.5, then to achieve a 0.01 defect level (1% of shipped devices are likely to be defective) we need 99% fault coverage. A test with only 95% fault coverage will result in 0.035 defect level. If yield = 0.8, then 95% fault coverage is sufficient to achieve a defect level of 0.001
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Faults and Detection Methods

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Faults and Detection Schemes

Fault Model Detected by Test Procedure Comments

Path delay Stuck-at Bridging

Voltage tests

Speed testing

Requires guardbanding at the tester, known paths and tests

High fault coverage costs Design must have Iddq and voltage Structural tests and current (Iddq) low background current measurements, high burn-in toggle coverage voltage Structural tests run at speed Tests vectors must be targeted to defect prone layout areas

Voltage

Structural tests

Gate delay

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How to Interpret Fault Coverage Results?

Faults are classified as:
Detected - a test does indeed detect these fault Undetected - these faults can be detected but a test must be provided Potentially Detected - these faults generate an unknown (x) value at the output Untestable - there is no way to test for these faults (due to redundant logic, uncontrollable fault, masking effect)

How to reconcile these?

Untestable - for computing the fault coverage, delete these from the total fault list. These faults will need other type of tests Potentially Detected - (i)optimistic treatment: classify these as detected (ii) pessimistic treatment: classify these as undetected and (iii) give 50% for these towards the coverage number Undetected - subtract these from the total number when computing the coverage
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Automatic Test Pattern Generation

ATPG

Algorithmic generation of test patterns for model faults Requires netlist and fault list of the circuit under test Objective is to generate a set of test patterns that is capable of detecting as many faults in the fault list as possible Ideally all faults are tested (100% fault coverage)

ATPG typically alternates between

Constructive pattern generation for one or several untested faults at a time Fault simulation to determine if other untested faults are also tested

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Terminology

Primary Input (PI)

External circuit input that can be controlled by the ATE External circuit output that can be observed by the ATE A fault from the list of still untested faults selected for constructive pattern generation Forcing good machine value at the fault site to the opposite value of the fault value Making the difference between good-machine and fault-machine values visible at a PO
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Primary Output (PO)

Target fault

Fault excitation/activation

Fault propagation

Terminology (cont.)

Objective

Trying to achieve a logic value at an internal node in the circuit

Backtrace

Moving backwards from an objective towards the PIs

Justification

Finding PI conditions that achieve one or more objectives

Implication

Determine other circuit states required for an objective

Decision

Making a choice between multiple possible circuit states that could be help to achieve the objective
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Terminology (cont.)

Decision Stack

A list to keep track of decisions

Conflict

An implication derives the opposite value of an objective or invalidates the test (e.g., blocks all possible propagation paths)

Backtracking/Decision Re-make

Change an earlier decision to overcome a conflict

Test-Cube

Combination of specified logic values at a subset of PIs that achieves a test for the target fault Typically leaves some PI values un-specified
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Terminology (cont.)

Compaction

Merging compatible test cubes for multiple faults into a larger, combined test cube Specification of values at PIs that are un-specified in the test cube Test cube with fill such that all PI values are specified Test patterns are sent to fault simulation

(Pattern) Fill

Test Pattern

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Primary Inputs and Outputs

Primary Outputs

Primary Inputs

i1
i1 o1 i2

o1

i2

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Fault Selection

Select next target fault from untested faults

Based on some selection criteria (e.g., dominance)

sa1
i1 i2 o1

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Excitation and Propagation

2-Input AND, i1-sa1

Fault excitation requires gm-value of 0 at i1 Fault propagation requires non-controlling value at i2 1 for an AND gate, 0 for an OR gate Sensitizes a fault propagation path through the gate

i1 i2 i1 i2 1 a b

ab

o1 gm/fm

o1

00 01 10 11

10 11 10 11

0/0 0/1 0/0 1/1

Fault Machine, i1-sa1

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Fault Excitation

Requires opposite good-machine value at fault site

Defines an objective for pattern construction

0 0/1
i1 i2

sa1
o1

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Fault Propagation

Sensitize path(s) from the fault site to POs

Defines objectives for sensitizing conditions

0 0/1 1
i1 i2

0/1

o1

0/1

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Backtrack and Justification

Move backwards from objective site to PIs Establish suitable logic conditions at the PIs

1 0 1 1 0 0 1 1 0

0 0/1 1
i1 i2

0/1

o1

0/1

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Implication

Required values that are consequences of a new objective(s) and the existing circuit state

Forward implication: downstream values caused by the objective(s) E.g., established by simulation Backward implication: specific upstream values that are required (must-values) to justify objective(s) at gate outputs E.g., driven by gate-type-specific implication rules Propagation implication: sensitizing value required for fault propagation E.g., fault must propagate through a single gate
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Forward Implication

new value

0/1
i1

0/x x/x

o1

implied value

existing state

i2

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Backward Implication
i1 i2

1/1 x/x 1/1 x/x x/x

1/1

o1

new value

i1 i2

0/0 1/1

0/0

o1

new value

i1 i2

x/x
multiple choices: NO implications !!!

0/0

o1

new value

x/x

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Propagation Implication
0/0
i1 i2

0/1
sa1

0/x 0/1

o1

x/x 1/1

1/1
NO choices: MUST sensitize

0/0

0/1
sa1

0/1

multiple choices: NO implications !!!

1/1

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Decisions
x/x 1/1

a b x/x

x/x 1/1

x/1 1/1 x/x

x/x 1/1
sa1 0/1

0/1 0/1 0/1

Conflict: Propagation blocked

0/0 0/0

c 0/0 d 0/0

0/0

e x/x

decision 1

a=1/1
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new
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Decision Remake (Backtracking)

If last decision is new, set to opposite value, mark old If last decision is old, remake previous decision
0/0 1/1 0/x 1/1

a b x/x

0/0 1/1

x/x 1/1
sa1 0/1

0/x 0/1

0/1 0/x 0/1

Conflict: Propagation blocked

0/0 0/0

c 0/0 d 0/0

0/x 0/0

e x/x

decision 1 decision 1

a=0/0 a=1/1
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Un-Testable Faults

If no more decisions can be remade the fault is un-testable

0/0 0/0 0/0 0/0

a b x/x

x/x
sa1 0/1

0/x

0/x

Conflict: Propagation blocked

0/0 0/0

0/x

c 0/0 d 0/0

0/0

e x/x

decision 1

a=0/0
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old
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Redundancy

If a fault in a combinational network is un-testable and the search has been complete (e.g., no constraints that limit the search space), then the fault is redundant Combinational ATPG techniques are used for redundancy identification and removal in logic synthesis Combinational ATPG techniques are also used in Boolean equivalence checking

To prove that two networks are identical in Boolean function

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Un-Testable Faults

ATPG is an np-complete problem

Run-time for a single fault can be excessive (e.g., due to too much backtracking)

Practical algorithms have time-out criteria where an excessive search is aborted before completion To prove that a fault is un-testable or redundant requires completion of the search Faults that are not tested without being proven untestable or redundant are called untested faults.
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Back Up

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Fault Simulation

Fault simulators have to be very fast

Large networks (millions of gates) Long stimulus sequences (tens of thousands) Lots of faults (millions of faults)

Trade-offs are required

Accuracy (zero-delay versus accurate delay) Fault dropping (drop after first or multiple detects) Fault handling (one or multiple faults at a time) Pattern handling (one or multiple patterns at a time)

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Fault Simulation Techniques

Predominant fault simulation techniques are

Concurrent for manually generated tests One pattern at a time, event-driven simulation Multiple faults at a time Nominal delays Slower, but more accurate, better sequential capabilities PPSFP (Parallel Patterns Single Fault Propagate) for automatically generated tests Multiple patterns at a time, event-driven or compiled Single fault at a time Typically zero-delay (levelized network) Much faster, but less accurate, limited sequential capabilities
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Other Fault Grading Techniques

E.g., testability measures

Try to avoid cost of simulation Estimated fault coverage without explicit fault lists based on controllability/observability of network nodes Very limited use in practice for fault grading Not accurate enough Some use for automatic test point insertion Test points will be discussed later

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Fault Grading

Tool and methodology to measure the effectiveness of a test(s) to detect manufacturing defects

100% fault coverage does not imply absence of defects - fault coverage is only an approximation of defect coverage.
Fault coverage is based on the stuck-at fault model; there are defects that do not manifest as stuck-at. Experience indicates that a test(s) with high coverage for stuck-at also achieves a high defect coverage.

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Fault Excitation and Propagation

A stuck-at fault is excited (aka activated) if the good machine (gm) value at the fault site is the opposite of the fault machine (fm) value

E.g., gm value must be 0 for exciting sa1 faults, such that gm value and fm value differ at fault site

If the fault site is not directly observable, the difference between gm- and fm-value must be propagated to an observable pin

E.g., i1 is not directly observable, must propagate the fault effect (differing gm/fm values) of i1-sa1 to output o1
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Some Definitions ...

Manufacturing tests
Validates the manufacturing of the device; checks if the devices operation has been impacted due to defects introduced during the manufacturing process. Understanding of the manufacturing/fabrication defects is needed to develop tests

Functional tests
Validates the correct operation of a system with respect to its functional specification. In addition to verifying the specified operation of a system, it is also necessary to check that unintended operations do not occur

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Some Definitions ...

Manufacturing defects
Imperfections that a manufacturing process can incur. Semiconductor defects can be classified as (I) front-end and (ii) backend defects. Front-end defects are due to deviations in doping concentrations, implant depth etc.. Backend defects are ones that occur during the matalization steps.

Fault models
Electrical manifestation of a defect. This electrical manifestation can cause a logical or timing failure. There are a number of different fault models in existence stuck-at being the most widely used.
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