DESIGN OF A DIGITAL FRONT-END TRANSMITTER FOR OFDM-WLAN SYSTEMS USING FPGA

MaJosk Canet', Felip Vicedo', Javier Valls'. Vicenq Almenar3

* Dpto. Fisica y Arquitectura Computadores, Universitat Miguel Hernandez, Elche, Spain

Dpto. Comunicaciones, Universitat Politecnica de Valencia, Gandia, Spain e-mail: valmenar@dcom.upv.es
ABSTRACT
This paper deals with the implementation issues of a digital transmitter for OFDM based WLAN systems. We explore different solutions for signal generation in baseband and in intermediate frequency taking into account the effect of the analog conversion in the overall performance. In order to minimize distortion of the cyclic prefix a new interpolation filter structure valid for OFDM signals is presented. Finally, the cost in area for FPGA implementation of every needed circuit is given. In this paper we present the study and implementation of different solutions for OFDM signal generation in a digital front-end. We give alternatives for systems whose digital part works until baseband or until intermediate frequency (IF). Although this study has been carried out for the design of a HiperLAN 2 (HL/2) transceiver on FPGA [4], it can be extended to the rest of OFDM based WLAN standards. The paper is structured as follows. In this section main characteristics of OFDM based WLAN systems has been commented. Section 2 describes the transmitter subsystem where solutions for OFDM signal generation in baseband and in IF are presented. Finally, in section 3 some conclusions are stated. In section 2 it is described the implementation in FPGA of those necessary circuits. For this implementation we have used Virtex family devices from Xilinx. Moreover, to benchmark our designs, in each circuit we compare the area employed by it to that needed by Xilinx's tool Svstem Generator [5].

' Dpto. Electronica, Universitat Politecnica de Valkncia, Gandia, Spain

1. INTRODUCTION
New WLAN standards in the 5 GHz band (HiperLAN 2 and IEEE 802.11a) and in the 2.4 GHz band (IEEE 802.1 lg) are based on Orthogonal Frequency Division Multiplexing (OFDM) transmission [ 1,2,3]. They have been designed to provide data rates up to 54 Mbps in order to support broadband multimedia communications. Orthogonal Frequency Division Multiplexing (OFDM) has been selected as the modulation scheme due to its good performance on highly dispersive channels, like the indoor scenarios where these standards will be used. The baseband signal can be easily generated using a 64-IFFT, and then a guard interval (also called cyclic prefix) using the last 16 samples must be added to make the system robust to multipath. Since the frequency sampling is 20 MHz, each symbol is 4 ps length (80 samples), including a guard interval of 800ns. To facilitate implementation of filters and to achieve sufficient adjacent channel suppression, only 52 subcarriers are used: 48 are data carriers (with modulations types from BPSK to 64-QAM) and 4 are pilots for phase tracking. This makes that subcarrier spacing is 312.5 kHz, and spacing between two outmost subcarriers is 16.25 MHz. That is, in baseband, the higher carrier is centred at 8.125 MHz.

2. TRANSMITTER
As it was commented above the OFDM signal can be generated at a rate of 20 MHz by a 64-point IFFT and the addition of a cyclic prefix of 16 samples. After this digital signal processing, samples must be converted to an analog signal, in this section we discuss three different solutions. The first one is the most straightforward manner, it consist in connecting two D/A converters (DAC) to both phase and quadrature branches working at a rate of 20 MHz. As we will see in subsection 2.1, although this solution is the one which makes use of fewer resources in the digital part, it causes a higher degradation in the generated signal that can only be compensated in part. The second solution is set out to solve those problems commented above, this works also in baseband, and consists in interpolating the OFDM signal from a rate of 20 MHz to 40 MHz, in subsection 2.2 we propose a new filter structure that performs the interpolation process without introducing inter-symbol interference (ISI).

0-7803-8379-6/04/$20.00 02004 IEEE.

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Finally, subsection 2.3 describes a possible solution for digital IF signal generation.
2.1. Baseband signal generation at 20 MHz

the cyclic prefix due to this filter, obtaining that more than 200 ns (4 samples) are distorted by the analog filter.

l o l ................. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ......................................
L

In this section we consider that the phase and quadrature outputs are directly connected to the DAC. As it was stated in the introduction, in order to facilitate the implementation of filters, only 52 subcarriers are employed: DC subcarrier and those in the higher frequencies are set to zero. So, the highest frequency subcarrier is centered at 8.125 MHz. In this solution there are two sources of distortion: the DAC, and the reconstruction analog filters. The first one has a frequency response with the well known sin(x)/x shape: due to this amplitude distortion the highest subcarrier suffers from an attenuation of 2.5 dB respect to the lowest one. At a first glance, it can be assumed that this attenuation can be compensated with other channel distortions by receiver's equalizer. However, as can be seen in Figure 1, this solution (dash dotted line) degrades the performance of the system: a loss of more than 1 dB at a bit error rate (BER) of lo4. So, to avoid this degradation it is necessary to pre-equalize this amplitude distortion in the transmitter (dotted line in Figure 1). Pre-equalization can be performed in the transmitter at a higher implementation cost. Good performance is obtained (dotted line in Figure 1) if subcarriers attenuated 1 dB or more by the DAC are amplified before the IFFT. This amplification can be done by multiplication or by adjusting the look-up table used in the subcarrier mapping. This last option consumes less FPGA resources. In both cases one bit more is needed to quantize the IFFT input signal due to signal amplification: in a normal transmitter 6 bits are enough [4]. The second source of distortion comes from analog reconstruction filtering. In an OFDM system a cyclic prefix is employed to prevent ISI, so its length must be equal or higher than the length of the significant part of the channel impulse response [6]. In a real system the total channel impulse response, not only comes from the multipath channel, but also from all transmit and receive filters. To check this effect a Butterworth analog filter has been designed with specifications that minimize distortion in the passband signal and attenuate the spectrum images generated by the D/A reconstruction process. The passband ripple is fixed as 0.5 dB at 8.5 MHz (the higher subcarrier is centered at 8.125 MHz). The beginning of the stopband is set at 11.5 MHz since at 20 MHz the first image can be found. To calculate the attenuation at this point we take into account both the attenuation given by the DAC (5.5 dB at 11.5 MHz), and the specifications of the transmission spectrum mask [ 11 that must be fulfilled by the output signal. Therefore, this value is fixed at 25 dB. With these specifications a 12'h order Buttenvorth filter is needed. We have checked the contamination of

.................. . . . . . . . . . . . . . . . . . . .

I - ldeai signal

tj

Cfl

Performance of an HL/2 system in a multipath channel A for different transmitter configurations

Fig. 1.

Next, as an example, we show what could happen in a HL/2 system whose standard sets as optional the use of a short cyclic prefix of 8 samples (400 ns). In figure 1 it is shown the performance of an HL/2 system (solid line with circles) through a multipath channel model A (50 ns rms delay spread [7], this is a typical NLOS office building environment) when a 12'h order Butterworth filter is used. It can be seen that IS1 degrades the performance of the system since the total channel impulse response (the convolution of the multipath channel with the transmitter filter impulse response) is larger than the short prefix (40011s). In this example an ideal OFDM receiver is assumed, therefore, in a real case, receiver front end filters (analog and digital) would increase the total distortion.

2.2. Baseband signal generation at 40 MHz

Despite leaving in the standards some subcarriers unused to simplify the conversion to the analog domain, we have seen that working at a sampling frequency of 20MHz introduces two problems: amplitude attenuation in some subcarriers due to the DAC, and a degradation of more than 20011s in the cyclic prefix due to the high order analog reconstruction filters employed. An obvious solution for both problems is to use a higher sample rate in the digital to analog conversion. However, this solution has a cost in the digital domain: more area will be employed to implement the necessary interpolation circuits, and there will be more power consumption due to the extra circuitry and the use of higher rate D/A converters. We have confirmed by simulation and experimental results that both distortions can be settled using a sample rate of only 40 MHz, and that there is no benefit in using a higher frequency as in [8], where a sample rate of 80 MHz is employed. Now the DAC attenuation at the higher

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subcarrier is less than 0.6 dB (compared to 2.5 dB in the previous case) and it is no longer necessary to preequalize. This simplifies the design of the transmitter. Moreover, first image appears centered at 40 MHz, therefore filter specifications can be relaxed: the stopband begins at 3 1.5 MHz and only 20 dB of attenuation are necessary thanks to a DAC attenuation of more than 12 dB. Only a 31d order Butterworth filter is needed, whose impulse response distorts less than 50 ns (1 sample). At a higher rate like 80 MHz the order of the filter is the same, so the analog design is not simplified at the expense of a higher complexity in the digital part. There are two ways of generating an interpolated by two OFDM signal: using an 128-IFFT or using an interpolation filter. The digital filter option has the same drawback as the previous analog filter: it shortens the safeguard part from the cyclic prefix. Its impulse response convolves with those of the dispersive channel and analog filters in the transceiver chain. So, IS1 can appear if the total impulse response is larger than the cyclic prefix. On the other hand, the 128-IFFT option generates an undistorted OFDM signal since in this case the cyclic prefix is generated copying the last 32 samples of the IFFT output. The main drawback of this solution is that an 128-IFFT needs more than twice the area of a 64-FFT [9]. In order to use as less as possible area in the interpolation process we have designed a new filter structure that interpolates each OFDM symbol using only samples from that symbol, preventing in this way IS1 from happening. As this new structure takes into account the periodicity of the OFDM signal, we have named this as circular interpolation filter.

behind this structure is to calculate the interpolated samples making use of samples from the present OFDM symbol: this preserves periodicity in the cyclic prefix. Figure 2 shows the hardware realization of this structure, and Figure 3 shows those signals involved. 64 samples from the FFT (named from 0 to 63) are stored in a dual port RAM, these samples are passed to the polyphase halfband interpolator filter which gives 128 samples, 32 of them are stored in a FIFO for cyclic prefix generation.

addr-A

42

MUX

RAM
Counter mod 64

FIFO

Fig. 2 HW realization of circular interpolation filter

memory full

symbol 1

symbol 2

Fig. 3 Control signals and number of output samples

2.2.1. Circular interpolation filter structure

To interpolate by 2, the first step is to design the halfband filter impulse response. We have used next filter specifications: a passband distortion of less than 1% (0.17 dB of ripple), a stopband attenuation of more than 20 dB (due to spectrum transmission mask), and an odd number of coefficients (this makes that in a halfband filter half the coefficients are zero). An equiripple filter design of 241h order (25 coefficients) meets the requirements (this filter has a passband ripple of 0.14 dB and a stopband attenuation of 41 dB). In a conventional interpolation structure this filter would be placed after the cyclic prefix generation block in the transmitter chain. But, as we commented previously, in an OFDM signal this filtering would distort the guard interval because the first 24 samples from the interpolated guard interval are generated using samples from a previous symbol, destroying in this way the periodicity at the beginning of the cyclic prefix [9]. The proposed interpolation structure goes directly after the FFT output and, besides interpolating the OFDM signal, it also generates the cyclic prefix. The main idea

Interpolation process begins when the RAM is filled with 64 samples from the FFT process: this is indicated by control signal memoryf u l l . In this structure, the 32 cyclic prefix samples are generated first and stored in a FIFO to be read at the end, completing in this way the OFDM symbol generation. So, the first sample to be passed from the RAM to the interpolation filter should be sample 48 (the first sample of the cyclic prefix). But to cope with filter delay (12 interpolated samples in our design) the first read sample must be 42 instead of 48 (6 samples delay before interpolation). As can be seen in Figure 3, this value is used to initialize the modulus 64 counter that addresses the RAM.Then, after 24 output-clock cycles more, the filter output is valid: from this moment the filter registers are filled only by samples of the present OFDM symbol. Next, during 32 output-clock cycles, as can be seen in Figure 2 and 3, MUX output (controlled by signal sel) is read from filter output, and FIFO (controlled by signals we and re) begins to be filled with the first 32 samples, then we is deactivated. After 96 output-clock cycles more, 128 interpolated samples have been generated, and signals re and se1 are activated to read samples stored at the FIFO. Filter continues working although its output is not used. 8 output-clock cycles later,

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m e m o y j i l l is again activated and the process starts again

filling the filter with the next OFDM symbol samples. Let us see the implementation cost of this structure. The FIR filter employs a polyphase structure and makes use of symmetries in filter coefficients; it has been implemented using distributed arithmetic. Fixed point precision has been evaluated [4] and only 8 bits are necessary both for the OFDM signal and for coefficients. To reduce the use of HW resources polyphase subfilters work serially; so, the minimum clock frequency is 20.8 = 120 MHz, which can be achieved by Virtex-E family devices. Our final design needs 46 FPGA slices per branch, whereas the same design done using System Generator needs 155 slices per branch. The control circuits (which work over both filter branches) of the circular filter make use of 62 slices in an optimized VHDL implementation, and 97 slices when System Generator is employed. In both cases the FIFO can be implemented using one BSRAM from the FPGA. To summarize, our design makes use of 154 slices and one BSRAM, whereas System Generator implementation needs 407 slices and one BSRAM.

table based DDS (Direct Digital Synthesis) and a complex multiplier. So, the CORDIC modulator makes use of 189 slices in the FPGA, meanwhile the DDS solution using System Generator needs 271 slices. In the analog domain, OFDM signal centred at 70 MHz is distorted by the DAC. In this case attenuation between higher and lower subcarriers is less than 0.8 dB, which can be seen from the central subcarrier as an attenuation of 0.4 dB for the highest subcarrier, and a gain of 0.4 dB for the lowest subcarrier. These values are low enough to be compensated by the receiver without performance degradation. As regards the analog filter, in this case a 3rd order bandpass Buttenvorth filter can attenuate the signal image centred at 130 MHz distorting only less than 90 ns of the cyclic prefix.

4. CONCLUSIONS
This paper shows that an OFDM signal for WLAN systems can be generated in baseband at a rate of 40 MHz with low distortion in the analog reconstruction. For interpolation a new filter structure, called circular filter, has been proposed, this new structure does not distort the cyclic prefix as a normal filter would do. Generation in intermediate frequency, which could be used in a Software Defined Radio implementation, has also been discussed. Finally, we have given implementation cost on FPGA for every circuit, comparing our optimized implementation with that given by Xilinxs System
Generator

2.3. Digital IF signal generation

In this section we will deal with signal generation at intermediate frequency by digital means. This last alternative could be employed in a Software Defined Radio solution of a multistandard access point. Here, as an example, an intermediate frequency of 70 MHz has been used since, apart from being a common IF, it allows us to show how FPGA can be employed in a high speed implementation. To comply with Nyquist sampling theorem, output sampling frequency must be 160 MHz or higher. So, to achieve a compromise between digital and analog implementation costs we have chosen a sampling rate of 200 MHz. In this case, an interpolation factor of 10 is needed; this can be done in two steps: the first one by 2 (using the scheme described in section 2.2) and the second one by 5. This second stage can be done using a FIR filter of 14h order (passband distortion lower than 1% and stopband attenuation greater than 30 dB). At a rate of 200MHz, this filter is so short compared to the cyclic prefix that distorts less than 80 ns. For this reason in this case the circular structure is not necessary. This filter has been implemented using a polyphase structure and distributed arithmetic. To achieve the needed throughput a digit-serial approach has been employed with a digit size of 2 bits. Coefficients are quantized with 8 bits. In this case our design employs 109 slices, meanwhile System Generator implementation needs 281 slices. The last circuit in the digital domain is the quadrature mixer. Here, a CORDIC operator has been employed [ 101. This approach saves area compared to schemes using a

5. ACKNOWLEDGEMENTS
This work was supported by the Ministerio de Cicencia y Tecnologia under Research Project TIC2001-2688-CO3 and in part by the Universitat Politecnica de Valencia.
6 . REFERENCES

[l] ETSI TS 101475 v1.2.2, BroadbandRadio Access Networks (BRAN): HIPERLAN Type 2; Physical (PHY) layer, Sep. 2002 [2] IEEE 802.1 la: Wireless LAN specifications: High-speed Physical Layer in the 5 GHz [3] IEEE 802.1lg: Wireless LAN specifications:Further Higher Data Rate Extension in the 2.4 GHz Band [4] F. Vicedo, M. Canet, J. Valls, and V. Almenar, FPGA design of an OFDM transceiver for HiperLAN 2, XIII Spanish URSI symposium, La Corufia, Spain, Sep. 2003 [5] Xilinx System Generator for DSP v2.2 Reference Guide [6] R. Van Nee and R. Prasad, OFDM for Wireless Multimedia Communications, Artech House, London, 2002 [7] J. Medbo et al., Channel Models for HIPERLAN 2, ETSI BRAN document number 3ERI085B, 1998 [SI E. Grass et al., On the Single-Chip Implementation of a Hiperlan 2 and IEEE 802.1 1a Capable Modem, IEEE Personal Communications, Dec. 2002 [9] M. Faulker, The effect of filtering on the performance of OFDM systems, IEEE Trans. on Veh. Tech., Sep. 2002 [lo] F. Cardells, and J. Valls, High Performance Quadrature Digital Mixers for FPGA, FPL2002, Monpelier, France, 2002

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