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Chap. 9 Interrupt p.

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PART 2.
Advanced Microprocessor Structures

The first part of the course explained the concept of the microprocessor. This was done by studying
a fictive (and afterwards the real PIC16F84) processor. Also the concept of the instruction set was
explained and some examples were given. This knowledge enables the engineer to practize some
experiments. But the PIC processor is just one of the many commercial available microprocessors.
As a matter of fact, it can even be considered as an entry level model.

Automobiles are available from brands like Ford, Volkswage, Volvo, Mercedes, Porsche, Ferrari,
Roll-Royce. All these cars have four wheels, a steering wheel, an engine and some iron envelope
box. They all aim the same target : moving its passengers from point A to point B. And yet the
market is asking for diversification. And the market rules

A similar situation is available on the microprocessor market. And knowing that a driver who can
drive a little Volkswagen can also drive a Mercedes, there is no need to study all available micro-
processors.

But it is meaningfull to study those aspects which do shine a certain microprocessor in a given ap-
plication. The study of these aspects are the subject of the second part of the course. One or some
combination of these aspects will be recognized in every middle to high range commercial micro-
processor.

This second part is dealing only with the von Neumann architecture where only one memory is
available for both program and data. This architecture is a good compromize between performance
and cost.

The PIC family with its Harvard architecture is rather an exception. The majority of the processors
only have the von Neumann. Especially if the memory is not part of the microprocessor chip. The
Harvard architecture is quiet expensive if the 2 memory types are externally : 2 databusses, 2 ad-
dressbusses, 2 control busses, a lot of busdrivers, decoders, etc. etc. This would result in an expen-
sive PCB with a high number of routing channels (multilayer PCB). The problem is less severe if
these 2 memories reside on the same die as the processor.

The highway in the von Neumann architecture is the databus. All transferts of data and instruc-
tions have to pass through this highway.
Processor
DATA
ADDRESS
CONTROL
Programma
(EP)ROM
FLASH
DATA
SRAM
DRAM
INPUT
OUTPUT

Chap. 9 Interrupt p. 2/ 12

Chapter 9. Interrupt Structures

The purpose of an efficient interrupt system is to process the data requests of the peripherals as fast
as possible and with a minimal of overhead. The overhead is required to identify the source of the
interrupt, to save the context of the CPU and to jump to the interrupt routine. After execution of the
interrupt routine the pre-interrupt context has to be restored and control has to be given back to the
interrupted program. To deal with interrupts as flexible as possible it is also required to recognize
priorities.
Maskable, Non-Maskable

Every decent interrupt system has 2 kinds of interrupts. The maskable interrupt (such as available
on the PIC16F84) can be enabled/disabled at any time by the programmer. The masking concept
also enables a controlled nesting of interrupts. (interrupt inside interrupt inside )
The non-maskable interrupt (NMI) can never be disabled. The NMI can interrupt any program at
any time. It is obvious that this NMI will be used only for extremely important events, such as a
coming power failure. To some extent the RESET could be considered as a NMI. But instead of
jumping to the interrupt routine there is a jump to a virgin situation. The RESET will forget about
the running program, the NMI will always give back control to the running program. The RESET is
destructive.
The NMI has its own interrupt vector : the appearance of the NMI will cause the program counter
to be loaded with this vector and the execution will continue at this new address. Of course, after
the previous value of the progam counter has been saved on stack !
Static Vector

The most simple implementation for the interrupt is by loading the program counter with a fixed
address. This address is the start of the interrupt routine, which is completed by the return instruc-
tion. The address which is loaded (by the hardware) in the program counter when the interrupt oc-
curs is also called the vector address or interrupt vector. The PIC16F84 has the value 0x04 as inter-
rupt vector.

Dynamic Vector

The mid- to high range microprocessors do not have a static but a dynamic interrupt vector : the
value which is loaded into the program counter depends on the situation. As a consequence there
are a lot of interrupt routines and they are accessible via the different interrupt vectors.

How can the outside world generate an interrupt and additionaly give information about its situa-
tion? The interrupting source has to take 2 actions :
1. it generates an interrupt signal
2. at the same time, it will put one single instruction on the bus.

This instruction, selectable by the user, can be interpreted by the CPU :

* either it is a simple instruction.
The concept simple instruction depends on the specific processor, but it could be for instance an
instruction which will set to 1 a given bit in a word. This instruction will quasi not interrupt the
running program. It is called a fast interrupt. The value of the program counter is not changed,
there is no jump to an interrupt routine: the only interrupt action is the execution of this simple in-
Chap. 9 Interrupt p. 3/ 12

struction. Besides, there is no need for a return.Obviously, very very fast interrupts can be served.

* either a complex instruction.
Once again, complex depends on the specific processor, but mostly some kind of jump or goto is
involved. This instruction will indeed interrupt the running program: the program counter will be
saved, the external instruction will be decoded and there will be a jump to the interrupt routine se-
lected by the address of the external jump instruction. The interrupt routine should finish with a re-
turn to give back control to the interrupted program.
The source of the interrupt not only generates the interrupt but also select the start of the interrupt
routine which should be executed. This allows for every interrupting device to be handled by its
own servicing routine. This concept is called thelong interrupt.

The fast and the long interrupt are implemented together. The instruction decoder is able to distinct
between the simple and complex instruction and will execute accordingly.

* Some processors are using another concept : they are using one dedicated instruction to jump to
several fixed interrupt vectors. The instruction RSTn could look like this :

111x xx00

The 3 selectable bits xxx are refering to 8 possible interrupt vectors at fixed locations offset, offset
+4, offset +8, offset +12, till offset +28. The value of offset depends on the specific processor.
The motivation to take a 4 byte step is mostly the instruction at that vector location will be a jump
to xyz. The jump instruction requires 4 bytes ; xyz can be any address pointing to a interrupt rou-
tine.

location instruction
----------- ---------------
offset +0 goto routine_0
offset +4 goto routine_1
...
offset +28 goto routine_7
...

routine_0 ... ; start interruptroutine #0
...
...
return

routine_1 ... ; start interruptroutine #1
...
...
return
...
routine_7 ... ; start interruptroutine #8
...
...
return

COMMENT
1. The static vector
The static vector does not need any additional hardware (low cost) but requires some software to
deal with the interrupts. There is only one interrupt routine and there are many interrupting sources.
The unique interrupt routine has to identify the source of the interrupt before it can proceed. This
is not requiring any intelligence from the interrupt source. All what is required
is to apply an electrical signal (0 or 1) to a given input. Thats all.
Chap. 9 Interrupt p. 4/ 12

requires some overhead software in the interrupt routine. Also some kind of priority scheme should
be managed to know if and when an interrupt can be interrupted by another interrupt. Indeed, cer-
tain sources are less important than others and should be processed accordingly.This also requires a
heavy overhead in the interrupt routine.
It is obvious that expensive but fast hardware has been replaced by cheap but slow software.

2. The dynamic vector
Most frequently one will only use dedicated building blocks which are developped by the micro-
processor manufacturer ($$$). These easy to use glueless building blocks allow to upgrade a
dummy source to a smart interrupt source.
mechanism requires some intelligence from the interrupting source. Its
hardware should be able to put the instruction on the bus. This requires a synchronization with the
whole processor system because normally the CPU has ownership of the bus. Changing ownership
from microprocessor to interrupt source is not that easily done and so requires a lot of dedicated
hardware at the source.

Who is generating the interrupt ?
This question need not be solved by the software because every interrupting device will point to its
own interrupt routine. This is the case as long as there are less interrupt sources than interrupt vec-
tors. If not, some filtered identification is required.
This situation is possible with the RSTn principle, never with the long interrupts.

What interrupt has priority ?
The priority can be controlled by the hardware. There are several implementations:

* The interrupt source can transmit additional signals to the processor (together with its interrupt
vector). These signals are connected with the priority input pins of the processor. The coded value
of these signals (eg. 3 signals can distinguish between 8 situations) contains priority information of
the interrupt. Internal in the processor is a priority register in which the running program can set the
priority level of the processor. Suppose that the register has a value of 4. This means that interrupts
with a value of 4 or higher are accepted, any interrupt with a value lower than 4 is ignored. The de-
cision is made by the hardware : the status of the priority pins are compared with the content of the
priority register. No software overhead is required in the decision.

Of course, the running program (this can be the normal program but also one of the interrupt rou-
tines) can change the priority register at any time. This allows for a dynamic nesting.
From time to time, the CPU should be at priority 0, otherwise the lowest interrupts will never be
processed.

* Another possibility is to put priorities in the interrupt vector itself. The highest vectors have the
highest priority. Once again, they will be compared with the internal priority register. This is the
case for the RSTn concept.

All these priority principles require a lot of extra hardware in the source. There is a handshaking
between processor and source : the processor has to acknowledge (or not) if the request for inter-
rupt is granted. Also the processor has to remember pending interrupts. Sooner or later, every inter-
rupt has to be processed.
The already mentioned dedicated building blocks also take care of the priority mechanism.

* The daisy-chain is another interrupt concept. The hardware overhead for the processor is mini-
mal. All interrupt sources are put into one chain and every item gets an IEI (interrupt enable in)
signal from its predecessor and generates an IEO (interrupt enable out) for its successor. The prior-
ity of the source is determined by its physical location in the chain. The leftmost source A has its
Chap. 9 Interrupt p. 5/ 12

IEI always at 1 and has the highest priority.

Bron_A
IEI IEO
Bron_B
IEI IEO
Bron_C
IEI IEO
Bron_D
IEI IEO
Databus
Vcc



If a source is not requesting an interrupt it will transfert its IEI signal to its output. The logical 1 at
IEI of source_A will be exported till the input IEI of source_D : every source could generate an in-
terrupt. Suppose source_C requires an interrupt. It will do so because its IEI is at 1 but source_C
will put its IE0 at 0. All devices located after source_C will be disabled to generate an interrupt.
The interrupt of source_C will be processed. But now source_B could also request an interrupt. It
can do so because its IEI is still at 1. It will disable the IEI of source_C and the routine_C will be
interrupted by routine_B. Source_C can even detect that it has been interrupted !
Once routine_C is executed routine_B will resume.
Of course, every source has its programmable interrupt vector register which value will be put on
the bus during the interrupt request.

3. Interrupt vectors also allow for patching. Patching (adapting) is an nice way to change the pro-
gram flow in read-only program memory. The von Neumann architecture only has one memory.
But of course, this memory is built up of several types of memory. The part of the memory used to
store the program will be implemented as (E)(P)ROM or Flash memory. RAM memory will be
used to store the data.

The interrupt vectors refer to locations in program memory ; they are burned into ROM.

Program memory :

locatie instructie
-------- ------------
vector_x goto do_x ; code in ROM
vector_y goto do_y ; (idem)
vector_z goto do_z ; (idem)

do_x action for routine x ; code in ROM
...
return

do_y action for routine y ; code in ROM
...
return

do_z action for routine z ; code in ROM
...
return

The occurence of vector_x will always call the same routine do_x.

Consider an existing
This is possible if first the interrupt vectors are pointing to a location in RAM. This RAM location
could point to the effective start address of the interrupt routine.
system. Suppose one would like to change the routine do_y into do_y1.
Chap. 9 Interrupt p. 6/ 12

'Program' memory (ROM)
---------------------------------------
vector_x goto do_xx ; code in ROM referring to RAM adress
vector_y goto do_yy ; (idem)
vector_z goto do_zz ; (idem)

do_x action for routine x ; code in ROM
...
return

do_y action for routine y ; code in ROM
...
return

do_y1 new action for routine y ; code in ROM
; (available in a subsequently added ROM)
...
return

do_z action for routine z ; code in ROM
...
return

'Data' memory (RAM)
-------------------------------
do_xx goto do_x ; RAM code referring to ROM address
do_yy goto do_y1 ; RAM code referring to ROM address
do_zz goto do_z1 ; RAM code referring to ROM address

do_z1 another action for routine z
...
return

This indirect goto the routine can optional be changed. In the example, the user program has
changed the indirect references in RAM : do_y is changed to do_y1 and do_z is changed in do_z1.
The new do_y1 resides in subsequently added ROM memory, the new do_z1 is loaded in RAM
memory.

The program should be organised in such a way that the required code for the RAM (either for the
reference table or for the routines) is available before it will be used for the first time.

The change in RAM can be done by the running program or by the add-on ROM.
Vector Table

The explained interrupt mechanism can even be extended with extra features. As an example con-
sider the interrupt concept of the Motorola MC68000 (16 bit processor).

A peripheral interrupt is but one way to interrupt the processor. There are other reasons why the
processor need to be interrupted. All events which could interrupt are put into one large vector ta-
ble. This table contains the info : if the event occurs, what value should be loaded in the progam
counter. The processor will continue by executing the instruction at that location. Normally this
will be a goto instruction ppointing to the interrupt routine.
The table not only contains the interrupt vectors, but every vector which are selected by a given
event. The Exception Vector is a extension of the concept Interrupt Vector.

This table with all the Exceptions gives a pretty good idea of what is available on a mid-range
Chap. 9 Interrupt p. 7/ 12

processor.




Comment :
Vector 0 : Stack Pointer
Vector 1 : Reset PC

These 2 vectors are executed when the processor starts from Reset or during power-up. The value
Chap. 9 Interrupt p. 8/ 12

of vector0 is copied into the stack poiner, the value of vector1 is copied into the program counter.
Vector1 gives the startaddress of the first instruction. Low-end processors have an on-chip stack
(cfr. PIC). It is a fast but a small stack. Mid- and high range processors have a stack in exteranl
RAM. The CPU has a pointer register to point to the top location of the stack.

Vector 2 : Acces Error

If the communication between the processor and the outside world is not as it should be (for what-
ever reason) the outside world can generate an access error (=signalisation on a certain phyisal pin).
This signal will not only activate vector2 but will put automatically (=hardware) som items on
stack to facilitate the diagnose of the error :
- value of the program counter
- the status register
- the instruction register
- the address at which the error occurred


The program counter has the address of the instruction being fetched when the error occurred. The
instruction register contains the instruction being executed and the address is the effective address
on the address bus during the error. This address should not be the same as the program couter. It
could be possible that the error occurred when the processor was dealing with an operand in data
memory. This address (and not the address of the instruction) will be saved in that dedicated stack
location.

A typical sitation for that error is that the external hardware is detecting that the processor is gener-
ating an address but there is no memory at that location.


Vector 3 : Address Error

This error is similar to the access error. Midrange processor are executing on bytes (8bit), words
(16bit) and long words (32bit). A word location always has to start at an even boundary, a long has
to start at a quad boundary. The processor will generate control signals together with the address
lines. The address error occurs if the address boundaries do not match the data type. Both the ad-
dress and the type identifier are generated by the software. The address error does not mean that the
processor is defect. No, it has to do with a small programming error..

Vector 4 : Illegal Instruction

It is possible that the processor is fetching an unknown instruction. This is an indication on the
quality of the program memory. The actions for vector4 are completely determined by the pro-
grammer.

Vector 5 : Integer divide by Zero

The midrange processor has a divide instruction. Division by 0 is not allowed and will be recog-
nized by the hardware and will result in exeption5. The activity of the exception routine is com-
pletely dependant on the programmer.
Chap. 9 Interrupt p. 9/ 12

Vector 6 : CHK

Some instructions are able to compare the content of given registers or memory locations to an up-
per- or lowe boundary. If the value is between limits, no problem, and the next instruction will be
executed. If not vector6 will be executed.


Vector 7 : (F)TRAPcc, TRAPV

A trap is to be considered as an interrupt which is generated by the softwae. The TRAP can test
certain conditions (overflow, carry, )and if true it will result in the execution of vector7.

Of course, no interrupt is strictly needed because the software is generating the event. The reason
has to do with structured programming.

Vector 8 : Privilege Violation


The midrange processor can operate in different modes. Consider the situation where several tasks
are running under the supervision of one main task. This main task could be the operating system
and the other tasks are the user applications running at a lower level.
A general idea is that the operating system is bug-free where the user program could be bad-
behaving. The operating system should have the final control over the system, even when some of
the applications are doing strange.

Therefore the 2 modes : supervisor mode and user mode
A well behaving stack is crucial if one would like to return from 12 levels of subroutine and 27 in-
terrupts. The user application should never access the system stack. And therefore 2 stacks and 2
stack pointers are provided.
. The processor is initialising in supervisor
mode and when ready will switch over to user mode. Some control bits keep track of the mode. The
difference between the 2 modes is processor specific but one thing is general : both modes should
have their own stack.
Also important is that certain operations could only be executed in supervisor mode (operating sys-
tem) and are forbidden for the user mode. The execution of supervisor instructions in the user mode
will result in vector8.


Vector 9. Trace

To make the debugging of a processor system (=hardware +software) somewhat easier it could be
meaningfull to put the processor in a single step mode. The context of the executed instruction will
be put completely on stack (by the hardware) and Vector9 could than be used as a kind of monitor
program to debug. From within the Vector9 routinte the processor can execute the next single step
of the user program.
Chap. 9 Interrupt p. 10/ 12

Vector 10 . Line '1010' emulation.

This concept is based on the fact that the MC68000 instructions never begin with the bit pattern
1010. If an instruction is fetched starting with pattern A than vector10 is executed. Notice that
more than one instruction could start with code A.
This concept allows that the user can implement a dedicated super instruction set. Each time the
processor is fetching such an instruction the vector 10 will be executed. This routine can execute
the dedicated instruction in software (done with the normal instructions). This is called emulation.:
the super instruction is executed by other instructions.

Thats not a strange thing of doing. These 1010 instructions will generate some extra control sig-
nals which could be recognized by external hardware. Eventually external hardware could react on
the 1010 instruction and execute the 1010 instruction in hardware. Before the instruction would
be executed in software by the microprocessor.
Summary : when the processor is fetching a 1010 instruction it will wait a few clock cycles so
that external hardware could take over. If there is no reaction from the external hardware the proc-
essor will execute Vector10 in software. As a matter of fact, the user can design his ovn co-
processor

. This could be for instance a graphics controller or a communication processor : they can
cooperate glueless with the processor.

Vector 11 . Line '1111' emulation.

This concept is similar as for the line 1010 emulation, but it is restricted for a floating point co-
processor. Because of the high volumes for floating point processors the manufacturers of micro-
processors will also sell the floating point processor.

Normal microprocessors can not execute floating point instructions. These instructions require ex-
tra hardware which is to expensive to be put on a general purpose microprocessor. If really re-
quired, the user can buy a separate co-processor. This processor will share the same busses as the
main processor but only during floating point operations. Ohterwise, the coprocessor will be idle.

The progammer can write a program as if a floating point processor is available. If this is not true,
the floating point instructions will be solved by software (slow). If yes, the hardware will execute
the floating point instruction (much faster).

The whole concept is completely transparant to the user. Normally one should not write the floating
point emulation. The Vector11 routine is available from the manufacturer of the processor.

Vector 12 : reserved for future extensions.

Vector 13 : Coprocessor Violation

A bad communication between the processor and coprocessor hardware handshaking signals will
result in vector13.

Chap. 9 Interrupt p. 11/ 12

Vector 14 : Format Error

Vector 15 : Uninitialized Interrupt

The vector table is a nice concept. It could even be better if the table would not be located at a fixed
location in ROM but at a flexible location in RAM. Once the processor is running the table can be
modified as required. The initial startup is done from ROM (because the RAM is still empty) but
one running the ROM table could be copied in RAM. This requires an extra internal register to in-
dicate where the startaddress of the vector table is located. After reset, that register has value zero.
Wrong manipulations of this base register will result in vectors14,15.(from ROM)

A possible application would be to have a separate vector table for the supervisor and for the user
applications. Eventually, every application could has its own vector table.

Vector 16 -23 : reserved

Vector 24 : Spurious Interrupt
.
Wrong handshaking between processor and interrupt source will cause vector24.

Vector 25 - 31 : Auto - Vectoren with priority.

The concept of the static interrupt vector is explained : a signal on a given input pin could cause an
interrupt where the program counter is loaded with a fixed value.
An extension would be to use not 1 but 3 input pins for the interrupt. The input 000 could mean
that there is no interrupt, code 111 could mean NMI.
The code could also imply the priority of the interrupt. A code higher than the internal priority reg-
ister will be accepted, a lower code will be rejected.
The code could also imply the identification of the source.

The name auto-vector is used because the interrupting source does not need to put an instruction on
the bus. Interrupts with auto-vectors can be implemented with minimal external hardware.




Chap. 9 Interrupt p. 12/ 12

Vector 32 - 47 : TRAP


As already mentioned, a TRAP could be an conditional interrupt generated by the software. There
are also unconditional TRAPS. (choice of 16).
Their use is similar to the calling of a subroutine, but mostly TRAPs will be used to call operating
system functions.

Vector 48 - 58 : Interrupts caused by floating point processor.

Vector 59 - 63 : reserved

Vector 64 - 255 :

These vectors are general purpose dynamic vectors, available for the user. The interrupting source
can call for one of these vector locations by putting the right vector number on the bus.

As mentioned, most of the vectors will also put some system information on the (supervisor) stack.