Bus AMBA

Advanced Microcontroller Bus Architecture (AMBA)

Rene.beuchat@epfl.ch Rene.beuchat@eig.unige.ch

Rf: AMBA Specification (Rev 2.0) www.a !.co! ARM "#" 00$$A
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What to see
AMBA %&%te! a chitectu e 'e ivative% Bu%( A#B( ASB( A)B * an%action%

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Bus hierarchies
Advanced Microcontroller Bus Architecture (AMBA)

Advanced High-performance Bus (A#B) Advanced System Bus (ASB) Advanced Peripheral Bus (A)B).

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Typical System

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Advanced High-performance Bus (AHB)

*he AMBA A#B i% fo high-performance( high clock fre uency system modules! *he A#B act% a% the high+pe fo !ance %&%te! backbone bu%. A#B %uppo t% the efficient connection of p oce%%o %( on+ chip !e!o ie% an, off+chip e-te nal !e!o & inte face% with low+powe pe iphe al !ac o cell function%. A#B i% al%o %pecifie, to en%u e ea%e of u%e in an efficient ,e%ign flow u%ing %&nthe%i% an, auto!ate, te%t techni.ue%. RB - 2003/2005 5

A,vance, S&%te! Bu% (ASB)

*he AMBA ASB i% fo high+pe fo !ance %&%te! !o,ule%. AMBA ASB i% an alte native %&%te! bu% %uitable fo u%e whe e the high+pe fo !ance featu e% of A#B a e not e.ui e,. ASB al%o %uppo t% the efficient connection of p oce%%o %( on+chip !e!o ie% an, off+chip e-te nal !e!o & inte face% with low+powe pe iphe al !ac ocell function%.
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A,vance, )e iphe al Bu% (A)B)

*he AMBA A)B i% fo low+powe pe iphe al%. AMBA A)B i% opti!i/e, fo !ini!al powe con%u!ption an, e,uce, inte face co!ple-it& to %uppo t pe iphe al function%. A)B can be u%e, in con0unction with eithe ve %ion of the %&%te! bu%.
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1b0ective% of the AMBA %pecification

*he AMBA %pecification ha% been ,e ive, to %ati%f& fou 2e& e.ui e!ent%:

to facilitate the right-first-time ,evelop!ent of e!be,,e, !ic ocont olle p o,uct% with one o !o e 3)4% o %ignal p oce%%o % to be technology-independent an, en%u e that highl& eu%able pe iphe al an, %&%te! !ac ocell% can be !ig ate, ac o%% a ,ive %e ange of "3 p oce%%e% an, be app op iate fo full+cu%to!( %tan,a , cell an, gate a a& technologie% RB - 2003/2005 8

1b0ective% of the AMBA %pecification (2)

to encou age modular system design to i!p ove p oce%%o in,epen,ence( p ovi,ing a ,evelop!ent oa,+!ap fo a,vance, cache, 3)4 co e% an, the ,evelop!ent of pe iphe al lib a ie% to !ini!i/e the %ilicon inf a%t uctu e e.ui e, to %uppo t efficient on+chip an, off+ chip co!!unication fo both ope ation an, !anufactu ing te%t.
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AMBA AHB" ne# generation

Advanced High-performance Bus AMBA A#B i!ple!ent% the featu e% e.ui e, fo high+pe fo !ance( high cloc2 f e.uenc& %&%te!% inclu,ing: 5 bu %t t an%fe % 5 split transactions 5 %ingle+c&cle bu% !a%te han,ove 5 %ingle+cloc2 e,ge ope ation 5 non+t i%tate i!ple!entation 5 wi,e ,ata bu% configu ation% (678$29 bit%).
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AHB $omponents
AHB master AHB slave AHB ar%iter AHB decoder transfers initiator multi-master centrali&ed decoder

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AHB" general vie#" multi-master

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AHB Master

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AHB Slave

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AHB Slave" mu' data

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AHB" simple transfert

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AHB" #ait

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AHB" multiples transfers

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AHB" e'amples of transfers

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(ata %us" little endian

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(ata %us" %ig endian

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AHB" central ar%iter

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$entrali&ed Ar%itration

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Ar%itration

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AHB decoder

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AHB" decoding" e'ample

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AMBA ASB" old generation

Advanced System Bus

bu %t t an%fe % pipeline, t an%fe ope ation !ultiple bu% !a%te .

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ASB Master

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ASB Slave

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ASB decoder

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ASB ar%iter

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AMBA A)B

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A)B transferts

: ite t an%fe
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Rea, t an%fe
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A)B %ridge

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A)B Slave

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A)B" tri-state Bus availa%le depending on the implementation

#rite cycle

AHB

A)B

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A)B" tri-state Bus availa%le depending on the implementation

read cycle

AHB

A)B

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