PRIST UNIVERSITY ASOOR CAMPUS KUMBAKONAM

DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING

Year/sem

Date :

Sub.code & Title :

SL.NO 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 REG.NO 60122210001 60122210002 60122210003 60122210004 60122210005 60122210006 60122210007 60122210008 60122110006 60122110010 60122020009 6013221501 6013221502 6013221503 6013221505 6013221506 60122110005 NAME H.FAISAL AHAMED M.RAFIUDEEN T.SUMAN S.VENKATESH D.VETRIVEL N.VETRIVEL S.BANUPRIYA R.S.SUBASHINI R.VIVEKA G.PRABHAVATHY B.AKILA K.ALMAS ALI E.AZARUDEEN G .GANGADHARAN S.NAVEENRAJ J. VIVEK K.TAMILARASAN SIGNATURE

INTERNAL EXAMINER

EXTERNAL EXAMINER

PRIST UNIVERSITY

ASOOR CAMPUS KUMBAKONAM

DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING

Year/sem Sub.code Subject

: : :

Date

ALLOCATION OF MARKS

1. 2. 3. 4. 5.

CIRCUIT DIAGRAM / LOGIC DIAGRAM CONNECTION EXECUTION RESULT & GRAPH VIVA

30 30 20 10 10

TOTOL

100

INTERNAL EXAMINER

EXTERNAL EXAMINER

PRIST UNIVERSITY ASOOR CAMPUS KUMBAKONAM

DEPARTMENT OF COMPUTER SCIENCE ENGINEERING

Year/sem Sub.code Subject

SL.NO 1 2 3 4 5 6

: : :
REG.NO 60122110002 60122110003 60122110004 60122110007 60122110008 60122110009 G.CHITRA B.MARIYAPPAN B.SATHESHPRABU T.ANITHA L.SUGANYA M.BANUPRIYA NAME

Date

SIGNATURE

INTERNAL EXAMINER

EXTERNAL EXAMINER

PRIST UNIVERSITY ASOOR CAMPUS KUMBAKONAM

DEPARTMENT OF COMPUTER SCIENCE AND ENGINEERING

Year/sem Sub.code Subject

: : :

Date

ALLOCATION OF MARKS

1. 2. 3. 4. 5.

CIRCUIT DIAGRAM / LOGIC DIAGRAM CONNECTION EXECUTION RESULT & GRAPH VIVA

30 30 20 10 10

TOTOL

100

INTERNAL EXAMINER

EXTERNAL EXAMINER

PRIST UNIVERSITY ASOOR CAMPUS KUMBAKONAM

DEPARTMENT OF COMPUTER SCIENCE AND ENGINEERING SYLLABUS

Year/sem

Date :

Sub.code & Title :

1.To design and implementation of adders and subtractors using logic gates 2. To design and implementation of code converter using logic gates 3. To design and implementation of 4 bit binary adder / subtractor 4. To design and implementation of 2 bit magnitude comparator using logic gates 5. To design and implementation of parity checker / generator using logic gates 6. To design and implementation of multiplexer and demultiplexer using logic gates 7. To design and implementation of encoder and decoder using logic gates 8. To design and implementation of SISO , SIPO,PISO and PIPO shift registers using flip-flop 9. To construct and verification of 4 bit ripple counter 10. To design and implementation of asynchronous up/down counter

1.To design and implementation of adders and subtractors using logic gates

2. To design and implementation of code converter using logic gates

3. To design and implementation of 4 bit binary adder / subtractor

4. To design and implementation of 2 bit magnitude comparator using logic gates

5. To design and implementation of parity checker / generator using logic gates

6. To design and implementation of multiplexer and demultiplexer using logic gates

7. To design and implementation of encoder and decoder using logic gates

8. To design and implementation of SISO , SIPO,PISO and PIPO shift registers using flip-flop

9. To construct and verification of 4 bit ripple counter

10. To design and implementation of asynchronous up/down counter

PRIST UNIVERSITY ASOOR CAMPUS KUMBAKONAM

DEPARTMENT OF COMPUTER SCIENCE AND ENGINEERING QUESTIONS

Year/sem

Date :

Sub.code & Title :

1.To design and implementation of adders and subtractors using logic gates 2. To design and implementation of code converter using logic gates 3. To design and implementation of 4 bit binary adder / subtractor 4. To design and implementation of 2 bit magnitude comparator using logic gates 5. To design and implementation of parity checker / generator using logic gates 6. To design and implementation of multiplexer and demultiplexer using logic gates 7. To design and implementation of encoder and decoder using logic gates 8. To design and implementation of SISO , SIPO,PISO and PIPO shift registers using flip-flop

INTERNAL EXAMINER

EXTERNAL EXAMINER

PRIST UNIVERSITY ASOOR CAMPUS KUMBAKONAM

DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING

Year/sem

Date

Sub.code & title :

1. To construct and test the performance of fixed bias amplifier circuit using BJT. (a) Wave forms at input and output without bias (b) Measurement of gain. (c) Plot the frequency response 2. To design and construct BJT common emitter amplifier using voltage divider bias (self bias) with and without bypassed emitter resistor (a)Measurement of gain (b)plot the frequency response & determination of gain bandwidth protect 3. To design and construct BJT common collector amplifier using voltage Divider bias (self bias) (a) Measurement of gain (b) Plot the frequency response & determination of gain bandwidth protect. 4.To construct and test the performance of darlington amplifier using BJT (a) Measurement of gain and input resistance (b) Plot the frequency response & determination of gain bandwidth protect 5. To construct and test the performance of power supply circuit- Half wave Rectifier with simple capacitor filter (a) Plot the load regulation characteristics (b) Measurement of dc voltage under load and ripple factor

6. To construct and test the performance of power supply circuit- full wave Rectifier with simple capacitor filter (a) Plot the load regulation characteristics (b) Measurement of dc voltage under load and ripple factor

7. . To design and implementation of adders and subtractors using logic gates 8. To design and implementation of code converter using logic gates (a) Binary to gray (b) BCD to Excess-3 code 9. To design and implementation of 4 bit binary adder / subtractor 10. To design and implementation of 2 bit magnitude comparator using logic gates 11. To design and implementation of parity checker / generator using logic gates 12. To design and implementation of multiplexer and demultiplexer using logic gates 13. To design and implementation of encoder and decoder using logic gates 14. To design and implementation of SISO , SIPO,PISO and PIPO shift registers using flip-flop

INTERNAL EXAMINER

EXTERNAL EXAMINER

1. To construct and test the performance of fixed bias amplifier circuit using BJT. (a) Wave forms at input and output without bias (b) Measurement of gain. Plot the frequency response

2. To design and construct BJT common emitter amplifier using voltage divider bias (self bias) with and without bypassed emitter resistor (a)Measurement of gain (b)plot the frequency response & determination of gain bandwidth protect

3. To design and construct BJT common collector amplifier using voltage Divider bias (self bias) (a)Measurement of gain (b)Plot the frequency response & determination of gain bandwidth protect.

4.To construct and test the performance of darlington amplifier using BJT (a) Measurement of gain and input resistance (b) Plot the frequency response & determination of gain bandwidth protect

5. To construct and test the performance of power supply circuit- Half wave Rectifier with simple capacitor filter

(a) Plot the load regulation characteristics (b)Measurement of dc voltage under load and ripple factor

6. To construct and test the performance of power supply circuit- full wave Rectifier with simple capacitor filter (a)Plot the load regulation characteristics (b)Measurement of dc voltage under load and ripple factor 7. . To design and implementation of adders and subtractors using logic gates

8. To design and implementation of code converter using logic gates (a) Binary to gray (b) BCD to Excess-3 code

9. To design and implementation of 4 bit binary adder / subtractor

10. To design and implementation of 2 bit magnitude comparator using logic gates

11. To design and implementation of parity checker / generator using logic gates

12. To design and implementation of multiplexer and demultiplexer using logic gates

13. To design and implementation of encoder and decoder using logic gates

14. To design and implementation of SISO , SIPO,PISO and PIPO shift registers using flip-flop