552

IEEE ELECTRON DEVICE LETTERS, VOL. 21, NO. 12, DECEMBER 2000

Mismatch of MOSFET Small Signal Parameters Under Analog Operation

Roland Thewes, Carsten Linnenbank, Ute Kollmer, Stefan Burges, Ulrich Schaper, Ralf Brederlow, and Werner Weber
AbstractThe matching behavior of drain current and small signal parameters transconductance and differential output conductance of MOSFETs is investigated under typical analog operating conditions. Whereas for the normalized standard deviand the well known proportionality to ( ations of e ) 1 2 is obtained, the normalized standard deviation of clearly deviates from this width and length dependence. For this 1 2 is found. parameter, a proportionality to Index TermsAnalog, differential drain conductance, matching, mismatch, MOSFET, small signal parameters, transconductance.

I. INTRODUCTION ISMATCH of MOS devices is a limiting factor for the achievable accuracy in analog CMOS applications. In order to achieve sufficient yield, the matching behavior of active and passive devices has been extensively studied in the literature and must be considered in circuit design [1][10]. For MOS transistors, usually drain current ( ) [1][4], [10] and/or threshold voltage ( ) [5][8] mismatch are measured and modeled as a function of mismatch affected device parameters. In this paper, we focus on the matching behavior of the MOSFET small signal parameters transconductance and in particular differential drain conduc, which are very important analog tance device parameters. II. EXPERIMENTAL The devices used in this study originate from two different CMOS processes. More detailed process and device data are given in the figure captions. We consider the standard deviation , and of tranof the differences of the parameters , ]. sistor pairs normalized to their mean values [e.g., The transistor pairs are arranged in large arrays and measured using a recently published high precision array characterization and are detechnique [10]. The small signal parameters termined by numerical differentiation. Characterization is performed under typical analog operating conditions, i.e. in the sat. For each data point uration regime for low values of shown in the figures, at least 400 pairs are measured.
Manuscript received June 14, 2000; revised April 20, 2000. The review of this letter was arranged by Editor C. Wann. R. Thewes, R. Brederlow, and W. Weber are with Corporate Research, Infineon Technologies, D 81730 Munich, Germany (e-mail: roland.thewes@infineon.com) C. Linnenbank, U. Kollmer, and U. Schaper are with Corporate Front Ends, Infineon Technologies, D 81730 Munich, Germany. S. Burges is with Automotive and Industrial, Infineon Technologies, D81541 Munich, Germany. Publisher Item Identifier S 0741-3106(00)10820-1.

Fig. 1. Standard deviations (a)  I =I , (b) g =g , and (c)  g =g of p-MOS pairs as a function of W L (W L active device area). Process data: Supply voltage 5 V, minimum gate length 15 nm, n-well, buried 0.65 m, oxide thickness channel LDD p-MOS, surface channel LATID n-MOS. Geometries investigated 6/0.65, 12/0.65, 24/0.65, 6/1.3, 12/1.3, 24/1.3, 48/1.3, 12/2.6, W=L 24/2.6, 48/2.6. P-MOS: L L 140 nm, V 800 mV, n-MOS: L L 160 nm, V 620 mV. Characterization with V 1.0 V and V 2.5 V.

(1 2

) =

(1 )

0 = j j=

(1 ) ( 2

) =

0 j j=

j j=

j j=

III. RESULTS AND DISCUSSION In Fig. 1, measured values of the standard deviations of drain current, transconductance, and differential drain conductance of p-MOS devices with different geometries are shown. For and [Fig. 1(a) and (b)], we find the well known proporand to , tionalities of respectively. Characterization in the saturation regime at conbut with different values of yields similar values of stant and (not shown in these plots), i. e., the influence of the characterization drain voltage is small. The slopes of the straight lines in these plots ( matching constants and ) differ approximately by a factor of two. related to This can be easily explained by a simple quadratic approach for , which is approximately the drain current, valid under analog operating conditions even for modern processes [11]. In Fig. 2, these data are plotted again (combined with data for further characterization drain voltages), but now . As can be seen, the experimentally obas a function of tained relation

07413106/00$10.00 2000 IEEE

THEWES et al.: MOSFET SMALL SIGNAL PARAMETERS

553

Fig. 2. Standard deviation  g =g of p-MOS pairs as a function of W . Process data and geometries investigated as in Fig. 1. Characterization with V 1.0 V and V as given in the figure. Note that the data of Fig. 1(c) are included and that all data points coincide on a single straight line in this representation. Inset: schematic diagram showing the lateral electrical field (E ) in two transistors with different channel lengths operated in the low gate voltage saturation regime. Note that the velocity saturation length (L ), amount and shape of the lateral field in the velocity saturation region, and ) are approximately thus also the maximum lateral field close to drain (E independent of the channel length [11].

j j=

(1 j j

Fig. 3. Same plot as in Fig. 2 but for different operating points, different processes, and n- and p-MOS pairs. : Same process and same devices as in 1.5 V and V 2.5 V; n-MOS data Fig. 2, but characterized at V from same process as in Figs. 1 and 2, characterized at V 1 V and V 2.5 V; : n-MOS devices from a 3.3 V process with minimum gate length 7.5 nm, n-well, surface channel LDD p- and 0.35 m, oxide thickness L 110 nm, V 450 mV. n-MOS. Further n-MOS device data: L Geometries investigated W=L 4.4/0.35, 8.8/0.35, 17.6/0.35, 4.4/0.7, 8.8/0.7, 17.6/0.7, 8.8/1.3, 17.6/1.3, and 35.2/1.3. Characterization with V 0.65 V and V 1.65 V.

j j=

j j=

= =

is well suited to describe the matching behavior of the differbeing a characteriential output conductance with zation gate voltage dependent matching constant related to the (cf. Fig. 3, symbol). Furthermore, the impact parameter on is small. As shown in Fig. 3, these of findings are also valid for different gate voltages, for n-MOS devices, and for different processes.Using and the Gaussian law of error propagation, and is obtained. These relations predict a factor of 2 between and . This result approximately holds, although contributions of further mismatch affected device parameters (e.g., current factor and mobility reduction parammismatch is known to be the eter [2]) are neglected, since mismatch in the considered most important contribution to operating regime [1][8], [10]. In case of the drain conductance [Fig. 1(c)], for each particular channel length the data result in a straight line whose . Large deviations slope strongly increases with increasing occur for devices with equal active area but of , so that an analogy to the matching behavior of different and concerning the active device area dependence is obviously not given. A qualitative explanation for these findings is given in the following: The geometry dependence of the normalized stan, , and results from the fact, that the dard deviations of considered parameters are influenced by effects which are distributed over the whole active area of the transistor (e.g., doping variations, etc.) [1][8]. The absolute value of the standard deviation of these effects is proportional to the square root of this area so that its normalized value (obtained after division through . The parameter the area) is proportional to strongly depends on the lateral electrical field in the high field region between drain and pinch-off point. The channel potential at the pinch-off point, the length of the pinch-off region, and thus under the also the lateral electrical field are independent of considered operating conditions (inset in Fig. 2) [11]. Device pa-

rameter variations of the parameters which determine this field are located in a volume close to the drain junction (e.g., doping gradient in the transition regime between drain and channel region). The normalized standard deviation of these parameters is proportional to the square root of the reciprocal value of this volume. Since this volume is proportional to , but is not a , the relation is plaufunction of sible. REFERENCES
[1] M. Pelgrom, A. Duinmaijer, and A. P. G. Welbers, Matching properties of MOS transistors, IEEE J. Solid-State Circuits, vol. 24, pp. 14331440, 1989. [2] J. Bastos et al., Mismatch characterization of small size MOS transistors, in Proc. Int. Conf. Microelectronic Test Structures (ICMTS), 1995, pp. 271276. [3] J. Oehm and K. Schumacher, Quality assurance and upgrade of analog characteristics by fast mismatch analysis option in network analysis environment, IEEE J. Solid-State Circuits, vol. 28, pp. 865871, 1993. [4] H. Tuinhout, A. Montree, J. Schmitz, and P. Stolk, Effects of gate depletion and boron penetration on matching of deep submicron CMOS transistors, in IEDM Tech. Dig., 1997, pp. 631634. [5] K. R. Lakshmikumar, R. A. Hadaway, and M. A. Copeland, Characterization and modeling of mismatch in MOS transistor for precision analog design, IEEE J. Solid-State Circuits, vol. SC21, pp. 10571066, 1986. [6] P. Stolk, F. Widdershoven, and D. Klaassen, Modeling statistical dopant fluctuations in MOS transistors, IEEE Trans. Electron Devices, vol. 45, pp. 19601971, 1998. [7] T. Mizuno, J. Okamura, and A. Toriumi, Experimental study of the threshold voltage fluctuation due to statistical variation of channel dopant number in MOSFETs, IEEE Trans. Electron Devices, vol. 41, pp. 22162221, 1994. [8] C. G. Linnenbank et al., What do matching results of medium area MOSFETs reveal for large area devices in typical analog applications?, in Proc. Eur. Solid-State Device Research Conf., 1998, pp. 104107. [9] R. Thewes et al., Explanation and quantitative model for the matching behavior of poly-silicon resistors, in IEDM Tech. Dig., 1998, pp. 771774. [10] R. Thewes et al., On the matching behavior of MOSFET small signal parameters, in Proc. Int. Conf. Microelectronic Test Structures, 2000, pp. 137141. [11] P. K. Ko, Approaches to scaling, in Advanced MOS Device Physics, N. G. Einspruch, Ed. New York: Academic, 1989.