Low-Power Pulse-Triggered Flip-Flop Design with Conditional Pulse-Enhancement Scheme

AIM: The main aim of the project is to design and implement Low-Power PulseTriggered Flip-Flop Design with Conditional Pulse-Enhancement Scheme!" A#ST$ACT: In this paper, a novel low-power pulse-triggered flip-flop (FF) design is presented. First, the pulse generation control logic, an AN transistor AN function, is removed from the critical path to facilitate a faster discharge operation. A simple twogate design is used to reduce the circuit comple!it". #econd, a conditional pulse-enhancement techni$ue is devised to speed up the discharge along the critical path onl" when needed. As a result, transistor si%es in dela" inverter and pulse-generation circuit can &e reduced for power saving. 'arious postla"out simulation results &ased on ()* *)+# ,--nm technolog" reveal that the proposed design features the &est power-dela"-product performance in seven FF designs under comparison. Its ma!imum power saving against rival designs is up to ./.01. *ompared with the conventional transmission gate-&ased FF design, the average lea2age power consumption is also reduced &" a factor of ..34.

Proposed Method: In this paper low-power pulse-triggered flip-flop (FF) was implemented using ()* ,- 5nm further we can implement with lower technolog" li&rar". Further we
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can appl" low power techni$ues to reduce static power. 6ven though area increases.

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Fig7 *onventional pulse-triggered FF designs. (a) ip- *+. (&) )899F. (c) #**6:.

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Fig7 #chematic of the proposed ;-FF design with pulse control scheme.

T%%LS: hspice<vA-4--/.-., t-spice APPLICATI%( AD)A(TA'ES: The proposed design e!cels rival designs in performance inde!es such as power, <-to-< dela", and ; ;. *oupled with these design merits is a longer hold-time re$uirement inherent in pulse-triggered FF designs. The hold-time violations are much easier to fi! in circuit design compared with the failures in speed or power.

$EFE$E(CES: 8. =awaguchi and T. #a2urai, >A reduced cloc2-swing flip-flop (:*#FF) for ?.1 power reduction,@ IEEE J. Solid-State Circuits, vol. .., no. 3, pp. /-A5/BB. A. C. ). #trollo, . e *aro, 6. Napoli, and N. ;etra, >A novel high speed

sense-amplifier-&ased flip-flop,@ IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. B., no. BB, pp. B4??5B4A0.
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 8. ;artovi, :. Durd, (. #alim, F.Ee&er, 9. Tech. Dig. ISSCC, pp. B./5B.,. F. =lass, *. Amir, A.

iCregorio, and

raper,

>Flow-through latch and edge-triggered flip-flop h"&rid elements,@ in IEEE

as, =. Aingaran, *. Truong, :.Eang, A. )ehta, :.

8eald, and C.Fee, >A newfamil" of semi-d"namic and d"namic flip flops with em&edded logic for high-performance processors,@ IEEE J. Solid-State Circuits, vol. .0, no. 3, pp. AB45AB?. #. . Naff%iger, C. *olon-Donet, T. Fischer, :. :iedlinger, T. G. #ullivan,

and T. Crut2ows2i, >The implementation of the Itanium 4 microprocessor,@ IEEE J. Solid-State Circuits, vol. .A, no. BB, pp. B00/5B0?-.

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