Low Power VLSI Circuit Design with Efficient HDL Coding AIM: The main aim of the project

is to design Low Power VLSI Circuit Design with Efficient HDL Coding. ABS !AC : In this paper, four-bit unsigned up counter with an asynchronous clear and a clock enable is designed in Xilinx ISE !"# and implemented on high performance $irtex-% &'(), X*%$+X#!,T de-ice, - speed grade, &&( .% package and /+%,. board" 0ser constraints file 1ucf2 and net list constraints design 1ncd2 file are taken into consideration with X'ower !"# for power consumption analysis" 3e take two codes" 4ur first code maps the clock enable signal to +0Ts then the power consumption is 5"!#5 3att" 4ur second code maps the clock enable signal to control ports then the power consumption is 5"%#. 3att" 6y changing mapping style, we reduce %7 power reduction and also reduce number of +0T and 8 flipflop used in implementation leads to area efficient design" 6y efficiently mapping, we reduce power consumption in multiple of power reduction with single statements" The experimental result shows the power analysis of both 98+ mapping code" ""LS: Xilinx :"#ISE, /odelsim%"!c" APPLICA I"# ADVA# A$ES: IS" %&&': (&&) Certified Co*+,nManager) V. Malli karjuna (Project

08297578555, 09640648777

 'ower consumption is directly proportional to number of elements used in reali;ation of 98+ code on &'()" This is the main reason behind reduction in power consumption when we change the mapping of clock enable from control port to +0Ts input" This reduction in number of basic element in net list translated to reduction in power consumption from 5"%#.3 1in case )2 to 5"!<53 1in case 62" !E.E!E#CES: 6haktha-atchalu, => 8eepthy, ("=" > $idhya, S" > ?isha, $", @8esign and analysis of low power open core protocol compliant interface using $98+A, International *onference on Emerging Trends in Electrical and *omputer Technology 1I*ETE*T2, pp"%# -%#." =anganathan, ?"> ?amballa, ="> 9anchate, ?", @*9ESSB a comprehensi-e tool for *8&( extraction and synthesis of low power designs from $98+A, IEEE *omputer Society )nnual Symposium on Emerging $+SI Technologies and )rchitectures" 8eepak Cumar, 'ankaj Cumar, /anisha 'attanaik, A'erformance analysis of :,nm +ook 0p Table1+0T2 for +ow 'ower )pplicationsA, 5th Euromicro *onference 4n 8igital System 8esign )rchitectures, /ethods and Tools , +ille, &rance, -5"

IS" %&&': (&&) Certified Co*+,nManager)

V. Malli karjuna (Project

08297578555, 09640648777

 4rtega-*isneros, S"> =aygo;a-'anduro, D"D"> Suardia; /uro, D"> 6oemo, E", A=apid prototyping of a self-timed )+0 with &'()sA International *onference on =econfigurable *omputing and &'()s,pp" #%-55" A&'() power management design techniEuesA, www"xilinx"com

IS" %&&': (&&) Certified Co*+,nManager)

V. Malli karjuna (Project

08297578555, 09640648777