Course Code : MCS-012 Course Title : Problem Solving and Programming Assignment Number : BCA(I1)/011/Assign/12 Maximum Marks : 100

Weightage : 25% Last Dates for Submission : 15th October, 2012 (For July 2012 Session) 15th April, 2013 (For January 2013 Session)

Question 1 (covers Block 1) (a) Perform the following arithmetic operations using binary signed 2s complement notation for integers. You may assume that the maximum size of integers is of 12 bits including the sign bit. (Please note that the numbers given here are in decimal notation) (3 Marks) i) Add 512 and 298 ii) Subtract 512 from 64 ii) Add 1025 and 1023 Please indicate the overflow if it is occurs. (b) Convert the hexadecimal number: AB CD EF into binary, octal and decimal equivalent. Ans:-Convert into binary no. A=1010 B=1011 C=1100 D=1101 E=1110 F=1111 Convert to Hexa decimal (ABCDEF)16=(101010111100110111101111)2 Convert into decimal:Ax16^0+Bx16^1|+Cx16^2+Dx16^3+Ex16^4+Fx16^5 10x16+11x16^1+12x16^2+13x16^3+14x16^4+15x16^5 10+176+3072+53248+917504+15728640 =(16782650)2

Convert into octal:A B C D 1010 1011 1100 Regroup it into 3 digit 101 010 111 100

F 1101 1110 1111 110 111 101 111

Now place equivalent octal number 4 2 7 3 6 7 =(42736747)8

(c) Convert the following string into equivalent UTF 8 code Copyright sign is and you must check it prior to using copyrighted material. Are these codes same as that used in ASCII?

(d) Design a logic circuit that takes a four digit binary input, counts the number of 1s in it, and produces it as the output. For example, if the input is 1101, then output will be 11 (as there are three ones in the input). Draw the truth table and use K-map to design the Boolean expressions for each of the output bits. Draw the resulting circuit diagram using AND OR NOT gates.

Ans:-

(d) Design a two bit counter (a sequential circuit) that counts as 0, 2, 0, 2... and so on. You should show the state table, state diagram, the k-map for circuit design, logic diagram of the resultant design using D flip-flop.

Ans:-

(f) Design a floating point representation of 16 bits closer to IEEE 754 format. The number should have a biased exponent of 5 bits. You may assume that the mantissa is in normalised form; the exponent bias of 15; and one bit is used for the sign bit in the mantissa. Represent the number (24.125) 10 using this format ans:-

Question 2 (covers Block 2) (a) A RAM has a capacity of 32 K 16. (2 Marks) (i) How many data input and data output lines does this RAM need to have? Ans:-64, since the word size is 64. (ii) How many address lines will be needed for this RAM? Ans:-32K = 32 1024 = 32768 words. Hence, there are 32768 memory addresses. Since 65536 = 216 it requires 16 bits address code to specify one of 32768 addresses. (b) Consider a RAM of 512 words with a word size of 32 bits. Assume that this memory have a cache memory of 8 Blocks with block size of 64 bits. For the given memory and Cache in the statements as above, draw a diagram to show the address mapping of RAM and Cache, if two way set associative memory to cache mapping scheme is used. Ans:-Main memory Size = 64 Words Main Memory word size = 16 bits Cache Memory Size = 8 Blocks Cache Memory Block size = 32 words Block of Cache = 2 Words of RAM 1 Memory location address 25 is equivalent to Block address 12. Total number of possible Blocks in Main Memory = 64/2 = 32 blocks
(i) Associative Mapping: The block can be anywhere in the cache. (ii) Direct Mapping: Size of Cache = 8 blocks Location of Block 12 in Cache = 12 modulo 8 = 4 (iii) 2 Way set associative mapping: Number of blocks in a set = 2 Number of sets = Size of Cache in blocks / Number of blocks in a set =8/2=4 Block 12 will be located anywhere in (12 modulo 4) set, that is set 0.

(c) Explain which of the Input/output techniques that will be used for the following operations. Also explain the I/O techniques.

(i) Reading data from a keyboard (ii) Reading data from a file. Ans:-(i) Reading data from a Keyboard In computing, input/output or I/O is the communication between an information processing system (such as a computer) and the outside world, possibly a human or another information processing system. Inputs are the signals or data received by the system, and outputs are the signals or data sent from it. The term can also be used as part of an action; to "perform I/O" is to perform an input or output operation. I/O devices are used by a person (or other system) to communicate with a computer. For instance, a keyboard or a mouse may be an input device for a computer, while monitors and printers are considered output devices for a computer. Devices for communication between computers, such as modems and network cards, typically serve for both input and output. Note that the designation of a device as either input or output depends on the perspective. Mouse and keyboards take as input physical movement that the human user outputs and convert it into signals that a computer can understand. The output from these devices is input for the computer. Similarly, printers and monitors take as input signals that a computer outputs. They then convert these signals into representations that human users can see or read. For a human user the process of reading or seeing these representations is receiving input. These interactions between computers and humans is studied in a field called human-computer interaction. In computer architecture, the combination of the CPU and main memory (i.e. memory that the CPU can read and write to directly, with individual instructions) is considered the brain of a computer, and from that point of view any transfer of information from or to that combination, for example to or from a disk drive, is considered I/O. The CPU and its supporting circuitry provide memory-mapped I/O that is used in low-level computer programming, such as the implementation of device drivers. An I/O algorithm is one designed to exploit locality and perform efficiently when data reside on secondary storage, such as a disk drive. Interface An I/O interface is required whenever the I/O device is driven by the processor. The interface must have necessary logic to interpret the device address generated by the processor. Handshaking should be implemented by the interface using appropriate commands (like BUSY, READY, and WAIT), and the processor can communicate with an I/O device through the interface. If different data formats are being exchanged, the interface must be able to convert serial data to parallel form and vice-versa. There must be provision for generating interrupts and the corresponding type numbers for further processing by the processor if required. A computer that uses memory-mapped I/O accesses hardware by reading and writing to specific memory locations, using the same assembly language instructions that computer would normally use to access memory. Higher-level implementation Higher-level operating system and programming facilities employ separate, more abstract I/O concepts and primitives. For example, most operating systems provide application programs with the concept of files. The C and C++ programming languages, and operating systems in the Unix family, traditionally abstract files and devices as streams, which can be read or written, or sometimes both. The C standard library provides functions for manipulating streams for input and output. In the context of the ALGOL 68 programming language, the input and output facilities are collectively referred to as transput. The ALGOL 68 transput library recognizes the following standard files/devices: stand in, stand out, stand errors and stand back.

d) Find the average disk access time that reads or writes a 1024 byte sector. Assume that the disk rotates at 18000 rpm; each track of the disk has 128 sectors and data transfer rate of the disk is 100 MB/second. (Please calculate data transfer time, assume a suitable seek time and calculate the average latency time). Ans:-

(e) What is the purpose of FAT in Windows? What construct do you use in Linux/Unix instead of FAT? Explain the differences between the two. Ans:-The FAT maps the usage of data space of the disk. It contains information about the space used by each individual file, the unused disk space and the space that is unusable due to defects in the disk. Since FAT contains vital information, two copies of FAT are stored on the disk, so that in case one gets destroyed, the other can be used. A FAT entry can contain any of the following: unused cluster reserved cluster bad cluster last cluster in file next cluster number in the file.
In the UNIX system, the information related to all these fields is stored in an Inode table on the disk. For each file, there is an inode entry in the table. Each entry is made up of 64 bytes and contains the relevant details for that file. These details are: a) Owner of the file b) Group to which the Owner belongs c) File type d) File access permissions e) Date & time of last access f) Date & time of last modification g) Size of the file h) No. of links i) Addresses of blocks where the file is physically present.

(f) Define each of the following term. Explain the main purpose / use / advantage. (Word Limit for answer of each part is 50 words ONLY) (i) ZBR in the context of disks (ii) SCSI (iii) Colour Depth (iv) Graphics Accelerators (v) Monitor Resolution (vi) Active matrix display Ans:- (i) ZBR in the context of disks The inner tracks are packed as densely as the particular drive's technology allows, but with a CAV drive the data on the outer tracks are less densely packed. Using ZBR

the drive divides all the tracks into a number of zones, and the inner track of each zone is packed as densely as it can, with the other tracks in that same zone recorded with the same read/write rate. This permits the drive to have more bits stored in each track outside of the innermost zone than drives not using this technique. Storing more bits per track equates to achieving a higher total data capacity on the same disk area. On a hard disk using ZBR, the data on the tracks in the outer most zone will have the highest data transfer rate. Since both hard disks and floppy disks typicallly number their tracks beginning at the outer edge and continuing inward, and since operating systems typically fill the lowest-numbered tracks first, this is where the operating system typically stores its own files during its initial installation onto an empty drive. Testing disk drives when they are new or empty after defragmenting them with some benchmarking applications will often show their highest performance. After some time, when more data is stored in the inner tracks, the average data transfer rate will drop, because the transfer rate in the inner zones is slower; often making people think their disk drive is slowing down over time. Some other ZBR drives, such as the 800 kilobyte 3.5" floppy drives in the Apple IIGS and older Macintosh computers, don't change the data rate but rather spin the medium faster when reading or writing outer tracks, thus approximating constant linear velocity drives (ii) SCSI Small Computer System Interface (SCSI, is a set of standards for physically connecting and transferring data between computers and peripheral devices. The SCSI standards define commands, protocols, and electrical and optical interfaces. SCSI is most commonly used for hard disks and tape drives, but it can connect a wide range of other devices, including scanners and CD drives, although not all controllers can handle all devices. The SCSI standard defines command sets for specific peripheral device types; the presence of "unknown" as one of these types means that in theory it can be used as an interface to almost any device, but the standard is highly pragmatic and addressed toward commercial requirements. SCSI is an intelligent, peripheral, buffered, peer to peer interface. It hides the complexity of physical format. Every device attaches to the SCSI bus in a similar manner. Up to 8 or 16 devices can be attached to a single bus. There can be any number of hosts and peripheral devices but there should be at least one host. SCSI uses handshake signals between devices, SCSI-1, SCSI-2 have the option of parity error checking. Starting with SCSI-U160 (part of SCSI-3) all commands and data are error checked by a CRC32 checksum. The SCSI protocol defines communication from host to host, host to a peripheral device, peripheral device to a peripheral device. However most peripheral devices are exclusively SCSI targets, incapable of acting as SCSI initiatorsunable to initiate SCSI transactions themselves. Therefore peripheral-to-peripheral communications are uncommon, but possible in most SCSI applications. The Symbios Logic 53C810 chip is an example of a PCI host interface that can act as a SCSI target. (iii) Colour Depth color depth or bit depth is the number of bits used to indicate the color of a single pixel in a bitmapped image or video frame buffer. This concept is also known as bits per pixel (bpp), particularly when specified along with the number of bits used. Higher color depth gives a broader range of distinct colors. Color depth is only one aspect of color representation, expressing how finely levels of color can be expressed; the other aspect is how broad a range of colors can be expressed (iv)Graphics Accelerators Graphics accelerators have their own memory, which is reserved for storing graphical representations. The amount of memory determines how much resolution and how many colors can be displayed. Some accelerators use conventional DRAM, but others use a special type of video RAM (VRAM), which enables both the video circuitry and the processor to simultaneously access the memory. bus : Each graphics accelerator is designed for a particular type of video bus. As of 1995, most are designed for the PCI bus. register width: The wider the register, the more data the processor can manipulate with each

instruction. 64-bit accelerators are already becoming common, and we can expect 128-bit accelerators in the near future. (v) Monitor Resolution The display resolution of a digital television or display device is the number of distinct pixels in each dimension that can be displayed. It can be an ambiguous term especially as the displayed resolution is controlled by all different factors in cathode ray tube (CRT), flat panel or projection displays using fixed picture-element (pixel) arrays. It is usually quoted as width height, with the units in pixels: for example, "1024 768" means the width is 1024 pixels and the height is 768 pixels. This example would normally be spoken as "ten twenty-four by seven sixty-eight" or "ten twenty-four by seven six eight". One use of the term "display resolution" applies to fixed-pixel-array displays such as plasma display panels (PDPs), liquid crystal displays (LCDs), digital light processing (DLP) projectors, or similar technologies, and is simply the physical number of columns and rows of pixels creating the display (e.g., 1920 1080). A consequence of having a fixed-grid display is that, for multi-format video inputs, all displays need a "scaling engine" (a digital video processor that includes a memory array) to match the incoming picture format to the display. Note that the use of the word resolution here is a misnomer, though common. The term "display resolution" is usually used to mean pixel dimensions, the number of pixels in each dimension (e.g., 1920 1080), which does not tell anything about the resolution of the display on which the image is actually formed: resolution properly refers to the pixel density, the number of pixels per unit distance or area, not total number of pixels. In digital measurement, the display resolution would be given in pixels per inch. In analog measurement, if the screen is 10 inches high, then the horizontal resolution is measured across a square 10 inches wide. This is typically stated as "lines horizontal resolution, per picture height; for example, analog NTSC TVs can typically display about 340 lines of "per picture height" horizontal resolution from over-the-air sources, which is equivalent to about 440 total lines of actual picture information from left edge to right edge (vi) Active matrix display Alternatively referred to as Thin Film Transistor (TFT) and Active-matrix LCD (AMLCD), an active-matrix display is a liquid crystal display (LCD) first introduced with the IBM ThinkPad in 1992. With activematrix displays, each pixel is controlled by one to four transistors that can make the screen faster, brighter, more colorful than passive-matrix, and capable of being viewed at different angles. Because of this improved technology, active-matrix screens are often more expensive, but better quality than a passive matrix display. While active-matrix displays do have a crisp display because each pixel has its own transistor, you will find that when running off a battery that the power drains faster. Also, because of the number of transistors, there is more of an opportunity fordead pixels.

Question 3 (Covers Block 3) (a) Assume that a new machine has been developed which has only 16 general purpose registers, but have a big high speed RAM. The machine uses stack for procedure calls. The machine is expected to handle all the object oriented languages. List four addressing modes that must be supported by such a machine. Give justification of the selection of each of the addressing modes. Ans:-A stack machine implements a stack with registers. The operands of the arithmetic logic unit (ALU) are always the top two registers of the stack and the result from the ALU is stored in the top register of the stack. 'Stack machine' commonly refers to computers which use a Last-in, First-out stack to hold short-lived temporary values while executing individual program statements. The instruction set carries out most ALU actions with postfix (Reverse Polish notation) operations that work only on the expression

stack, not on data registers or main memory cells. For a typical instruction like Add, both operands implicitly come from the topmost (most recent) values of the stack, and those two values get replaced by the result of the Add. The instruction's operands are 'popped' off the stack, and its result(s) are then 'pushed' back onto the stack, ready for the next instruction. Most stack instructions are encoded as just an opcode, with no additional fields to specify a register number or memory address or literal constant. This encoding is easily extended to richer operations with more than two inputs or more than one result. Integer constant operands are pushed by separate Load Immediate instructions. Very Compact Object Code Stack machines have much smaller instructions than the other styles of machines. But operand loads are separate and so stack code requires roughly twice as many instructions as the equivalent code for register machines. The total code size (in bytes) is still less for stack machines. In stack machine code, the most frequent instructions consist of just an opcode and can easily fit in 6 bits or less. Branches, load immediates, and load/store instructions require an argument field, but stack machines often arrange that the frequent cases of these still fit together with thin opcode into a single byte or syllable. The selection of operands from prior results is done implicitly by the ordering of the stack ops. In contrast, register machines require two or three register-number fields per ALU instruction to select its operands; the densest register machines average about 16 bits per instruction. The instructions for accumulator or memory-to-memory machines are not padded out with multiple register fields. Instead, they use compiler-managed anonymous variables for subexpressionvaluesSimple Compilers Compilers for stack machines are simpler and quicker to build than compilers for other machines. Code generation is trivial and independent of prior or subsequent code. It can be easily integrated into the parsing pass. No register management is needed, and no optimizations for constants or repeated simple memory references are needed (or even allowed). The same opcode that handles the frequent common case of Add, Indexed Load, or Function Call will also handle the general case involving complex subexpressions and nested calls. The compiler and the machine need not deal separately with corner cases. This simplicity has allowed compilers to fit onto very small machines. Minimal Processor State A machine with an expression stack can get by with just two visible registers, the top-of-stack address and the next-instruction address. The minimal hardware implementation has few bits of flipflops or registers. Faster implementations buffer the topmost N stack cells into invisible temp registers to reduce memory stack cycles. Responding to an interrupt involves pushing the visible registers and branching to the interrupt handler. More Memory References Some in the industry believe that stack machines execute more data cache cycles for temporary values and local variables than do register machines. On stack machines, temporary values often get spilled into memory, whereas on machines with many registers these temps usually remain in registers. (However, these values often need to be spilled into "activation frames" at the end of a procedure's definition, basic block, or at the very least, into a memory buffer during interrupt processing). Values spilled to memory add more cache cycles. This spilling effect depends on the number of hidden registers used to buffer top-of-stack values, upon the frequency of nested procedure calls, and upon host computer interrupt processing rates. Some simple stack machines or stack interpreters use no top-ofstack hardware registers. Those minimal implementations are always slower than standard register machines. A typical expression like X+1 compiles to 'Load X; Load 1; Add'. This does implicit writes and reads of the memory stack which weren't needed: Load X, push to memory Load 1, push to memory Pop 2 values from memory, add, and push result to memory for a total of 5 data cache references.

The next step up from this is a stack machine or interpreter with a single top-of-stack register. The above code then does: Load X into empty TOS register (if hardware machine), or Push TOS register to memory, Load X into TOS register (if interpreter) Push TOS register to memory, Load 1 into TOS register Pop left operand from memory, add to TOS register and leave it there for a total of 5 data cache references, worst-case. Generally, interpreters don't track emptiness, because they don't have to anything below the stack pointer is a non-empty value, and the TOS cache register is always kept hot. Factoring Out Common Subexpressions Has High Cost In register machines, a subexpression which is used multiple times with the same result value can be evaluated just once and its result saved in a fast register. The subsequent reuses have no time or code cost, just a register reference that would have happened anyhow. This optimization wins for common simple expressions (e.g. loading variable X or pointer P) as well as less-common complex expressions. With stack machines, in contrast, the results of a subexpression can be stored in one of two ways. The first way involves a temporary variable in memory. Storing and subsequent retrievals cost additional instructions and additional data cache cycles. Doing this is only a win if the subexpression computation costs more in time than fetching from memory, which in most stack CPUs, almost always is the case. Rigid Code Order In modern machines, the time to fetch a variable from the data cache is often several times longer than the time needed for basic ALU operations. A program runs faster without stalls if its memory loads can be started several cycles before the instruction which needs that variable, while also working on independent instructions. Complex machines can do that with a deep pipeline and "out-of-order execution" that examines and runs many instructions at once. Register machines can[1a]lso do this with much simpler "in-order" hardware, a shallow pipeline, and slightly smarter compilers. 3 The load step becomes a separate instruction, and that instruction is statically scheduled much earlier in the code sequence. The compiler puts independent steps in between.. Hides a Faster Register Machine Inside Some simple stack machines have a chip design which is fully customized all the way down to the level of individual registers. The top of stack address register and the N top of stack data buffers are built from separate individual register circuits, with separate adders and ad hoc connections. However, most stack machines are built from larger circuit components where the N data buffers are stored together within a register file and share read/write buses. The decoded stack instructions are mapped into one or more sequential actions on that hidden register file. Loads and ALU ops act on a few topmost registers, and implicit spills and fills act on the bottommost registers. The decoder allows the instruction stream to be compact.

(b) Assume a hypothetical machine that has only PC, AC, MAR, IR, DR and Flag registers. (You may assume the roles of these registers same as that are defined in general for a von Neumann machine) The instructions of this machine can take two operands - one the operand of these must be a register operand. It has an instruction: SUB AC, X; // it performs the operation AC AC Content of location X. Write and explain the sequence of micro-operations that are required to fetch and execute the instruction. Make and state suitable assumptions, if any. Ans:-Program counter or PC: The program counter, or PC (also called the instruction pointer to a seminal Intel instruction set, such as the 8080 or 4004, or instruction address register, or just part of the instruction sequencer in some computers) is a processor register that indicates where the computer is in its instruction sequence. Depending on the details of the particular computer, the PC holds either the address of the instruction being executed, or the address of the next instruction to be executed. In most processors, the program counter is incremented automatically after fetching a program instruction, so

that instructions are normally retrieved sequentially from memory, with certain instructions, such as branches, jumps and subroutine calls and returns, interrupting the sequence by placing a new value in the program counter. Such jump instructions allow a new address to be chosen as the start of the next part of the flow of instructions from the memory. They allow new values to be loaded (written) into the program counter registerA subroutine return is then achieved by writing the saved value back in to the program counter again. Accumulator (AC): In a computer's central processing unit (CPU), an accumulator is a register in which intermediate arithmetic and logic results are stored. Without a register like an accumulator, it would be necessary to write the result of each calculation (addition, multiplication, shift, etc.) to main memory, perhaps only to be read right back again for use in the next operation. Access to main memory is slower than access to a register like the accumulator because the technology used for the large main memory is slower (but cheaper) than that used for a register. The canonical example for accumulator use is summing a list of numbers. The accumulator is initially set to zero, then each number in turn is added to the value in the accumulator. Only when all numbers have been added is the result held in the accumulator written to main memory or to another, non-accumulator, CPU register. An accumulator machine, also called a 1-operand machine, or a CPU with accumulator-based architecture, is a kind of CPU in whichalthough it may have several registersthe CPU always stores the results of most calculations in one special registertypically called "the" accumulator of that CPU. Historically almost all early computers were accumulator machines; and many microcontrollers still popular as of 2010 (such as the 68HC12, the PIC micro, the 8051 and several others) are basically accumulator machines. Modern CPUs are typically 2-operand or 3-operand machinesthe additional operands specify which one of many general purpose registers (also called "general purpose accumulators"[1]) are used as the source and destination for calculations. These CPUs are not considered "accumulator machines". The characteristic which distinguishes one register as being the accumulator of acomputer architecture is that the accumulator (if the architecture were to have one) would be used as an implicit operand for arithmetic instructions. For instance, a CPU might have an instruction like: ADD memaddress This instruction would add the value read from the memory location at memaddressto the value from the accumulator, placing the result in the accumulator. The accumulator is not identified in the instruction by a register number; it is implicit in the instruction and no other register can be specified in the instruction. Some architectures use a particular register as an accumulator in some instructions, but other instructions use register numbers for explicit operand specification. MAR: The Memory Address Register (MAR) is a CPU register that either stores the memory address from which data will be fetched to the CPU or the address to which data will be sent and stored. In other words, MAR holds the memory location of data that needs to be accessed. When reading from memory, data addressed by MAR is fed into the MDR (memory data register) and then used by the CPU. When writing to memory, the CPU writes data from MDR to the memory location whose address is stored in MAR. The Memory Address Register is half of a minimal interface between a microprogram and computer storage. The other half is a memory data register. Far more complex memory interfaces exist, but this is the least that can work. IR (Instruction register): Instruction register is the part of a CPU's control unit that stores the instruction currently being executed or decoded. In simple processors each instruction to be executed is loaded into the instruction register which holds it while it is decoded, prepared and ultimately executed, which can take several steps. More complicated processors use a pipeline of instruction registers where each stage of the pipeline does part of the decoding, preparation or execution and then passes it to the next stage for its step. Modern processors can even do some of the steps of out of order as decoding on several instructions is done in parallel. Decoding the opcode in the instruction register includes determining the instruction,

determining where its operands are in memory, retrieving the operands from memory, allocating processor resources to execute the command (in superscalar processors), etc DR: Data registers are used to hold numeric values such as integer and floating-point values. In some older and low end CPUs, a special data register, known as the accumulator, is used implicitly for many operations. Flag Registers: The FLAGS register is the status register in Intel x86 microprocessors that contains the current state of the processor. This register is 16-bits wide. Its successors, the EFLAGS and RFLAGS registers are 32-bits and 64-bits wide, respectively. The wider registers retain compatibility with their smaller predecessors Steps for instruction execution Step 1: The first step of instruction execution is to fetch the instruction that is to be executed. To do so we require: Address of the "instruction to be fetched". Normally Program counter (PC) register stores this information. Now this address is converted to physical machine address and put on address bus with the help of a buffer register sometimes called Memory Address Register (MAR). This, coupled with a request from control unit for reading, fetches the instruction on the data bus, and transfers the instruction to Instruction Register (IR). On completion of fetch PC is incremented to point to the next instruction. In Step 2: The IR is decoded; let us assume that Instruction Register contains an instruction. ADD Memory location B with general purpose register R1 and store result in R1, then control unit will first instruct to: Get the data of memory location B to buffer register for data (DR) using buffer address register (MAR) by issuing Memory read operation. This data may be stored in a general purpose register, if so needed let us say R2 Now, ALU will perform addition of R1 & R2 under the command of control unit and the result will be put back in R1. The status of ALU operation for example result in zero/non zero, overflow/no overflow etc. is recorded in the status register.

Similarly, the other instructions are fetched and executed using ALU and register under the control of the Control Unit The number and the nature of registers is a key factor that differentiates among computers. For example, Intel Pentium has about 32 registers. Some of these registers are special registers and others are general-purpose registers. Some of the basic registers in a machine are: All von-Neumann machines have a program counter (PC) (or instruction counter IC), which is a register that contains the address of the next instruction to be executed.

Most computers use special registers to hold the instruction(s) currently being executed. They are called instruction register (IR).

There are a number of general-purpose registers. With these three kinds of registers, a computer would be able to execute programs.

Other types of registers:

 Memory-address register (MAR) holds the address of next memory operation (load or store).

Memory-buffer register (MBR) holds the content of memory operation (load or store). Processor status bits indicate the current status of the processor. Sometimes it is combined with the other processor status bits and is called the program status word (PSW). A few factors to consider when choosing the number of registers in a CPU are: CPU can access registers faster then it can access main memory.

For addressing a register, depending on the number of addressable registers a few bit addresses is needed in an instruction. These address bits are definetly quite less in comparison to a memory address. For example, for addressing 256 registers you just need 8 bits, whereas, the common memory size of 1MB requires 20 address bits, a difference of 60%.

Compilers tend to use a small number of registers because large numbers of registers are very difficult to use effectively. A general good number of registers is 32 in a general machine.

Registers are more expensive than memory but far less in number. From a user's point of view the register set can be classified under two basic categories. Programmer Visible Registers: These registers can be used by machine or assembly language programmers to minimize the references to main memory. Status Control and Registers: These registers cannot be used by the programmers but are used to control the CPU or the execution of a program.

(c) Assume that you have a machine as shown in section 3.2.2 of Block 3 having the microoperations as given in Figure 10 on page 62 of Block 3. Consider that R1 and R2 both are 8 bit registers and contains 11110101 and 10101001 respectively. What will be the values of select inputs, carry-in input and result of operation if the following micro-operations are performed? (For each micro-operation you may assume the initial value of R1 and R2 as defined above) 1) Decrement R1 2) R1 Exclusive OR R2 3) Subtract R1 from R2 with borrow 4) Shift Right R2
Ans:-1) Subtract R1 from R2

Number Input R2 Output

Carry Bit R1 0 1 0

Sign Bit 11110101 01011010 01001111

Increment R1
Number Input 00000001 Output 3) Sift left R1 Number Input Output Carry Bit R1 1 Sign Bit 11110101 11101010 Carry Bit R1 Sign Bit 11110101 11110110

4) Add R1, R2 with an initial input carry bit as 1 Number Input R2 Output Carry Bit R1 1 1 01011010 Sign Bit 11110101 01010000

(d) Explain the functions performed by the Micro-programmed Control Unit with the help of diagram Control Units? Also explain the role of sequencing logic component of Control Unit. Ans:-THE MICRO-PROGRAMMED CONTROL An alternative to a hardwired control unit is a micro-programmed control unit, in which the logic of the control unit is specified by a micro-program. A micro-program is also called firmware (midway between the hardware and the software). It consists of:
(a) One or more micro-operations to be executed; and

(b) The information about the micro-instruction to be executed next. The general configuration of a micro-programmed control unit is demonstrated in The microinstructions are stored in the control memory. The address register for the control memory contains the address of the next instruction that is to be read. The control memory Buffer Register receives the micro-instruction that has been read. A micro-instruction execution primarily involves the generation of desired control signals and signals used to determine the next micro-instruction to be executed. The sequencing logic section loads the control memory address register. It also issues a read command to control memory. The following functions are performed by the micro-programmed control unit: 1. The sequence logic unit specifies the address of the control memory word that is to be read, in the Address Register of the Control Memory. It also issues the READ signal. 2. The desired control memory word is read into control memory Buffer Register.

3. The content of the control memory buffer register is decoded to create control The Control Unit signals and next-address information for the sequencing logic unit. 4. The sequencing logic unit finds the address of the next control word on the basis of the next-address information from the decoder and the ALU flags. As we have discussed earlier, the execute cycle steps of micro-operations are differentfor all instructions in addition the addressing mode may be different. All such information generally is dependent on the opcode of the instruction Register (IR). Thus, IR input to Address Register for Control Memory is desirable. Thus, there exist a decoder from IR to Address Register for control memory. This decoder translates the opcode of the IR into a control memory address.

(e) What are the advantages of instruction pipeline? Explain with the help of a diagram for a 3 stage instruction pipeline having cycles IFD (Instruction Fetch and Decode), OF (Operand Fetch) and ES (Execute and store results). What can be the problems of such an instruction pipeline? Ans:-An instruction pipeline is a technique used in the design of computers to increase their instruction throughput (the number of instructions that can be executed in a unit of time). Pipelining does not reduce the time to complete an instruction, but increases the number of instructions that can be processed at once. Each instruction is split into a sequence of dependent steps. The first step is always to fetch the instruction from memory; the final step is usually writing the results of the instruction to processor registers or to memory. Pipelining seeks to let the processor work on as many instructions as there are dependent steps, just as an assembly line builds many vehicles at once, rather than waiting until one vehicle has passed through the line before admitting the next one. As the goal of the assembly line is to keep each assembler productive at all times, pipelining seeks to use every portion of the processor busy with some instruction. Pipelining lets the computer's cycle time be the time of the slowest step, and ideally lets one instruction complete in every cycle. The term pipeline is an analogy that stems from the fact that each part of the processor is doing work, as there is fluid in each link of a pipeline.

(f) Assume that a RISC machine has 64 registers out of which 16 registers are reserved for the Global variables. Assuming that 8 of the registers are to be used for one function, explain how the remaining registers will be used as overlapped register windows. How will these registers be used for parameter passing for subroutine calls? Explain with the help of diagram. Ans:-In general, the register storage is faster than the main memory and the cache. Also the register addressing uses much shorter addresses than the addresses for main memory and the cache. However, the numbers of registers in a machine are less as generally the same chip contains the ALU and control unit. Thus, a strategy is needed that will optimize the register use and, thus, allow the most frequently accessed operands to be kept in registers in order to minimize register-memory operations. Such optimisation can either be entrusted to an optimisingcomplier, which requires techniques for program analysis; or we can follow some hardware related techniques. The hardware approach will require the use of more registers so that more variables can be held in registers for longer periods of time. This technique is used in RISC machines. On the face of it the use of a large set of registers should lead to fewer memory accesses, however in general about 32 registers were considered optimum. Since most operand references are to local variables of a function in C they are the obvious choice for storing in registers. Some registers can also be used for global variables. However, the problem here is that the program follows function call - return so the local variables are related to most recent local function, in addition this call - return expects saving the context of calling program and return address. This also requires parameter passing on call. On return, from a call the variables of the calling program must be restored and the results must be passed back to the calling program. RISC register file provides a support for such call- returns with the help of register windows. Register files are broken into multiple small sets of registers and assigned to a different function. A function call automatically changes each of these sets. The use from one fixed size window of registers to another, rather than saving registers in memory as done in CISC. Windows for adjacent procedures are overlapped. Thisfeature allows parameter passing without moving the variables at all. The following figure tries to explain this concept: Assumptions: Register file contains 64 registers. Let them be called by register number 0 - 64. The diagram shows the use of registers: when there is call to function A (fA) which calls function B (fB) and function B calls function C (fC).

Registers Nos. 0-7 required by fA, fB, and fC 8-9 10 be passed to next call 16

Used for Global variables Function A Function B Function C

- 15 (6 Registers)

Unused Used by parameters of fC that may

Temporary variables of function C Local variables of function C Parameters of function C Local variables of function B Parameters of function B Local variables of function A Parameters of function A

Used for local variable of fC 26 - 31 (6 Registers) Used by parameters Temporary that variables of were passed from fB ->fC function B 32 - 41 (10 Registers) Local variables of fB 42 passed from fA to fB 48 58 - 47 (6 Registers) Parameters that Temporary were variables of function A - 57 (10 Registers) Local variable of fA - 64 (6 Registers) Parameter passed to fA

- 25 (10 Registers)

Question 4 (a) Write a program in 8086 assembly Language (with proper comments) to find if a given substring is prefix of a given string. For example, the sub-string Assembly is the prefix in the string Assembly Language Programming. You may assume that the sub-string as well as the string is available in the memory. You may also assume that the end of the strings is the character $. Make suitable assumptions, if any. Ans:-DATA SEGMENT STR1 DB "ENTER FIRST STRING HERE ->$" STR2 DB "ENTER SECOND STRING HERE ->$" STR3 DB "CONCATED STRING :->$" STR11 DB "FIRST STRING : ->$" STR22 DB "SECO ND STRIN G: >$" INSTR 1 DB 20 DUP(" $") INSTR2 DB 20 DUP("$") N DB ? N1 DB ?NEWLINE DB 10,13,"$" DATA ENDS CODE SEGMENT ASSUME LEA DX,NEWLINE INT 21H

MOV AH,09H LEA DX,STR2 Page 24 INT 21H MOV AH,0AH MOV DX,DI INT 21H MOV AH,09H LEA DX,NEWLINE INT 21H ; PRINT THE STRING MOV AH,09H LEA DX,STR11 INT 21H MOV AH,09H LEA DX,INSTR1+2 INT 21H MOV AH,09H LEA DX,NEWLINE INT 21H MOV AH,09H LEA DX,STR22 INT 21H MOV AH,09H LEA DX,INSTR2+2 INT 21H MOV AH,09H LEA DX,NEWLINE INT 21H ; CONCATINATION OF THE STRING LEA SI,INSTR1 LEA DI,INSTR2 MOV CX,00 INC SI L1:INC SI CMP BYTE PTR[SI],"$" JNE L1 ADD DI,2 MOV BX,0 L2: MOV BL,BYTE PTR[DI] MOV BYTE PTR[SI],BL INC SI INC DI CMP BYTE PTR[DI],"$" JNE L2 L8:DEC SI CMP SI,2 JNE L8 MOV AH,09H LEA DX,NEWLINE INT 21H MOV AH,09H LEA DX,STR3 INT 21H MOV AH,09H LEA DX,NEWLINE INT 21H L6: MOV BL, BYTE PTR[SI] MOV AH, 02H MOV DL, BL INT 21H INC SI CMP BYTE PTR[SI],"$" JNE L6 ; MOV AH, 09H ; LEA DX, INSTR1+2 ; INT 21 MOV AH,4CH INT 21H CODE ENDS END START (b) Write a program in 8086 assembly language to convert a two digit packed BCD number into equivalent ASCII digits. Your program should print the two ASCII digits. You may assume that the BCD number is in the AL register. Ans:-: name "convert" ; this program uses a subroutine written in 8086 assembly language ; that can be used for converting a string of number ; max of 4 ascii digit) to equivalent packed bcd digits. ; bcd is binary coded decimal. ; this program does no screen output. ; to see results click "vars". org 100h jmp start string db '1234' ; 4 ascii digits. packed_bcddw ? ; two bytes (word) to store 4 digits. start: lea bx, string lea di, packed_bcd call pack_to_bcd_and_binary ret ; return to operating system. ; subroutine written in 8086 assembly language ; that can be used for converting a string of number ; (max of 4 ascii digit) to equivalent packed ; bcd digits. ; input parameters: ;

bx - address of source string (4 ascii digits). ; output: ; di - must be set to address for packed bcd (2 bytes). pack_to_bcd_and_binary proc near pusha ; point to 2 upper digits of packed bcd: ; (assumed that we have 4 digits) add di, 1 ; loop only for 2 because every time we ; read 2 digits (2 x 2 = 4 digits) mov cx, 2 ; reset packedbcd: mov word ptr [di], 0 ; to convert a char (0..9) to digit we need ; to subtract 48 (30h) from its ascii code, ; or just clear the upper nibble of a byte. ; mask: 00001111b (0fh) next_digit: mov ax, [bx] ; read 2 digits. and ah, 00001111b and al, 00001111b ; 8086 and all other Intel's microprocessors store less ; significant byte at lower address. xchg al, ah ; move first digit to upper nibble: shl ah, 4 ; pack bcd: or ah, al ; store 2 digits: mov [di], ah ; next packed bcd: sub di, 1 ; next word (2 digits): add bx, 2 loop next_digitpopa ret pack_to_bcd_and_binaryendp

(c) Write a simple subroutine that receives one parameter value. The subroutine checks if the passed parameter value is 0 or otherwise. In case, the value is 0 then it prints FALSE, otherwise it prints TRUE. Make suitable assumptions, if any.

Ans:-A simple subroutine that accepts a parameter value and checks if the passed parameter value is Zero(0). If the value is ZERO the subroutine outputs a string "Divide Overflow" and terminates the execution, otherwise it allows the calling program to continue
#include<stdio.h> #include<stdlib.h>intchk_input(int in) { if(in==0) { printf("Divide Overflow\n"); exit(1); /* terminate Program*/ } else { return(0); /* continue execution*/ } } void main() { inti=89,in,flg; printf("A Program to divide 89 by any number supplied\nPlease enter divisor:"); scanf("%d",&in); flg=chk_input(in); if(flg==0) {printf("%d divided by %d =%f\n",i,in,float(i/in)); } } /* End of Program