SEP INSTITUTO

DGEST TECNOLGICO DE

SNEST MATAMOROS

DEPARTAMENTO DE INGENIERA ELCTRICA Y ELECTRNICA

DISEO DIGITAL CON VHDL

8:00 a 9:00pm, Lunes, Mircoles, Viernes 7:00 a 9:00 pm, Martes

Prctica 9.- Cronometro en VHDL

Alumnos: Leonardo Adn Mora Vzquez Jos Fortino Rico San Martn Luis Eduardo Guzmn Puga Julin Vera vila Nm. de control: 11260099 11260110 11260085 11260125

Profesor: Ing. Arturo Rodrguez Casas

H. MATAMOROS, TAM.

05 DE NOVIEMBRE DE 2013

OBJETIVO

Implementar un cronometro del 0 al 99 con opcin de pausa y reseteo usando el Aldec HDL y el kit de desarrollo Basys 2.

MARCO TERICO

Los dispositivos digitales medidores de tiempo son una aplicacin de lgica secuencial en la solucin de una situacin de nuestra vida diaria. Un ejemplo de estos dispositivos digitales son los cronmetros.

El cronmetro es un reloj cuya precisin ha sido comprobada y certificada por algn instituto o centro de control de precisin. La palabra cronmetro es un neologismo de etimologa griega: Cronoses el dios del tiempo, metron es hoy un sufijo que significa aparato para medir.

CDIGOS VHDL

library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity relojanodos is port( resetanodo,clkan:in std_logic; clkanout: out std_logic ); end relojanodos; architecture func_relojanodos of relojanodos is signal counter:std_logic_vector(19 downto 0); signal clkoutsignal: std_logic; begin process(resetanodo, clkan) begin if (resetanodo='1')then clkoutsignal<='0'; counter<=(others=>'0'); elsif(clkan'event and clkan='1')then if(counter=x"186a0")then counter<=(others=>'0'); clkoutsignal<=not clkoutsignal; else counter<=counter+1; end if; end if; end process; clkanout<=clkoutsignal; end func_relojanodos; Relojanodos

library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity relojcontador is port ( rst2,clkin2 : in std_logic; clkout2 : out std_logic ); end relojcontador; architecture behavioral of relojcontador is signal counter : std_logic_Vector (27 downto 0); signal clkout2Signal : std_logic; begin process (clkin2, rst2) begin if (rst2 = '1') then clkout2Signal <= '0'; counter <= (others => '0'); elsif (clkin2'event and clkin2 = '1') then if (counter = "1011111010111100001000000")then counter <= (others => '0'); clkout2Signal <= not clkout2Signal; else counter <= counter + 1; end if; end if; end process; -- output assignments clkout2 <= clkout2Signal; end behavioral; relojcontador

library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity contador7seg is port ( clkincontador,rst,start,pause,continue : in std_logic; digitOne,digitTen : out std_logic_vector (3 downto 0) ); end contador7seg; architecture func_contador7seg of contador7seg is signal digitOneSignal : std_logic_vector (3 downto 0); signal digitTenSignal : std_logic_vector (3 downto 0); type states is (resetState, countState, pauseState); signal state : states; begin process (clkincontador, rst) begin if (rst = '1') then state <= resetState; elsif (clkincontador'event and clkincontador = '1') then case state is when resetState => digitOneSignal <= (others => '0'); digitTenSignal <= (others => '0'); if (start = '1') then state <= countState; end if; when countState => if (pause = '1') then state <= pauseState; end if; if (digitOneSignal = "1001") then digitOneSignal <= (others => '0'); digitTenSignal <= digitTenSignal + '1'; if (digitTenSignal = "1001") then digitTenSignal <= (others => '0'); end if; else digitOneSignal <= digitOneSignal + '1'; end if; when pauseState => if (continue = '1') then state <= countState; end if; end case; end if; end process; digitOne <= digitOneSignal; digitTen <= digitTenSignal; end func_contador7seg;

contador7s eg

library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity controldeanodos is port (clkinanodo : in std_logic; san0,san1,san2,san3 : out std_logic ); end controldeanodos; architecture func_controldeanodos of controldeanodos is signal an0Signal,an1Signal,an2Signal,an3Signal : std_logic; begin process (clkinanodo) begin if (clkinanodo = '0') then an2Signal <= '1'; an3Signal <= '0'; else an2Signal <= '0'; an3Signal <= '1'; end if; end process; -- an0 & an1 are always '1' an0Signal <= '1'; an1Signal <= '1'; -- output assignments san0 <= an0Signal; san1 <= an1Signal; san2 <= an2Signal; san3 <= an3Signal; end func_controldeanodos; controldeanodos

library IEEE; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity bcd7seg is port( binaryin: in std_logic_vector(3 downto 0); seg7out: out std_logic_vector(0 to 6) ); end bcd7seg; architecture func_bcd7seg of bcd7seg is signal seg7signal: std_logic_vector(0 to 6); begin process(binaryin) begin case binaryin is --abcdefg se encienden en 0 when "0000" =>seg7signal <= "0000001"; --0 when "0001" =>seg7signal <= "1001111"; --1 when "0010" =>seg7signal <= "0010010"; --2 when "0011" =>seg7signal <= "0000110"; --3 when "0100" =>seg7signal <= "1001100"; --4 when "0101" =>seg7signal <= "0100100"; --5 when "0110" =>seg7signal <= "0100000"; --6 when "0111" =>seg7signal <= "0001111"; --7 when "1000" =>seg7signal <= "0000000"; --8 when others =>seg7signal <= "0001100"; --9 end case; end process; --dp is always zero --seg7signal(7)<='1'; seg7out<=seg7signal; end func_bcd7seg; bcd7seg

library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity mux7seg is port (an2in,an3in: in std_logic; sevenOne : in std_logic_vector (0 to 6); sevenTen : in std_logic_vector (0 to 6); sevenOut : out std_logic_vector (0 to 6) ); end mux7seg; architecture behavioral of mux7seg is signal sevenOutSignal : std_logic_vector (0 to 6); begin process (an2in, an3in, sevenOne, sevenTen) begin if (an2in = '1' and an3in = '0') then sevenOutSignal <= sevenTen; else sevenOutSignal <= sevenOne; end if; end process; sevenOut <= sevenOutSignal; end behavioral; mux7seg

Interconexin de los componentes

U1 Reset CLK50M
re s etano d o c lk an c lk ano ut

U4
c lk inano d o s an0 s an1 s an2 s an3

relojanodos U2
rs t2 c lk in2 c lk out2

an0 an1 an2 an3 U7

an2 in s e v enO ut(0:6 )

controldeanodos

U5
b inary in(3 :0 ) s e g 7o ut(0 :6 )

Display(0:6)

an3 in s e v enO ne (0:6 ) s e v e nT e n(0 :6 )

relojcontador U3
c lk inc ontad o r rs t d ig itO ne (3:0 ) d ig itT e n(3 :0 )

bcd7seg U6
b inary in(3 :0 ) s e g 7o ut(0 :6 )

mux7seg

Iniciar Pausar Continuar

s tart p aus e c o ntinue

bcd7seg

contador7seg

Cableado.bde

CONCLUSIN

Durante la realizacin de la prctica no se presentaron inconvenientes, fue finalizada correctamente a la primera, algo que pudimos notar es como se pueden usar condiciones de estado para elaborar sistemas ms complejos, y como se pueden facilitar la electrnica digital con la ayuda de la programacin en VHDL.