SHRI SHIRDI SAI INSTITUTE OF SCIENCE AND ENGINEERING III B.Tech. I Sem.

, ECE, I Mid-Term Examinations DIGITAL IC APPLICATIONS Subjective Paper Duration: 1hour 30 minutes. Marks: 30 Answer any 3 questions from the following. 1. Explain the steps in designing a digital system using VHDL. 2. Design a CMOS transistor circuit with the functional behavior ___________ _ _ (A+B) (C+D) 3. Design TTL tri-state NAND gate and explain the operation with the help of function table. 4. Write short note on following terms: a) Std_logic b) Process statement c) Fan out d) VHDL Program Structure 5. Compare CMOS and TTL by considering at least four parameters.

SHRI SHIRDI SAI INSTITUTE OF SCIENCE AND ENGINEERING III B.Tech. I Sem., ECE, I Mid-Term Examinations DIGITAL IC APPLICATIONS Objective Paper Duration: 20 minutes. Marks: 10 Answer all questions by choosing the correct alternative. 1. ECL belongs to ______ family [ ] A) Bipolar-Saturated B) Bipolar-Unsaturated C) Unipolar-Saturated D) Unipolar-Unsaturated 2. The TTL output stage is called _______ [ ] A) Open-collector B) High impedance C) Push-pull D) None 3. Mosfet is a ________ transistor [ ] A) Bipolar B) Unipolar C) Field-effect D) Both B and C 4. In CMOS circuit the voltage levels between 1.5 V to 3.5V are interpreted as [ ] A) Logic 0 B) Logic 1 C) Either logic 0 or logic 1 D) High Impedance 5. Metal oxide semiconductor devices are better __________ [ ] A) Amplifiers B) Switches C) Oscillators D) Power Amplifiers 6. _______ DC noise margin ensure that the highest LOW voltage produced by an output is always lower than the highest voltage that an input can reliably interpret as low [ ] A) Negative B) Non-Negative C) High D) Low 7. The fan-out of logic gate depends on [ ] A) Characteristics of output B) Number of inputs that gate is driving C) Both A and B D) None 8. Loading an output beyond its rated fan-out has following effects [ ] A) Reduce the DC noise margin B) Reduce the timing margin C)Both A and B D) Increase the DC noise margin 9. CMOS circuits have very low [ ] A) Static power dissipation B) Dynamic power dissipation C) Apparent power dissipation D) Average power dissipation 10. The dynamic power dissipation of CMOS circuits depends on [ ] A) Transition frequency of output signal B) Power supply Voltage C)Power dissipation Capacitance D) A,B and C 11. If the outputs of several open-drain gates are tied together with a single pull up resistor, then __________ logic is performed. [ ] A) and B) or C) nand D) nor 12. Fastest logic family from the following [ ] A) Schottky TTL B) TTL C) RTL D) DTL Cont.

13. Total number of values present in std_logic A) 10 B) 9 C) 11 D)7 14. Difference between std_logic and std_ulogic lies in the concept of ________ A) Resolving Function B) Resolution Function C) User defined function 15. Std_logic_1164 is a A) Library B) Function C) Package D)Procedure 16. Pick up the invalid data object name A) A9Signal B) A9_Signal C) A9_ _ Signal D) Both B and C 17. Library and Use clause comes under ________ visibility A) Implicit B) Explicit C) Over D)Under 18. In ECL propagation delay is A) Longer B) Constant C) Shorter D)Zero 19. Units of dynamic power dissipation is A) milliwatt B) millivolt/megahertz C)joules D)no units 20. The VHDL constants can be used to describe wires of the digital circuit A) Yes B) Only sometimes C) Never D)It depends

[ ] D) None [ ] [ [ ] ]

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