International Journal of Advanced Research in Engineering (IJARE) Vol 1, Issue 1,2012 Page

31 3!

Design Of 128 Bit Low Power and Area Efficient Carry Select Adder
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A.Andamut u! S."it anyaa

M.E (VLSI Design), Department of ECE, Bannari Amman Institute of Tec no!og". # M.Sc (IT), Department of Information Tec 2 no!og", $ongu Engineering Co!!ege. 1
andamuthuece@gmail.com, srithanyaa@gmail.com

Abstract Design of area% an& po'er%efficient ig %spee& &ata pat !ogic s"stems forms t e !argest areas of researc in VLSI s"stem &esign. In &igita! a&&ers, t e spee& of a&&ition is !imite& (" t e time re)uire& to transmit a carr" t roug t e a&&er. Carr" Se!ect A&&er (CSLA) is one of t e fastest a&&ers use& in man" &ata%processing processors to perform fast arit metic functions. *rom t e structure of t e CSLA, it is c!ear t at t ere is span for re&ucing t e area an& po'er consumption in t e CSLA. T is 'or+ uses a simp!e an& efficient gate%!e,e! mo&ification to &rastica!!" re&uce t e area an& po'er of t e CSLA. Base& on t is mo&ification -, 1., /#, .0 an& 1#-%(it s)uare%root CSLA (S12T CSLA) arc itectures a,e (een &e,e!ope& an& compare& 'it t e regu!ar S12T CSLA arc itecture. T e propose& &esign as re&uce& area an& po'er as compare& 'it t e regu!ar S12T CSLA 'it on!" a minor increase in t e &e!a". T is 'or+ estimates t e performance of t e propose& &esigns in terms of &e!a", area, po'er, an& t eir pro&ucts are imp!emente& in 3i!in4 *56A. T e resu!ts ana!"sis s o's t at t e propose& CSLA structure is (etter t an t e regu!ar S12T CSLA. T e propose& &esign is app!ie& to t e *I2 fi!ter structure in t e a&&er part. Index TermsApp!ication%specific integrate& circuit (ASIC), area%efficient, CSLA, !o' po'er. 1. #$%"OD&C%#O$ Area an& po'er re&uction in &ata pat !ogic s"stems are t e main area of researc in VLSI s"stem &esign. 7ig % spee& a&&ition an& mu!tip!ication as a!'a"s (een a fun&amenta! re)uirement of ig %performance processors an& s"stems. In &igita! a&&ers, t e spee& of a&&ition is !imite& (" t e time re)uire& to propagate a carr" t roug t e a&&er. T e sum for eac (it position in an e!ementar" a&&er is generate& se)uentia!!" on!" after t e pre,ious (it position as (een summe& an& a carr" propagate& into t e ne4t position. T e ma8or spee& !imitation in an" a&&er is in t e pro&uction of

carries an& man" aut ors a,e consi&ere& t e a&&ition pro(!em. T e CSLA is use& in man" computationa! s"stems to mo&erate t e pro(!em of carr" propagation &e!a" (" in&epen&ent!" generating mu!tip!e carries an& t en se!ect a carr" to generate t e sum. 7o'e,er, t e CSLA is not area efficient (ecause it uses mu!tip!e pairs of 2ipp!e Carr" A&&ers (2CA) to generate partia! sum an& carr" (" consi&ering carr" input an& t en t e fina! sum an& carr" are se!ecte& (" t e mu!tip!e4ers (mu4). To o,ercome a(o,e pro(!em, t e (asic i&ea of t e propose& 'or+ is (" using n%(it (inar" to e4cess%1 co&e con,erters (BEC) to impro,e t e spee& of a&&ition. T is !ogic can (e imp!emente& 'it an" t"pe of a&&er to furt er impro,e t e spee&. 9sing Binar" to E4cess%1 Con,erter (BEC) instea& of 2CA in t e regu!ar CSLA to ac ie,e !o'er area an& po'er consumption. T e main a&,antage of t is BEC !ogic comes from t e !esser num(er of !ogic gates t an t e *u!! A&&er (*A) structure. Digita! Signa! 5rocessing (DS5) &ea!s 'it t e manipu!ation of &igita! signa!s using comp!e4 signa! processing s"stems (ui!t from (asic (ui!&ing (!oc+s !i+e fi!ters. T e propose& 'or+ is imp!ementation in t e *I2 fi!ter in a&&er parts. T is re&uces t e area an& !o' po'er consumption in *I2 fi!ter. ##. BAS#C '&$C%#O$ A$D S%"&C%&"E O' BEC LO(#C T e (asic 'or+ is to use Binar" to E4cess%1 Con,erter (BEC) instea& of 2CA 'it Cin:1 in t e regu!ar CSLA to ac ie,e !o'er area an& po'er consumption. T e main a&,antage of t is BEC !ogic comes from t e !esser num(er of !ogic gates t an t e n%(it *u!! A&&er (*A) structure As state& a(o,e t e main i&ea of t is 'or+ is to use BEC instea& of t e 2CA 'it Cin:1 in or&er to re&uce t e area an& po'er consumption of t e regu!ar CSLA. To rep!ace t e n%(it 2CA, an n;1%(it BEC is re)uire&. A structure an& t e function

co"

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ta(!e of a 0%(it BEC are s o'n in *igure.# an& Ta(!e .#, respecti,e!".

###. BAS#C S%"&C%&"E O' "E(&LA" 1/0B#% S1"% CSLA A 1.%(it carr" se!ect as t'o t"pes of (!oc+ siDe name!" uniform (!oc+ siDe an& ,aria(!e (!oc+ siDe. A 1.%(it carr" se!ect a&&er 'it a uniform (!oc+ siDe as t e &e!a" of four fu!! a&&er &e!a"s an& t ree M93 &e!a"s. E i!e a 1.%(it carr" se!ect a&&er 'it ,aria(!e (!oc+ siDe as t e &e!a" of t'o fu!! a&&er &e!a"s, an& four mu4 &e!a"s. T erefore 'e use 1.%(it carr" se!ect a&&er 'it ,aria(!e (!oc+ siDe. 2ipp!e%carr" a&&ers are t e simp!est an& most compact fu!! a&&ers, (ut t eir performance is !imite& (" a carr" t at must ripp!e from t e !east%significant to t e most%significant (it. A carr"%se!ect a&&er ac ie,es spee&s 0=F to G=F faster (" performing a&&itions in para!!e! an& re&ucing t e ma4imum carr" pat .

*igure #< 0%(inar" to e4cess%1 con,erter Ta(!e.# *unction ta(!e of t e 0%(it

B)*+,-

.)*+,-

==== ===1 >

===1 ==1= > >

*igure /< 2egu!ar 1.%(it S12T CSLA A carr"%se!ect a&&er is &i,i&e& into sectors, eac of ' ic , e4cept for t e !east significant performs t'o a&&itions in para!!e!, one assuming a carr"%in of Dero, t e ot er a carr"% in of one 'it in t e sector, t ere are t'o 0%(it ripp!e% carr" a&&ers recei,ing t e same &ata inputs (ut &ifferent Cin. T e upper a&&er as a carr"%in of Dero, t e !o'er a&&er a carr"%in of one. T e actua! Cin from t e prece&ing sector se!ects one of t e t'o a&&ers. If t e carr"%in is Dero, t e sum an& carr"%out of t e upper a&&er are se!ecte&. If t e carr"%in is one, t e sum an& carr"%out of t e !o'er a&&er are se!ecte&. Logica!!", t e resu!t is not &ifferent if a sing!e ripp!e%carr" a&&er 'ere use&. *irst t e co&ing for fu!! a&&er an& &ifferent mu!tip!e4ers of .</, -<0, 1=<H, an& 1#<. 'as &one. T en #, /, 0, H%(it ripp!e carr" a&&er 'as &one (" ca!!ing t e fu!! a&&er. T e regu!ar .0%(it CSLA 'as create& (" ca!!ing t e ripp!e carr" a&&ers an& a!! mu!tip!e4ers (ase& on circuit. *ina!!", regu!ar 1#-%(it 'as imp!emente& in t e *I2 fi!ter &esign (sectionH).

> 111= 1111

> > 1111 ====

T e Boo!ean e4pressions of t e 0%(it BEC is !iste& as (note t e functiona! s"m(o!s ? @AT, B A@D, C3A2) 3= : ?B= 31 : B=CB1 3# : B#C (B= B B1) 3/ : B/C (B= B B1 B B#)

remaining groupLs t e arri,a! time of mu4 se!ection input is a!'a"s greater t an t e arri,a! time of &ata inputs from t e BECLs. T us, t e &e!a" of t e remaining groups &epen&s on t e It is simi!ar to regu!ar 1.%(it S12T CSLA. An!" arri,a! time of mu4 se!ection input an& t e mu4 &e!a". c ange is t at in (asic (!oc+s a,ing t'o ripp!e%carr" a&&ers, one ripp!e carr" a&&er fe& 'it a constant 1 carr"%in is rep!ace& (" BEC. T e area estimation of eac group is 2. #3PLE3E$%A%#O$ #$ '#" '#L%E" ca!cu!ate&. A fi!ter is use& to mo&if" an input signa! in or&er to faci!itate furt er processing. A &igita! fi!ter 'or+s on a &igita! Base& on t e consi&eration of &e!a" ,a!ues, t e T e most common &igita! fi!ter is t e Linear Time%In,ariant arri,a! time of se!ection input C1 Itime (T) :JK of .</ mu4 is (LTI) fi!ter. Designing an LTI in,o!,es arri,ing at t e fi!ter ear!ier t an t e s/ It :GK an& c/ It :JK an& !ater t an t e s# It coefficients ' ic , in turn, represents t e impu!se response of :0K. T us, t e sum/ an& fina! c/ (output from mu4) are t e propose& fi!ter &esign. T ese coefficients, in !inear &epen&ing on s/ an& mu4 an& partia! c/ (input to mu4) an& con,o!ution 'it t e input se)uence 'i!! resu!t in t e &esire& mu4, respecti,e!". T e sum# &epen&s on c1 an& mu4. *or t e remaining parts t e arri,a! time of mu4 se!ection input is a!'a"s greater t an t e arri,a! time of &ata inputs from t e BECLs. T us, t e &e!a" of t e remaining M93 &epen&s on t e arri,a! time of mu4 se!ection input an& t e mu4 &e!a". *irst t e co&ing for fu!! a&&er an& mu!tip!e4ers of .</, -<0, 1=<H, an& 1#<. 'as &one. T e BEC program 'as &esign (" using @AT, 3A2 an& A@D gates. T en #, /, 0, H%(it ripp!e carr" a&&er 'as &one (" ca!!ing t e fu!! a&&er. T e mo&ifie& 1.%(it CSLA 'as create& (" ca!!ing t e ripp!e carr" a&&ers, BEC an& a!! mu!tip!e4ers (ase& upon t e circuit. *ina!!", mo&ifie& .0%(it 'as imp!emente& in t e *I2 fi!ter &esign (section H).

#2 BAS#C S%"&C%&"E O' "E(&LA" 1/0B#% S1"% CSLA

output. In t e a(o,e figure.H, t e a&&er part is rep!ace& (" t e regu!ar an& mo&ifie& S12T CSLA. T en output is compare& (et'een t e regu!ar an& mo&ifie& S12T CSLA. 2#. #3PLE3E$%A%#O$ "ES&L%S T e &esign propose& in t is paper as (een &e,e!ope& using Veri!og%7DL an& s"nt esiDe& in 3i!in4 ISE G.1i. *or eac 'or& siDe of t e a&&er, t e same ,a!ue c ange& &ump (VCD) fi!e is generate& for a!! possi(!e input con&itions an& importe& t e same to 3i!in4 ISE G.1i 5o'er Ana!"sis to perform t e po'er simu!ations. T e simi!ar &esign f!o' is fo!!o'e& for (ot t e regu!ar an& mo&ifie& S12T CSLA. Ta(!e H e4 i(its t e simu!ation resu!ts of (ot t e CSLA fir fi!ter structures in terms of &e!a", area an& po'er. T e po'erM&e!a" pro&uct of t e propose& -%(it is ig er t an t at of t e regu!ar S12T CSLA (" H.#F an& t e area% &e!a" pro&uct is !o'er (" #.GF. 7o'e,er, t e po'er%&e!a" pro&uct of t e propose& 1.%(it S12T CSLA re&uces (" 1.J.F an& for t e /#%(it, .0%(it an& (" as muc as -.1-F, an& 1#.#-F respecti,e!".

*igure. .. Mo&ifie& 1.%(it S12T CSLA. T e arri,a! time of se!ection input of .</ mu4 is ear!ier. T us, t e sum/ an& fina! c/ (output from mu4) &epen&s on s/ an& mu4 an& partia! c/ (input to mu4) an& mu4, respecti,e!". T e sum# &epen&s on c1an& mu4. *or t e input (a se)uence of num(ers, resu!ting from samp!ing an& )uantiDing an ana!og signa!) an& pro&uces a &igita! output.

%ABLE 4 CO3PA"#SO$ O' %5E "E(&LA" A$D 3OD#'#ED S1"% CSLA #$ '#" '#L%E" S.$ O ADDE"S DELA 6 7ns8 *I2 fi!ter using regu!ar .0%(it 1 *I2 fi!ter using mo&ifie& .0%(it *I2 fi!ter using regu!ar 1#-%(it # *I2 fi!ter using mo&ifie& 1#-%(it 1=#.#H 1,.#,H.J JH0.01 G/.GH/ -0.H. 0.,JG= 1,G=,G0J /-/.JJ GHJ.H. J1.-J/ 0J,#J/ 0##./J A"EA 7gates8 PO9E" 7m98

2##. CO$CL&S#O$ A simp!e approac is propose& in t is paper to re&uce t e area an& po'er of S12T CSLA arc itecture. T e re&uce& num(er of gates of t is 'or+ offers t e great a&,antage in t e re&uction of area an& a!so t e tota! po'er. T e compare& resu!ts s o' t at t e mo&ifie& S12T CSLA as a s!ig t!" !arger &e!a" (on!"/.J.F), (ut t e area an& po'er of t e 1#-%(it mo&ifie& S12T CSLA are significant!" re&uce& (" 1J.0F an& 1H.0F respecti,e!". T e po'er%&e!a" pro&uct an& a!so t e area%&e!a" pro&uct of t e propose& &esign s o' a &ecrease for 1., /#,.0 an& 1#-%(it siDes ' ic in&icates t e success of t e met o& an& not a mere tra&eoff of &e!a" for po'er an& area. T e mo&ifie& CSLA arc itecture is t erefore, !o' area, !o' po'er, simp!e an& efficient for VLSI ar&'are imp!ementation. "E'E"E$CES I1K Be&ri8, A. N., (1G.#), OCarr"%se!ect Trans. Electron. Comput., pp./0=M/00 . a&&er,P IRE I0K 2am+umar,B. , $ittur, 7.M. an& $annan ,5. M. ,(#=1= ),OASIC imp!ementation of mo&ifie& faster carr" sa,e a&&er,P Eur. '. $c&. Res., vol. 42, no. 1,pp.H/MH-. IHK $im ,Q. an& $im ,L.%S.,((a%2001", O.0%(it carr"% se!ect a&&er 'it re&uce& area,PElectron Lett., vol. 3), no. 10, pp. *14 *1!. I.K E. A(u%S ama an& M. Ba"oumi, OA @e' ce!! for !o' po'er a&&ers,P in 5roc.Int. Mi&'est S"mp. Circuits an& S"stems, 1GGH, pp. 1=10M1=1J IJK '''.4i!in4.com.

I#K Ceiang ,T. Q. an& 7siao,M. N. ,(Oct1998 ),OCarr"% se!ect a&&er using sing!e ripp!e carr" a&&er,P Electron. Lett., vol. 34, no. 22, pp. 2101 2103 I/K 7e, Q. , C ang ,C. 7. an& 6u, N. , (200!", OAn A rea efficient .0%(it s)uare root carr"%se!ect a&&er for !o' po'er app!ication,P in #roc. IEEE Int. $%mp.C&rcu&ts $%st. vol. 4, pp. 4082 408!.