VHDL Write User.s and Reference Manual

VHDLwrite Users and Reference Manual
Software Version 8.6_4
Copyright 1994 - 1999 Mentor Graphics Corporation. All rights reserved. This document contains information that is proprietary to Mentor Graphics Corporation and may be duplicated in whole or in part by the original recipient for internal business purposes only, provided that this entire notice appears in all copies. In accepting this document, the recipient agrees to make every reasonable effort to prevent the unauthorized use of this information.
This document is for information and instruction purposes. Mentor Graphics reserves the right to make changes in specifications and other information contained in this publication without prior notice, and the reader should, in all cases, consult Mentor Graphics to determine whether any changes have been made. The terms and conditions governing the sale and licensing of Mentor Graphics products are set forth in written agreements between Mentor Graphics and its customers. No representation or other affirmation of fact contained in this publication shall be deemed to be a warranty or give rise to any liability of Mentor Graphics whatsoever. MENTOR GRAPHICS MAKES NO WARRANTY OF ANY KIND WITH REGARD TO THIS MATERIAL INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OR MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. MENTOR GRAPHICS SHALL NOT BE LIABLE FOR ANY INCIDENTAL, INDIRECT, SPECIAL, OR CONSEQUENTIAL DAMAGES WHATSOEVER (INCLUDING BUT NOT LIMITED TO LOST PROFITS) ARISING OUT OF OR RELATED TO THIS PUBLICATION OR THE INFORMATION CONTAINED IN IT, EVEN IF MENTOR GRAPHICS CORPORATION HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. RESTRICTED RIGHTS LEGEND 03/97 U.S. Government Restricted Rights. The SOFTWARE and documentation have been developed entirely at private expense and are commercial computer software provided with restricted rights. Use, duplication or disclosure by the U.S. Government or a U.S. Government subcontractor is subject to the restrictions set forth in the license agreement provided with the software pursuant to DFARS 227.72023(a) or as set forth in subparagraph (c)(1) and (2) of the Commercial Computer Software - Restricted Rights clause at FAR 52.227-19, as applicable. Contractor/manufacturer is: Mentor Graphics Corporation 8005 S.W. Boeckman Road, Wilsonville, Oregon 97070-7777. A complete list of trademark names appears in a separate Trademark Information document. This is an unpublished work of Mentor Graphics Corporation.
Table of Contents
TABLE OF CONTENTS
About This Manual ................................................................................................xi On-line Documentation .........................................................................................xi Year 2000 Ready ..................................................................................................xii Chapter 1 VHDLwrite Overview ......................................................................................... 1-1 Introduction......................................................................................................... 1-1 VHDL Export Procedure .................................................................................... 1-2 Exporting VHDL to a Source Directory ............................................................. 1-4 Modifying the Export Options............................................................................ 1-6 Miscellaneous Options........................................................................................ 1-8 Libraries and Packages Options........................................................................ 1-10 Types Options ................................................................................................... 1-12 Generics Options .............................................................................................. 1-14 Primitive Control Options................................................................................. 1-16 Archs and Configs Options............................................................................... 1-18 Name Mapping Options.................................................................................... 1-20 Compilation Options......................................................................................... 1-22 Options File Example ....................................................................................... 1-24 Adding VHDL Information to a Symbol.......................................................... 1-26 Adding VHDL Information to Schematic ........................................................ 1-28 Overriding the Arch or Config Name ............................................................... 1-30 Invoking VHDLwrite from a Shell................................................................... 1-32 Compiling Source Files for ModelSim............................................................. 1-34 Frame Example (review) .................................................................................. 1-36 Design Viewpoint (conceptual review) ............................................................ 1-38 Generating a Symbol from an Entity ................................................................ 1-40 Symbol Generation Example ............................................................................ 1-42 Importing VHDL Info to a Symbol .................................................................. 1-44 Chapter 2 The VHDL Generation Process.......................................................................... 2-1 Adding VHDL Info to a Symbol ........................................................................ 2-1
VHDLwrite User's and Reference Manual, V8.6_4
iii
Table of Contents
TABLE OF CONTENTS [continued]

Adding VHDL Info to a Schematic .................................................................... 2-3 Specifying VHDL Export Options ..................................................................... 2-5 Specifying Export Options from the DA User Interface.................................. 2-5 Specifying Export Options from a Shell Invocation ........................................ 2-6 Options File Format ......................................................................................... 2-6 Verifying the Design......................................................................................... 2-19 Checking the Symbols.................................................................................... 2-19 Checking the Schematics ............................................................................... 2-19 Checking for VHDL Syntax Errors................................................................ 2-19 Generating the VHDL Source Files.................................................................. 2-24 Output Source File Naming Conventions ...................................................... 2-24 Overwriting Output Source Files ................................................................... 2-26 Compiling the VHDL Source ........................................................................... 2-26 Chapter 3 Symbol-to-VHDL Entity Mapping .................................................................... 3-1 Generating an Entity ........................................................................................... 3-1 Mapping Names.................................................................................................. 3-2 Basic and Extended VHDL Identifiers ............................................................ 3-2 Rules for Name Mapping ................................................................................. 3-2 Mapping Entity Names .................................................................................... 3-4 Libraries .............................................................................................................. 3-5 Handling Generics .............................................................................................. 3-6 Generic Example 1 ........................................................................................... 3-7 Generic Example 2 ........................................................................................... 3-7 Generic Example 3 ........................................................................................... 3-8 Generic Example 4 ........................................................................................... 3-9 Generic Example 5 ......................................................................................... 3-10 Symbol Properties Mapped to VHDL .............................................................. 3-11 Generating a Symbol from a VHDL Entity ...................................................... 3-13 Importing VHDL Info to Symbols ................................................................... 3-15
iv
Table of Contents

Chapter 4 Schematic-to-VHDL Architecture Mapping ..................................................... 4-1 Instances on a Schematic Sheet .......................................................................... 4-1 Descent through Unevaluated Design Data ..................................................... 4-2 Descent through Evaluated Design Data (Viewpoint Specified) ..................... 4-3 Overriding Architecture or Config Name........................................................... 4-3 Parameterization ................................................................................................. 4-6 Determining the VHDL Data Type .................................................................... 4-6 Port Data Type ................................................................................................. 4-6 Net Data Type .................................................................................................. 4-9 Mapping the Range Direction for Buses .......................................................... 4-11 Multidimensional Signals ................................................................................. 4-11 Multiple Occurrences of Arrayed Net Names .................................................. 4-12 Determining Port Mode (direction) .................................................................. 4-12 Generating an Entity from a Schematic............................................................ 4-14 Handling Pins with Mode Out....................................................................... 4-14 Mapping Net Connectors .................................................................................. 4-15 Mapping Bus Rippers ....................................................................................... 4-16 Complex Bus Structures ................................................................................... 4-18 Mapping Net Bundles ....................................................................................... 4-19 Mapping Global Nets........................................................................................ 4-19 Mapping Frames ............................................................................................... 4-20 Mapping FOR Frames.................................................................................... 4-21 Complications and Subtleties........................................................................ 4-21 Mapping IF Frames ........................................................................................ 4-24 Mapping CASE and OTHERWISE Frames .................................................. 4-24 Mapping Repeating Instances........................................................................... 4-24 Schematic Constructs that Do Not Map ........................................................... 4-24 Net Bundles.................................................................................................... 4-24 Pin-to-Net Bundle Connections ..................................................................... 4-25 Two Ports Shorted Together .......................................................................... 4-25 Unnamed Nets Connected to Wide Pins ........................................................ 4-26 Global Net Ripped from a Bus....................................................................... 4-26 Multidimensional Ports .................................................................................. 4-27
Table of Contents

Pin Names Referencing a Bus........................................................................ 4-27 Schematic Properties Mapped to VHDL .......................................................... 4-28 Chapter 5 Function Dictionary ............................................................................................ 5-1 Introduction......................................................................................................... 5-1 Function Descriptions ......................................................................................... 5-2 $delete_all_hdl_entity_generics() .................................................................. 5-15 $delete_default_architecture_name() ............................................................. 5-16 $delete_default_pin_hdl_type() ..................................................................... 5-17 $delete_hdl_entity_constants() ...................................................................... 5-18 $delete_hdl_entity_generic().......................................................................... 5-19 $delete_hdl_entity_libraries() ........................................................................ 5-20 $delete_hdl_entity_packages()....................................................................... 5-21 $delete_hdl_entity_statements() .................................................................... 5-22 $delete_instance_architecture_name() ........................................................... 5-23 $delete_net_hdl_type()................................................................................... 5-24 $delete_pin_hdl_mode() ................................................................................ 5-25 $delete_pin_hdl_type() .................................................................................. 5-26 $delete_schematic_architecture_name() ........................................................ 5-27 $dx__import_entity_info()............................................................................. 5-28 $export_vhdl()................................................................................................ 5-30 $generate_symbol()........................................................................................ 5-33 $get_default_architecture_name().................................................................. 5-39 $get_default_pin_hdl_type() .......................................................................... 5-40 $get_hdl_entity_constants() ........................................................................... 5-41 $get_hdl_entity_generics()............................................................................. 5-42 $get_hdl_entity_libraries() ............................................................................. 5-43 $get_hdl_entity_packages() ........................................................................... 5-44 $get_hdl_entity_statements() ......................................................................... 5-45 $get_instance_architecture_name()................................................................ 5-46 $get_net_hdl_type() ....................................................................................... 5-47 $get_pin_hdl_mode() ..................................................................................... 5-48 $get_pin_hdl_type() ....................................................................................... 5-49 $get_schematic_architecture_name()............................................................. 5-50
vi
Table of Contents

$set_default_architecture_name() .................................................................. 5-51 $set_default_pin_hdl_type() .......................................................................... 5-53 $set_hdl_entity_constants()............................................................................ 5-54 $set_hdl_entity_generics() ............................................................................. 5-55 $set_hdl_entity_info() .................................................................................... 5-56 $set_hdl_entity_libraries() ............................................................................. 5-58 $set_hdl_entity_packages()............................................................................ 5-59 $set_hdl_entity_statements().......................................................................... 5-60 $set_instance_architecture_name() ................................................................ 5-61 $set_net_hdl_type()........................................................................................ 5-62 $set_pin_hdl_mode()...................................................................................... 5-64 $set_pin_hdl_type()........................................................................................ 5-65 $set_schematic_architecture_name() ............................................................. 5-66 Chapter 6 Shell Command Dictionary ................................................................................ 6-1 Introduction......................................................................................................... 6-1 vhdlwrite .......................................................................................................... 6-2 Index
vii
Table of Contents
LIST OF FIGURES
Figure 4-1. Overriding the Architecture or Configuration Name...................... 4-4 Figure 4-2. Handling Pins of Mode OUT ........................................................ 4-14 Figure 4-3. Mapping Bus Rippers ................................................................... 4-16 Figure 4-4. Mapping Parameterized Bus Rippers............................................ 4-17 Figure 4-5. Schematic with Complex Bus Structures...................................... 4-18 Figure 4-6. For Frame...................................................................................... 4-22 Figure 4-7. Bus/Bundle Connections that Do Not Map .................................. 4-25 Figure 4-8. Two Ports Shorted Together ......................................................... 4-25 Figure 4-9. Unnamed Nets that Connect Two Wide Pins ............................... 4-26 Figure 4-10. Global Net Ripped from a Bus.................................................... 4-26 Figure 4-11. Pin Names Referencing a Bus..................................................... 4-27
viii
Table of Contents
LIST OF TABLES
Table 2-1. Adding VHDL Information to a Symbol ......................................... 2-2 Table 2-2. Adding VHDL Information to a Schematic ..................................... 2-4 Table 2-3. Options File Keywords and Arguments ........................................... 2-8 Table 2-4. String Length Restrictions .............................................................. 2-20 Table 2-5. Naming Conventions for Output Files ........................................... 2-25 Table 2-6. Keyword Substitution in Compilation Template ........................... 2-27 Table 3-1. Symbol Properties Mapped to VHDL ............................................ 3-11 Table 3-2. Symbol Body Properties Added to a Generated Symbol ............... 3-14 Table 3-3. Properties Added to Generated Symbol Pins ................................ 3-14 Table 4-1. Mapping Wide Pins to VHDL Text .............................................. 4-7 Table 4-2. Inferred Signal Width & Data Type for Bus-Ripped Signals ........ 4-10 Table 4-3. Initial Default Scalar/Vector Data Type ......................................... 4-11 Table 4-4. Mapping PINTYPE to VHDL Mode ............................................. 4-13 Table 4-5. Mapping PIN Name to Signal Direction ........................................ 4-13 Table 4-6. Schematic Properties Mapped to VHDL ........................................ 4-28 Table 5-1. Summary of VHDLwrite Functions ................................................. 5-4
ix
About This Manual
VHDLwrite is a product that provides the functionality to generate and export VHDL source code from a specified Mentor Graphics component structure, design viewpoint, or EDDM single-object netlist. VHDLwrite is packaged as a Design Architect(DA) Personality Module, an extension to the AutoLogic I and Design Viewpoint Editor User Interface, or as a standalone batch utility. When invoked from a Mentor Graphics application, the functionality appears as a tightly integrated part of the user interface. This VHDLwrite User's and Reference Manual is part of a VHDLwrite Doc Set that also contains VHDLwrite Release Notes. Training exercises using Design Architect, VHDLwrite and ModelSimTM EE/PLUS* can be found in the Getting Started with QuickSim Pro training workbook. For Microsoft Windows NT users, this symbol identifies unique information for using VHDLwrite on a Windows NT platform.
NT
On-line Documentation
This application uses Adobe Acrobat Exchange as its online documentation and help viewer. Online help requires installing the Mentor Graphics-supplied Acrobat Exchange program with Mentor Graphics-specific plugins and also requires setting an environment variable. For more information, refer to the section, Setting Up Online Manuals and Help in Using Mentor Graphics Documentation with Acrobat Exchange.
___________________ * ModelSim EE/PLUS is referred to as ModelSim from now on.
xi
Year 2000 Ready
About This Manual
Year 2000 Ready

VHDLwrite, as an internally developed product, has been rigorously reviewed, thoroughly tested, and is fully certified as Year 2000 ready. By the phrase Year 2000 ready, Mentor Graphics means this product will be able to function correctly within and between the 20th and 21st centuries, provided that all other computer products used with it exchange accurate date information. Existing Mentor Graphics products will determine the proper century based upon the following convention:
A two-digit year of 00 through 68 will be interpreted as years 2000 through

2068;
a two-digit year of 69 through 99 will be interpreted as years 1969 through

1999. Be aware that Mentor Graphics is not able to independently certify Year 2000 readiness of software products from third-party vendors or of customer-generated code which links with this product at runtime.
xii
Chapter 1 VHDLwrite Overview
Introduction
VHDLwrite is a tool that generates plain-text VHDL structural source code from unevaluated design data (a Mentor Graphics component structure), evaluated design data (a Mentor Graphics component structure as seen through a viewpoint) and from a single-object EDDM netlist. VHDLwrite can be added to Design Architect (DA) through a personality module, it can be invoked from the Autologic I or Design Viewpoint Editor User Interface, or it can be invoked in batch mode from a Shell. The design data can be represented by a schematic and symbol inside a newly created or previously created Mentor Graphics component structure. A VHDL entity source file is generated from the information on the symbol and a VHDL architecture source file is generated from the schematic. If the component structure represents the top level of a hierarchical design, VHDLwrite generates an entity and an architecture for each non-primitive (schematic-based) component in the design hierarchy, unless specifically instructed not to do so. Although you will generally provide VHDL export setup values and options before generating the source files, VHDLwrite does not require you to do so. Pre-set default values allow you to quickly generate the VHDL files provided the schematics and symbols have been successfully checked and do not contain constructs that violate the VHDL code generation rules. A number of new functions are added to an applications user interface in order to provide you with greater flexibility and control over the VHDL output. You can use these functions in AMPLE scripts to automatically add VHDL-specific properties to schematics and symbols before the code is generated or you can use them interactively to add VHDL information to the design in the Schematic and Symbol editors.
1-1
VHDL Export Procedure
VHDLwrite Overview

Default Path Options Path Customization Path
(optional) Inspect the Design for Incompatible Constructs
Add Custom VHDL Information to Symbols and Sheets
Check and Save Each Symbol Check and Save Each Schematic
Verify VHDL Export Options (Modify Options)
(optional) Execute File > VHDL Export > Check Only
Execute File > Export VHDL
(optional) Inspect and Verify VHDL Source Files
1-2
VHDLwrite Overview

The basic procedure for generating VHDL source code is as follows: 1. (optional) Visually inspect each symbol and schematic in your design hierarchy for constructs that will not translate to VHDL. Remove or replace these constructs with valid VHDL-compatible design objects. A partial list of these schematic constructs can be found on page 4-24. 2. (optional) Add VHDL information to Symbols and Schematics. 3. (optional, but highly recommended) Verify that each symbol in the design has been checked without errors. a. From the DA Symbol Editor, execute Check > Symbol on unchecked symbols used in the design hierarchy. b. Make corrections and repeat the process until no errors are reported. c. Execute File > Save Symbol 4. (optional, but highly recommended) Verify that each schematic in the design has been checked without errors. a. From the DA Schematic Editor, execute Check > Schematic on each unchecked schematic in the design hierarchy. b. Make corrections and repeat the process until no errors are reported. c. Execute File > Save Schematic 5. (optional) Verify that the VHDL Export options are set as you desire. Execute Check > Export VHDL until no errors are reported. 6. Generate the code. Execute File > Export VHDL 7. (optional) Open the newly generated VHDL source files. Visually inspect and verify that the code reflects the intent of the schematic-based design.
1-3
Exporting VHDL to a Source Directory
VHDLwrite Overview

Design Specified Here Export VHDL
Navigator... Component/Viewpoint: $DESIGN/card_reader Model Label: schematic Output to: Each Component
(Not used for viewpoint) Directory
Output to Path: $QSLAB/card_reader_src VHDL Units to Generate Entity and Architecture Entity Only Architecture Only Options Control Reset to Defaults Modify Options... Load from File... Messages
Target Source Directory No notes Specified Here

Check Only No warnings
OK
Reset
Cancel
$DESIGN
$QSLAB/card_reader_src
card_reader $DESIGN/card_reader
card_reader_ent
card_reader_structural_arch
analog_ent card_reader schematic

dvpt
add_convert_ent
freq_det_ent
access_chk_ent
part
viewpt1
1-4
VHDLwrite Overview

The illustration to the left shows how VHDL source files are generated from a hierarchical design called $DESIGN/card_reader. The export operation has the following characteristics:
The design may be the path to an mgc_component structure, a design

viewpoint or a single-object EDDM netlist that is generated by AutoLogic.
The target source directory $QSLAB/card_reader_src specifies where the

VHDL source files are to be placed. If the specified target directory does not exist, the directory is automatically created by VHDLwrite.
Both entity declarations and architecture bodies are generated for

card_reader. When VHDLwrite finds an error in the design source, an error message is issued to the transcript. VHDLwrite will generate as much VHDL as possible. You should always examine the transcript after an export operation for possible error messages and, if found, realize that the generated code may contain errors.
!
Caution
Selecting the Load from File... button causes VHDLwrite to first reset all the option settings to their default values, then load the options configuration as defined in the specified options file.
References to the VHDLwrite options file (which can have any name you want), are shown in italic font to emphasize that these references are all to the same file.
1-5
Modifying the Export Options
VHDLwrite Overview
Modify Options
Libs/Pkgs... Archs/Configs... Compile... Generics... Primitives... Types... Name Mapping... Misc Options...
Reset to Defaults
Save to File...
Merge from File...
OK
Reset
Cancel
Resets the current options settings to system-defined default values
Merges the options settings from a specified file to the options settings currently in memory
Saves the current option settings to a specified file
1-6
VHDLwrite Overview

When you select the Modify Options... button on the File > Export VHDL dialog box, the Modify Options dialog box appears as shown on the opposite page. You may then change the options by selecting a category represented by one of eight buttons. Additional dialog boxes pop up requesting information: These are explained on the pages that follow. When VHDLwrite is invoked from Design Architect or the Design Viewpoint Editor, the options you specify are held in memory even after the export operation is complete. This allows you to re-invoke VHDLwrite repeatedly without having to specify the options each time. If you want to save a particular options setup, you must explicitly save the setup to an options file by selecting the Save to File... button. You may import an options setup that was saved by selecting Load from File... in the Export VHDL dialog box. All options specified in the file overwrite the corresponding option setting that may currently be in memory. Selecting the Merge from File... button merges the options settings from the file you specify with the option settings currently in memory. Option settings already set manually through the User Interface are not overwritten by a corresponding option specification statement that may be in the file. Selecting the Reset to Defaults button returns all option settings to their system defined default values. See the Options File Example on page 1-24.
1-7
Miscellaneous Options
VHDLwrite Overview
(showing default settings)
Modify Options
Reset to Defaults
Save to File...
Merge from File...
OK Reset Cancel Miscellaneous Options

Replace Files ALL NONE Single File Netlist Yes No
Configurations IN-LINE IN-FILE NONE
Vector Direction AS-IS TO
Component Decls IN-LINE IN-FILE NONE Alias Rippers On Off Asserts Yes No
NON-PRIMS
3
Off
2 7
DOWNTO Coalesce Wide Pins On
QuickSim Port Mode On Off LRM Vital 87 93 Yes No OK
Alias Netcon On Off
Descend Yes No
Verbose Yes No
14
10
Reset
Cancel
13
12
11
1-8
VHDLwrite Overview
(1) Component Decls. For components referenced by the map library options, tells VHDLwrite to place the generated architecture (IN-LINE) or in a package located in a separate file (IN-FILE). The NONE option suppresses those component declarations. (Assumes that there is an existing package which should be referenced with the default_libs and default_pkgs option.) (2) Vector Direction. Changes all vectors to be ascending A(0:7) or descending A(7:0) or as-is. (3) Configurations. Tells VHDLwrite where to place configuration statements. (4) Replace Files. Gives VHDLwrite permission to overwrite an existing file of the same name in the target source directory. (5) Single File Netlist. Yes tells VHDLwrite to place all generated entities and architectures into a single source file. (6) QuickSim Port Mode. On tells VHDLwrite to use the first letter of the pin name to determine the port mode(direction). See the section Determining Port Mode (direction) on page 4-12. (7) Coalesce Wide Pins. On tells VHDLwrite to coalesce symbol pins of the form (Q(0), Q(0)...Q(7)) into a single VHDL vector Q with a range of (0 to 7). (8) Alias Rippers. Off tells VHDLwrite not to create aliases for unnamed nets that are ripped off a bus. (9) Alias Netcon. Off tells VHDLwrite not to create aliases for unnamed netcon bits. (10) Asserts. Yes tells VHDLwrite to place Assert statements explaining VHDLwrite assumptions into the exported VHDL source code. (11) Verbose. Yes tells VHDLwrite to output detailed messages describing the progress of the VHDL code generation. (12) Descend. Yes tells VHDLwrite to generate VHDL for all symbols and schematics in the design hierarchy. Any object marked primitive stops the descent on that leg of the hierarchy. See Primitive Control Options on page 1-16. (13) Vital. Yes tells VHDLwrite to make the generated VHDL code compliant with VITAL (VHDL Initiative Toward ASIC Libraries). (14) LRM 87 identifiers are restricted to letters, digits and the underline character(_). LRM 93 identifiers may be any sequence of graphic characters enclosed in back slashes(\). If LRM 93 is used, also set the compilation options to use the 93 switch. (See page 1-22.)
1-9
Libraries and Packages Options
VHDLwrite Overview
Modify Options
Reset to Defaults
Save to File...
Merge from File...
OK
Reset
Libraries & Packages
Cancel
Default Libraries (Valid VHDL) LIBRARY ieee; LIBRARY my_parts_lib; Default Packages (Valid VHDL) USE ieee.std_logic_1164.ALL; USE my_parts_lib.my_package.ALL;
OK
Reset
Cancel
Tells VHDLwrite to include the specified LIBRARY statements in the entity source file
Tells VHDLwrite to include the specified USE statements in the entity source file
1-10
VHDLwrite Overview

When you click the Libs/Pkgs... button, the Libraries & Packages dialog box pops up as shown on the opposite page. The VHDL statements you enter into the list boxes are directly inserted into the entity source code. Since VHDLwrite does not check the statements for valid VHDL syntax, invalid statements will cause compile errors when the entity source code is compiled.
1-11
Types Options
VHDLwrite Overview
Types Options
Modify Options
Lies/Pegs... Archs/Configs... Compile... Generics... Primitives... Types... Name Mapping... Misc. Options...
Reset to Defaults
Save to File...
Merge from File...
OK
Reset Cancel Types Options std_logic std_logic_vector
Default Scalar Type: Default Vector Type:
Scalar/Vector Table (<scalar> : <vector>)
bit:bit_vector std_logic:std_logic_vector std_ulogic:std_ulogic_vector

Auto Type Conversion Table (<driver> <reader> <function>)
OK
Reset
Cancel
1-12
VHDLwrite Overview
Types Options
Types Options
The figure to the left further illustrates how to set the options for a VHDL export operation. When you click the Types... button, the Types Options dialog box pops up. Scalar/Vector Table Sets the mapping between a scalar type on a scalar object and a vector type on a vector object. VHDLwrite always expects to find a scalar type assigned to a wire and a vector type assigned to a bus. Therefore, if you unintentionally assign a vector type like std_ulogic_vector to a wire on a schematic (for example), or assign a scalar type like std_ulogic to a bus, VHDLwrite will issue an error message. See the discussion on page 4-11. Auto Type Conversion Table Allows you to specify two different type marks and the type conversion function needed to convert the first type mark into the second. For each pin to net connection, the first argument corresponds to the type mark of the driver and the second argument corresponds to the type mark of the receiver. The type conversion function will be inserted in the port map connecting the pin to the signal. The function name is specified as the third argument and should not include the function parentheses, because the parentheses get added automatically when the conversion function is inserted in the port map. You must supply the conversion function in a package and make the package visible by adding the package to the design using the VHDLwrite default_libraries and default_packages option or the da_hdl_libraries and da_hdl_packages property on the root symbol.
1-13
Generics Options
VHDLwrite Overview
Generics Options
The generic named delay1 of type Modify Options
Libs/Pkgs... Archs/Configs... Compile... Generics...
time with a default value of 5 ns is added Primitives... to the entity and component Name Mapping... declarations for component card_reader Types... Misc Options...
Merge from File...
Reset to Defaults
Save to File...
Generics
[conditional] component <component[ :intf]> <name <type> [:= <default>] [conditional] library <libraryPath> <name> <type> [:= <default>]
OK
Reset
Cancel
Add: Add Quoted: (will doublequote all values)
component $QSLAB/component_lib/card_reader delay1 time : = 5 ns library $QSLAB/component_lib delay2 time := 10 ns
<component[ :intf] > <name>
Delete:
$QSLAB/component_lib/card_reader RED_LED
OK
Reset
Cancel
A generic named delay2 of type time with a default value of 10 ns will be declared in every entity source file generated from components in component_lib
The generic RED_LED is not included in the entity and component declarations for card_reader
1-14
VHDLwrite Overview
Generics Options
Generics Options
There are two ways to flag properties as generics in a design. 1. You can open the Design Architect Symbol Editor on a symbol and add generics to the symbol body using the popup menu item Set VHDL Info > Generics. You must then check and save the symbol, then update, check and save any sheets that include instances of the symbol. Adding Generic information to a symbol is further explained on page 1-26. 2. You may also associate generic information with a component or with a library of components as shown on the opposite page. The advantage of this method is that editing changes to the design are not required. These two alternatives flag symbol/instance properties as VHDL generics. Either method defines the generic statements which appear in the VHDL entity and component declarations while the associated symbol/instance properties determine the value passed in the VHDL generic map. If you enter generics in the Add Quoted: entry box rather than the Add: box, the value of the generic will always be double quoted in the VHDL source code. A detailed discussion of generics and more examples can be found in the section Handling Generics on page 3-6.
1-15
Primitive Control Options
VHDLwrite Overview

Modify Options
This tells VHDLwrite Libs/Pkgs... to generate an entity, Compile... for the primitive objects specified below. Archs/Configs... Generics...
Reset to Defaults
Primitives... Types...
This tells VHDLwrite to generate a black box Name Mapping... (empty) architecture body, for the primitive objects specified below. Misc Options...
Save to File...
Merge from File...
This tells VHDLwrite OK to treat all components in these libraries as primitive
Reset Primitive Cancel Control Primitive Units:
Entity
Architecture
Libraries (<library_path>) $MGC_GENLIB $MGC_STDLIB Components (<component_path>) $QSLAB/component_lib/card_reader/access_chk $QSLAB/component_lib/card_reader/analog $QSLAB/component_lib/card_reader/freq_det Schematics (<schematic_path>) $QSLAB/component_lib/my_dff/schematic $QSLAB/component_lib/my_dff/schematic2 Netlists (<netlist_path>)
This tells VHDLwrite to treat these specific components as primitive

OK Reset Cancel
This tells VHDLwrite to treat these schematic objects as primitive
1-16
VHDLwrite Overview

When you click the Primitives... button, the Primitive Control dialog box appears. The callouts explain these options. Remember that the term primitive means non-schematic. Therefore, when VHDLwrite descends down a design hierarchy, it stops at every object labeled primitive and descends no further, even though there may be a schematic model underneath. (See also the topic Overriding the Arch or Config Name on page 1-30 for other ways to control the descent into the design hierarchy. With the Primitive Units buttons set as shown in the illustration on the left, an entity declaration and a black box (empty) architecture body is generated for the objects specified as primitive in the lower part of the form. If, for example, VHDLwrite descends into a schematic containing an instance of a component located in libraries $MGC_GENLIB or $MGC_STDLIB, then an entity declaration and a black box architecture body is generated for that instance. If the Architecture button is not set, then an architecture body is not generated for the instance. Suppressing All VHDL Code for Objects Declared Primitive If both the Entity and the Architecture buttons are clicked OFF in the Primitive Control dialog box, then all VHDL code is suppressed for all the objects specified as primitive in the dialog box. Using a Viewpoint to control Descent If VHDLwrite is invoked on a design through a Design Viewpoint, then descent of VHDLwrite down through the hierarchy may be controlled by the viewpoints Primitive Rule as well as through the VHDLwrite Primitive Control options. When VHDLwrite is invoked on a design through a Design Viewpoint, the VHDLwrite Primitive Control options override the Primitive Rule in the Viewpoint. The concept of a Design Viewpoint is summarized on page 1-38. The Design Viewpoint Editor Users and Reference Manual has more in-depth information. VHDL code can also be suppressed for all schematic sheets below the root schematic on down by setting the descend option to OFF. See item (7) in the illustration on page 1-9.
Note
1-17
Archs and Configs Options
VHDLwrite Overview

Modify Options
Reset to Defaults
Save to File...
Merge from File...
Architectures & Configurations

Default Architectures (<library_path> <architecture_name>) OK Reset Cancel $QSLAB/component_lib behav1
Default Configurations (<library_path> <configuration_name>) $QSLAB/component_lib config1
OK
Reset
Cancel
If not specified elsewhere, this tells VHDLwrite to use the architecture name behav1 for all VHDL configuration specifications generated from symbols in the $QSLAB/component_lib MGC component library. If not specified elsewhere, this tells VHDLwrite to use the configuration name config1 for all VHDL instances generated from symbols in the $QSLAB/component_lib MGC component library.
1-18
VHDLwrite Overview

When you click the Archs/Configs... button, the Architectures & Configurations dialog box appears as shown on the left. There are several different ways to specify an architecture or configuration name. The search rules for determining which name is used are summarized on page 1-30.
Note
1-19
Name Mapping Options
VHDLwrite Overview

Modify Options
Generate a name Reset to Defaults Save to File... Merge mapping from File... file for Map invalid userName Mapping Options each architecture defined VHDL identifiers to Generate Mapping Map User OK Names Reset Cancel File valid VHDL Yes Yes
No No
component <component[ ::intf]> {<(property_name)> | <entity_name>} library <Mentor_libraryPath> <(propertyName)>
Map Entity Name:
component $QSLAB/component_lib/my_dff library $LSLIB (COMP)
\7474\
{<Mentor_libraryPath> <VHDL_libraryName> [<VHDL_libraryPath>]}
Map Library:
$QSLAB/component_lib
my_parts_lib
$QSLAB/my_parts_lib
Use the entity name \7474\ for all OK Reset instances of the component at pathname $QSLAB/component_lib/my_dff
Cancel
For all instances in the library $LSLIB, use the value of the COMP property as the entity name For all VHDL instances generated from symbols in $QSLAB/component_lib use my_parts_lib as the VHDL logical library name instead of work. The logical library my_parts_lib is located at path $QSLAB/my_parts_lib.
1-20
VHDLwrite Overview

When you click the Name Mapping... button, the Name Mapping Options dialog box pops up. The callouts explain the options. Map User Names The Map User Names option has a different effect, depending on the setting of the LRM option as shown on page 1-8. If the LRM options is set to 87, then illegal characters are mapped to legal characters. See the section Rules for Name Mapping on page 3-2 If the LRM option is set to 93, then extended identifiers are generated. Refer to the section Mapping Names on page 3-2 for details.
1-21
Compilation Options
VHDLwrite Overview
Compilation Options
Modify Options
Libs/Pkgs... Compile... Primitives... Name Mapping...
Archs/Configs...
Generics...
Types...
Misc Options...
Save to File... Merge from File... 1 Reset to Defaults Compilation Options
2 3
Work Library:
Compilation Script Automatic Compilation OK Reset Cancel Yes Yes No Default No ModelSim LRM 87 93
6
Other Compiler
Compilation Template From: $LIBPATH
Start Compiler at Line #:
Load Standard Package
No Warnings for: Unbounded Component Process without Wait Stmt
Print VHDL Source line w/errors No STD 1164 Range Checking Explicit scoping No Debug
Null Range No Space in TIme Literal Multiple drivers on Unresolved Signal
OK
Reset
Cancel
1-22
VHDLwrite Overview
Compilation Options
Compilation Options
When you click the Compile... button, the Compilation Options dialog box pops up. The paragraphs below explain the callouts on the left: (1) Yes tells VHDLwrite to create a compile shell script for the generated design units. (2) Click one of these buttons to specify which compiler to use. ModelSim compile options are specified in the areas marked by the (5) and (8). (3) This entry box specifies the path to the VHDL logical library where the compiled code will be placed. The value of the compile template keyword $LIBPATH is used as the default. If the keyword $LIBPATH is specified, the VHDL library name specified in the Map Library option is used as the working library. See the section Compiling the VHDL Source on page 2-26. (4) You may specify the line number in the source file where the compiler is to start. (5) This is the area where you specify ModelSim compiler options. (6) Yes tells VHDLwrite to automatically execute the generated compile script after the netlisting operation is complete. If errors are reported during the netlisting operation, the automatic execution of this script is suppressed. (7) This option sets the LRM compile switch to either 87 or 93. (8) These buttons allow you to turn off the specified warning messages during the ModelSim compile operation. Sometimes a Warning message similar to Warning: No default binding for... is issued while the compilation script is running. This warning can be ignored. It occurs when the name of an architecture body, which has not yet been compiled, appears in a configuration statement.
Note
1-23
Options File Example
VHDLwrite Overview

# vhdlwrite options file descend on override_vectors as-is primitive_units entity default_scalar_type std_ulogic default_vector_type std_ulogic_vector scalar_vector_table reset scalar_vector_table bit:bit_vector scalar_vector_table std_logic:std_logic_vector scalar_vector_table std_ulogic:std_ulogic_vector lrm 93 map_user_names on map_file on configurations inline compilation_script on replace_files all primitive_library $MGC_GENLIB primitive_component $QSLAB/component_lib/analog primitive_component $QSLAB/component_lib/freq_det primitive_component $QSLAB/component_lib/access_chk primitive_schematic $QSLAB/component_lib/my_dff/schematic primitive_schematic $QSLAB/component_lib/my_dff/schematic2 default_libraries LIBRARY ieee; default_libraries LIBRARY my_parts_lib; default_libraries LIBRARY card_reader_lib; default_packages USE ieee.arithematic.All; default_architecture $QSLAB/component_lib behav1 asserts on verbose on #default_configuration $QSLAB/component_lib config1 map_library $QSLAB/component_lib card_reader_lib $QSLAB/card_reader_lib single_file_netlist off automatic_compilation on vital_compliance off compilation_template $MTI_HOME/bin/vcom -93 -work $LIBPATH -source -map card_reader_lib $QSLAB/card_reader_lib #add generic $QSLAB/component_lib/add2 MODEL string $hdl #delete_generic
1-24
VHDLwrite Overview

An ASCII text options file may be used to first hold and then load a particular set of VHDLwrite options into memory. An options file may also be used to specify options when VHDLwrite is invoked directly from a shell. The figure to the left illustrates the actual contents of an options file. This file may be overwritten from the File > Export VHDL > Modify Options... form or it may be edited with any ASCII text editor. Notice the following characteristics:
Some keywords such as descend

switches like nodescend.
on may be overridden by invocation
Only one argument may be specified in some statements like

primitive_library, but the statement may be included any number of
times to add libraries to the Primitive Libraries Table.
Arguments to keywords like default_libraries and

default_packages are inserted directly into the code, so they must be
valid VHDL statements with an ending semicolon. A second default_libraries keyword appends the second statement to the first. The same is true for the default_packages statements. The __da_hdl properties on the symbol override the default values specified in this file. When VHDLwrite is executed from a shell, it locates the options file by applying the following ordered list of rules: 1. Use the value of the options file pathname supplied with the -options switch. 2. Look for a file named vhdlwrite.options in the current working directory. (This working directory may be overridden by the value of the shell environment variable MGC_WD, if set.) 3. Look for a file at the location $HOME/mgc/vhdlwrite/options. 4. Look for the file $MGC_HOME/pkgs/vhdlwrite_da/doc/default_options.
1-25
Adding VHDL Information to a Symbol
VHDLwrite Overview

bit 2 __da_hdl_port_type RED_LED_RISE RED_LED_FALL PINTYPE
CARD_READER
RED_LED PINTYPE in RF_IN GREEN_LED
4 out
out inout bit
PINTYPE __da_hdl_port_mode __da_hdl_port_type __da_generic_GREEN_LED_RISE __da_generic_GREEN_LED_FALL
MODEL __da_hdl_lib_name __da_hdl_arch_name __da_hdl_libraries __da_hdl_packages __da_hdl_entity_name __da_hdl_constant __da_hdl_statements
schematic ls_lib struc
time := 5 ns time := 10 ns
LIBRARY ieee, my_vhdl_lib; USE ieee.std_logic_1164.all;USE my_vhdl_lib.my_package.all; card_reader CONSTANT pi :real := 3.14; (Logical Symbol Body Properties)
ASSERT GREEN_LED_FALL > 15;
----------------------------------------------------------- VHDL object: Entity"card_reader"(component interface"$DESIGNS/card_reader -- Generated on : Wed Jan 12 16:03:11 1994 -- Generated by: ellisc -- Source information: $DESIGNS/card_reader/part -- VHDLwrite version: v8.2_10.1 Fri Jan 7 19:00:03 PST 1994 ----------------------------------------------------------- LIBRARY STATEMENT LIBRARY ieee,my_vhdl_lib; --PACKAGE STATEMENT USE ieee.std_logic_1164.all;use my_vhdl_lib.my_package.all; USE work.card_reader_global_signals.ALL; entity card_reader is -- GENERIC LIST generic ( green_led_fall : time := 10ns; green_led_rise : time := 5ns ); -- PORT LIST port ( GREEN_LED : inout bit; RED_LED : out bit; RF_IN : in std_ulogic ); --CONSTANTS constant pi:real:= 3.14; begin -- ENTITY STATEMENTS -- ENTITY STATEMENTS assert GREEN_LED_FALL > 15; REPORT FALL time exceeded; end card_reader;
1-26
VHDLwrite Overview

The figure to the left illustrates how VHDL-specific information can be added to a symbol and exported to the entity source file. The VHDL information is included as __da_hdl property values, which are attached to the symbol as symbol body properties and/or logical symbol body properties. The __da_hdl properties can be added using the menus from the Symbol Editor or they can be added automatically using the VHDLwrite functions in AMPLE scripts. See Function Dictionary on page 5-1 for available functions. Port Mode The port mode is determined by the PINTYPE property, unless the __da_hdl_port_mode property is attached to a pin. The RF_IN pin and the RED_LED pin are assigned port mode in and out, respectively. The __da_hdl_port_mode property value inout is attached to the GREEN_LED pin and overrides the value of the PINTYPE property. Port Type The port type is assigned the default type that is called out in the specified options unless the value is overridden by the value of the __da_hdl_port_type property. In this case, the RF_IN port is assigned a default type of std_ulogic; however, the output ports are assigned a bit type as specified by the __da_hdl_ port_type property. (This has been done just for illustration purposes.) Generics Only the logical symbol body property values added to the symbol as __da_generic properties are passed into the code as generics. Notice that the RISE and FALL properties attached to the RED_LED pin are not included in the source file. However, the rise and fall values of the GREEN_LED pin are included because they are added as __da_generic properties. If you want to pass the value of a symbol body property into the code as a generic, you can attach a __da_generic logical symbol body property by the same name, assign it a type and not assign it a default value. For example, adding a __da_generic_ MODEL logical symbol body property to the symbol and only assigning it a value like string causes VHDLwrite to search for the value of the MODEL property. The statement MODEL : string := schematic would then be inserted into the GENERIC LIST for the VHDL component. If the value of the MODEL property on a schematic instance is changed, then that changed value is passed into the generic map for that VHDL instance. For details and more examples, refer to the section Handling Generics on page 3-6.
1-27
Adding VHDL Information to Schematic
VHDLwrite Overview

OSC ADDRESS_IN
FREQ_DET
_CLR LATCH PULSE START
__da_hdl_arch_name
custom
OSC START PULSE LATCH SERIAL_OUT RF_IN RF_IN _CLR
ACCESS_CHK
RED_LED DATA_BUS(15:0) READ GREEN_LED _CLR GREEN_LED RED_LED
ANALOG INST
ANALOG1 LATCH PULSE START
NET
ABUS(15:0)
NET
ADDRESS_IN
_CLR
ACCESS(15:0) READ
ADDRESS_IN
ADD_CONVERT
MODEL
schematic
architecture structure of card_reader is -- TYPE DECLARATIONS -- SIGNAL DECLARATIONS signal ABUS : std_ulogic_vector(15 to 0); signal . ADDRESS_IN : std_ulogic; signal \N$10\ : std_ulogic; signal \N$6\ : std_ulogic; -- COMPONENT DECLARATIONS component ANALOG port ( SERIAL_OUT : out std_ulogic; OSC : out std_ulogic; RF_IN : in std_ulogic; /_CLR/ : out std_ulogic ); . end component; -- INLINE CONFIGURATIONS for \I$210\ : ACCESS_CHK use entity my_parts_lib.ACCESS_CHK(custom); . for \I$211\ : ADD_CONVERT use entity card_reader_lib.ADD_CONVERT(struct for ANALOG1 : ANALOG use entity my_parts_lib.ANALOG(behav1); -- COMPONENT INSTANTIATIONS ANALOG1 : ANALOG port map( SERIAL_OUT => ADDRESS_IN, OSC => \N$6\, RF_IN => RF_IN
1-28
VHDLwrite Overview

VHDLwrite will generate valid VHDL code using net handles (like N$5) for internal signal names and instance handles (like I$256) for component instantiation labels. This, however, makes it harder to debug the code in the simulator because you may not remember the net handle of a particular wire. It is a good practice to assign NET properties to important internal nets and give them easy-to-remember values. It is also a good practice to do the same with instances by assigning instance-specific INST property values. The illustration on the left shows how a NET property value is mapped to a VHDL signal name and how an INST property value is mapped to a component instantiation label. Architecture Name for Each Instance If an architecture name is specified for an instance by attaching a __da_hdl_arch_name property, VHDLwrite treats the instance as primitive and uses the architecture name in the binding indication for that instance. This feature allows you to change a binding on an instance without editing the VHDL source file after it is generated. This is illustrated in the figure on the left with the ACCESS_CHK instance. The complete set of rules for determining the overriding architecture name for an instance is covered on the next page. Assigning a Net Type Typically, the net type of a particular net is assumed from the pin type assigned to the symbol pins to which the net is connected. VHDLwrite allows you to assign a net type to a net by attaching a __da_hdl_net_type property to the net, but this is not a common practice. In addition, the net type must match the pin type of the connected pins, or an error results. Assigning a Pin Type A VHDL pin type property can only be assigned to symbol pins (on a symbol), not instance pins on a schematic. It is possible to attach a __da_hdl_pin_type property to an instance pin by using the regular methods of adding properties, but VHDLwrite ignores a property like this.
1-29
Overriding the Arch or Config Name
VHDLwrite Overview

OU T0
N0
_ MY
IN 1
DE
G SI
OU
T1
OU
T2
__da_hdl_default_arch_name
IN
custom
Schematic Design Object

LA TC H TC H TC H
LA
4
Options File
# vhdlwrite options file descend on makefile on compilation_script on verbose on asserts on default_architecture $LIB behav default_configuration $LIB2 config1
Q T LA CH
LA
6
$schematic
__da_hdl_arch_name
Instance Body
1 3
R
LA
H TC
S
__da_hdl_arch_name
Q
behav_hi_speed
Symbol Body
Q
2
__da_hdl_arch_name
Q
behavior
1-30
VHDLwrite Overview

If a default architecture or configuration name is specified for an instance, VHDLwrite treats the instance as primitive and determines the overriding architecture or configuration name by applying the following rules: (1) If a __da_hdl_arch_name property is attached to the instance and it has a non-empty value, then that value is used for that instance. This property can be added by selecting the instance in the Schematic Editor and executing the menu (Instance Popup)Architecture Name. In the figure to the left, the references to the architecture for the LATCH instance in the lower-left corner will be made to behav_hi_speed. For example, the binding in a configuration statement points to...work.S-R_LATCH(behav_hi_speed). (2) If a valid name is not found, VHDLwrite searches the symbol body for the non-empty value of a __da_hdl_arch_name property. In the figure to the left, the architecture name referenced from the top two instances of LATCH is behavior. (3) If a valid name is not found, VHDLwrite looks to see if the referenced symbol is in a library specified in a default_configuration statement in the options file. If so, the specified configuration name is referenced. In this example, if the __da_hdl properties were not attached to the LATCH instance and symbol as shown, and if the LATCH component was in the $LIB2 library, then the configuration name config1 would be used for all instances of LATCH. (4) If a valid name is not found, VHDLwrite looks to see if the referenced symbol is in a library specified in a default_architecture statement in the options file. If so, the specified architecture name is referenced. (5) If a valid name is still not found, VHDLwrite looks to see if the schematic design object itself has a default architecture name assigned. If a valid architecture name was not found up to this point, the name custom would be used. (6) If the overriding architecture name is found to be $schematic, VHDLwrite assumes the instance is not primitive. This feature allows you to override the override on one or more instances. For example, in the illustration to the left, VHDLwrite looks at the lower-right instance and generates an architecture called structural from the underlying default schematic model.
1-31
Invoking VHDLwrite from a Shell
VHDLwrite Overview

$MGC_HOME/bin/vhdlwrite <component_or_viewpoint_pathname>
Optional Switches -help -model_label -options_file -option_summary -check_only -entity_only | -arch_only -nodescend -nonotes -nowarnings -nowrap -replace -output_to Example 1
Switch Argument
<model_name> <path_to_optionsfile>
[all | none | non_primitives] [component | directory <dir_path>]
$MGC_HOME/bin/vhdlwrite $DESIGN/card_reader -entity_only -nodescend -output_to $DESIGN/card_reader_src Example 2 vhdlwrite $DESIGN/card_reader -options_file $DESIGN/optionsfile -check_only -nonotes -nowarnings -nowrap
1-32
VHDLwrite Overview

The vhdlwrite shell command invokes the VHDLwrite application in standalone mode. If a switch is specified in this command (such as -nodescend) and a keyword in the options file is set differently (such as descend on), the shell command switch overrides the keyword in the options file. If the output_to switch is not specified, then the generated VHDL source files are placed in the current working directory. If the environmental variable $MGC_WD is defined for the shell, the generated files are placed in the directory defined by the value of this variable (unless output_to is defined). Example 1 Meaning: Generate VHDL source from the $DESIGN/card_reader component and place the code in the $DESIGN/card_reader_src directory. Use the default component interface. Only generate an entity and do not descend the design hierarchy. Because -options is not specified, look for an options file called vhdlwrite.options in the current working directory. If not found, look for an options file located at $HOME/mgc/vhdlwrite/options. If there is no options file there, use the default options specified in $MGC_HOME/pkgs/vhdlwrite_da/doc/ default_options. Example 2 Meaning: Perform all Export VHDL validity checks on the $DESIGN/card_reader component. Use the options file at the path $DESIGN/optionsfile. Only output Error Messages. Do not generate any VHDL source files. Tell VHDLwrite that the display does not auto wrap lines. Use the directory $QSLAB/card_reader_work as the work directory. The vhdlwrite_server process stays active for several minutes after netlisting finishes to speed up invocation time on a subsequent run of VHDLwrite. The following UNIX command shows this: $ ps -ef | grep vhdl 9309 9142 2 14:55:35 ttypb 0:00 grep vhdl 9292 1 0 14:50:14 ? 0:01 <$MGC_HOME>/pkgs/vhdlwrite_da/.lib/vhdlwrite_server If you want the process, vhdlwrite_server, to be terminated after each run of VHDLwrite, set the following environment variable: $ setenv MGC_VHDLWRITE_DISABLE_SERVER_REUSE XXXX
Note
1-33
Compiling Source Files for ModelSim
VHDLwrite Overview
$ cd $DESIGN/card_reader_vhdl_source $ ls Directory: $DESIGN/card_reader_vhdl_source
ACCESS_CHK_black_box_arch.vhd ACCESS_CHK_ent.vhd ADD_DET_ent.vhd ADD_DET_structural_arch.vhd ANALOG_black_box_arch.vhd ANALOG_ent.vhd FREQ_DET_black_box_arch.vhd FREQ_DET_ent.vhd card_reader_cfg.vhd compile shell script placed here card_reader_compile.sh card_reader_ent.vhd global_signals_card_reader.vhd card_reader_structural_arch.vhd makefile my_dff.vhd my_dff_structural_arch.vhd $ vlib /tmp/worklib
create a new working library execute the "compile" shell script
$ card_reader_compile.sh
1-34
VHDLwrite Overview

VHDLwrite optionally generates a Bourne shell script that compiles all the generated VHDL source in the following order: 1. package declaring global signals 2. all entities 3. all architectures 4. configuration file (if present) The figure to the left illustrates the contents of a directory containing VHDL source files from the card_reader design. The following list describes a general procedure for compiling the VHDL source with the ModelSim compiler: 1. Identify a location for creating a new working library. For example /tmp/worklib. (The directory worklib must not currently exist at this location.) 2. Execute the following command:$vlib /tmp/worklib This creates a new working library that will receive the compiled VHDL. 3. Next, execute the following command:
$DESIGN/card_reader_source/card_reader_compile.sh
This line executes the card_reader_compile.sh shell script. All the card_reader source files generated from VHDLwrite are compiled one-at-atime and placed in the /tmp/worklib directory. If references are made to architectures that exist outside the schematic-based design, these architectures must be compiled separately and placed in the /tmp/worklib before ModelSim is invoked on the compiled design.
1-35
Frame Example (review)
VHDLwrite Overview

delay_n Symbol
B N od
op Pr
ert
y OU
T
0: T(
N-
1)
_ US
OU
S BU
_IN
N (0:
-1)
IN
N
W ide Pin
E IS TR LL A ) TF ies t 0 r e op 0 Pr y od (B
delay_n Component
BU
de lay
S_
T OU
(J)
_ US
J) N(
E) IS ) R (T ALL F (T -1
for
J:
o 0t
delay_n Schematic FOR Frame

EX PI TE N IT RI SE FA 0 LL
R IN
y ela
YP E
OU 0
EN
delay Symbol
PI
NT
1-36
VHDLwrite Overview

The illustration on the left shows how a FOR frame can be used to create an instance for a bus of varying width. Components similar to the $MGC_GENLIB components delay and delay.n are used in this example. Starting at the bottom of the illustration, the delay symbol is used to represent a given amount of delay on a net. The RISE and FALL properties are owned by the OUT pin and are set to a 0 value. Moving up one level, the delay symbol is instantiated on a sheet in the delay_n component. The values of the RISE and FALL properties are defined to be expressions (TRISE) and (TFALL), respectively. The instance is enclosed by a FOR frame with an expression that is converted to a VHDL generate construct when the component is evaluated by VHDLwrite. The port names on the sheet are defined as array elements that follow the incrementing value of J as the frame is evaluated. If N is defined to be 8, then a VHDL Generate statement is created which produces the same result as if the circuit were included eight times on the sheet. Moving up one level, the symbol for delay_n is shown at the top of the illustration. The symbol owns three body properties N, TRISE, and TFALL that contain values that will be used as parameters for the symbol pins and the sheet below. The symbol pins are called wide pins, because the names are defined in the form of a bus. The names also contain an unknown value N which is defined by the N property on the symbol body. The following illustration shows how the delay_n component might be used.
BUS__IN(0:7)
5 10
BUS__OUT(0:7)
In this example, the delay_n instance is connected to buses that are 8-bits wide. The N property is set to 8. The total delay for each bus wire is specified as 5ns rise time and 10ns fall time. At evaluation time, a delay instance will be generated for each wire on the input and output buses. For details on how FOR frames are mapped to VHDL, refer to the section Mapping Frames on page 4-20.
1-37
Design Viewpoint (conceptual review)
VHDLwrite Overview
Design Architect
SET VIEWPOINT
Design Viewpoint Editor
OPEN SHEET OPEN VPT
Back Annotation Object

(X +5)
15
10
Source Schematic Design Viewpoint
VHDLwrite
15 10
What VHDLwrite Sees
1-38
VHDLwrite Overview

Schematics are represented by files and directories in a software environment, so they can take on some of the characteristics of a software program. A timing value, for example, can be represented by a numeric expression such as (X + 5) as shown in the figure on the left. This expression must be evaluated to a constant before a downstream tool like a simulator can operate on it. The object in the data model that allows a downstream tool to view the source schematic as fully evaluated data is called a design viewpoint. You may conceptually think of a design viewpoint object as a picture frame through which the downstream tool (like VHDLwrite) views the schematic. In your minds eye, think of the image of the source schematic as being reflected onto the back of the glass in the picture frame. Notice in the diagram that VHDLwrite sees the fully evaluated data through the viewpoint (15 in this case) even though the expression on the source schematic (X + 5) doesnt change. The value of X can be defined elsewhere on the schematic or defined in the viewpoint itself. Because the glass in the viewpoint protects the source schematic, you cant change the source schematic from VHDLwrite. You can appear to change the schematic, however, by selecting a property in the Design Viewpoint Editors Schematic View Window and making a change. The change is recorded in a Back Annotation object, which is conceptually represented as a transparent sheet laid over the top of the glass in the viewpoint. In the figure, the timing value in front of the center and gate is changed from 5 to 10 nanoseconds. VHDLwrite sees 10 ns, as shown in the lower figure, even though the source schematic is unchanged. Viewpoints can be created and modified with a tool called the Design Viewpoint Editor. Design Architect (DA) can also invoke on a design viewpoint (using the SET VIEWPOINT icon) as well as on a source schematic. When you open a schematic with the OPEN SHEET icon in DA and then execute File > Export VHDL, VHDLwrite generates VHDL code from the source schematic design (far left). When you open a schematic within the context of a design viewpoint and select FILE > Export VDHL, VHDLwrite generates VHDL code from the evaluated design data as seen through the design viewpoint. Any changes to the design that are made in the viewpoints rules list are seen by VHDLwrite. When you invoke DA on a design viewpoint, you may selectively merge back annotation information from the Back Annotation object onto the source schematic.
1-39
Generating a Symbol from an Entity
VHDLwrite Overview

Generate Symbol
Choose Source Pinlist File ModelSim InitFile: Library Logical Name: Entity Name: Default Architecture: Schematic Entity Set Init File... Choose Library... Choose Entity... Choose Arch...
1. Click
$QSLAB/modelsim.ini work card_reader structure Place Component In
2 3 4 5
6. Enter
Directory:
$QSLAB/component_lib 2 Current Shape Shape Arguments: Sort Pins? Yes No Replace existing? Yes No Choose Shape Activate symbol? Yes No (Symbol must be saved) [2,2]
Pin Spacing (in pin grids)
7. Click
11. Click
OK
Reset
Cancel
Choose a Symbol Shape

Shape: And Gate Min Width: 3 Or Gate Xor Gate Buffer Box AndOr OrAnd
Min Height: 2
8. Verify
OK Reset Cancel
9. Enter
10. Click
1-40
VHDLwrite Overview

A symbol can be generated from a compiled entity by executing the Design Architect session pulldown menu as follows: File > Generate > Symbol. Fill out the dialog box as shown on the left: (1) Click the Entity button. (2) Navigate to and select a valid modelsim.ini file. If an .ini file is not specified, VHDLwrite uses: (a) the value of MODELSIM if set, (b) the modelsim.ini file located in the directory from which DA was invoked, or (c) the modelsim.ini file located in 1) the directory containing the ModelSim executables, or 2) the parent of the ModelSim executables directory. (3) Click Choose Library..., then select a valid logical library name from the list. (4) Click Choose Entity..., then select a valid entity name from the list. (5) (optional) Click Choose Arch..., then select a valid default architecture name from the list. This will cause VHDLwrite to treat the symbol as a primitive when the symbol is instantiated on a sheet. (6) Enter the pathname of a component library. If a component with the same name as the entity does not exist at that location, a new component structure will be created. If a component structure with the same name as the entity does exist at the specified location and Replace existing? is Yes, then the symbol will be replaced with a new symbol. (7) Choose the graphic characteristics of the new symbol. (8) Choose the shape (box in this case). (9) Specify the shape (make the width greater than the height in this case). (10) Execute the Choose a Symbol Shape dialog box. (11) Execute the Generate Symbol dialog box. The new symbol is created, checked and saved to the specified location. The symbol editor is then opened for further editing on the symbol. The results of the Generate Symbol dialog box are recorded on the next page. This function also checks to see if a PARTNER hdl model has been registered with the interface for this symbol and that it is the only model with the label hdl. If it is not present, then a partner model is registered and labeled hdl. If any other model has the label hdl, then a non-fatal error message is issued. For detailed information on how to use this dialog box, refer to the Section, Creating a Symbol for a Sheet in the Design Architect Users Manual.
1-41
Symbol Generation Example
VHDLwrite Overview

----------------------------------------------------------- VHDL object: Entity"card_reader"(component interface"$QSLAB/component_lib/c -- Generated on Wed Sep 2 16:03:11 1998 -- Generated by: davidb -- Source from: $DESIGNS/card_reader/part -- Program: VHDLwrite v8.6_4.1 Fri Aug 21 19:00:03 PST 1998 ----------------------------------------------------------- LIBRARY STATEMENT LIBRARY ieee; --PACKAGE STATEMENT USE ieee.std_logic_1164.ALL; entity card_reader is -- GENERIC LIST generic(delay : time := 2 ns) -- PORT LIST port ( RF_IN : in std_ulogict; GREEN_LED : out std_ulogic; RED_LED : out std_ulogic ); attribute original_name : string end card_reader;
delay : 2 ns OUT RED_LED

STD_ULOGIC
delay property with a value of 2 ns
IN
RF_IN
OUT GREEN_LED
STD_ULOGIC
STD_ULOGIC
MODEL __da_hdl_libraries __da_hdl_packages __da_hdl_entity_name __da_hdl_arch_name __da_hdl_lib_name __da_hdl_suppress_units
hdl LIBRARY ieee; USE ieee.std_logic_1164.ALL; card_reader structure work entity delay(type) : time __da_generic_delay
1-42
VHDLwrite Overview

Information is taken from the specified Entity object and the Generate Symbol dialog box to make the new symbol as shown on the left page. (1) A pin is created for each port name specified in the Entity. A PIN property is attached to each pin with a value equivalent to its corresponding port name. (2) A PINTYPE property is attached to each pin with a value equivalent to the port mode(direction) of the corresponding port. (3) The port type, such as std_ulogic, is attached to the corresponding pin as the value of a __da_hdl_port_type property. (4) The LIBRARY statement(s) in the entity are attached to the symbol as the value of a __da_hdl_libraries symbol body property. (5) The USE statement(s) in the entity are attached to the symbol as the value of a __da_hdl_packages symbol body property. (6) The entity name specified in the Generate Symbol dialog box is attached to the symbol as the value of a __da_hdl_entity_name symbol body property. (7) The default architecture name specified in the Generate Symbol dialog box is attached to the symbol as the value of a __da_hdl_arch_name symbol body property. (The presence of this property on the symbol will cause VHDLwrite to think that the symbol is primitive the next time VHDL code is generated from an instance of the symbol.) (8) The logical library name specified in the Generate Symbol dialog box is attached to the symbol as the value of a __da_hdl_lib_name symbol body property. (9) A __da_suppress_units property is attached to the symbol body with a value of entity. This causes VHDLwrite to suppress the generation of entities from instances of this symbol.
1-43
Importing VHDL Info to a Symbol
VHDLwrite Overview

Import Entity Info
Choose Source Pinlist File ModelSim InitFile: Library Logical Name: Entity Name: Default Architecture: Schematic Entity Set Init File... Choose Library... Choose Entity... Choose Arch...
1. Click
$QSLAB/modelsim.ini work card_reader structure
2 3 4 5
6. Click
OK Reset Cancel
1-44
VHDLwrite Overview

The information contained in the properties on an existing symbol can be updated to match the VHDL information in the specified compiled entity. The VHDL information from the entity is annotated on the symbol pins and symbol body so that when VHDLwrite is used later to generate code from the symbol, the generated code will match the code of the original entity. The VHDL information can be imported by opening a Symbol Editor window on a symbol, then executing the ADD popup menu item Set VHDL Info... > Import from Entity: The procedure for filling out the dialog box is shown on the left and discussed as follows: (1) Click the Entity button. (2) Navigate to and select a valid modelsim.ini file. (3) Click Choose Library..., then select a valid logical library name from the list. (4) Click Choose Entity..., then select a valid entity name from the list. (5) (optional) Click Choose Arch..., then select a valid default architecture or configuration name from the list. This will cause VHDLwrite to treat the symbol as a primitive when the symbol is instantiated on a sheet, then netlisted later by VHDLwrite. Before making any design changes to an existing symbol, VHDLwrite first verifies that the pins on the symbol match the ports in the entity. If they do not match, an error message is issued and no edits are made. The properties added to the symbol are listed in 3-2 and Table 3-3 starting on page 3-14. This function also checks to see if a PARTNER hdl model has been registered with the interface for this symbol and that it is the only model with the label hdl. If it is not present, then a partner model is registered and labeled hdl. If any other model has the label hdl, then a non-fatal error message is issued.
1-45
VHDLwrite Overview
1-46
Chapter 2 The VHDL Generation Process
Although you will generally specify VHDL export setup values and options before generating the source files, VHDLwrite does not required you to do so. Pre-set default values allow you to quickly generate the VHDL provided the schematics and symbols do not contain constructs that violate the code generation rules and the default values are appropriate for you needs. If you are in a DA session, a DVE session or an AutoLogic I session, just execute the menu selection File > Export VHDL and specify a directory path where you want the VHDL source files placed. A number of new functions are added to an applications user interface in order to provide you with greater flexibility and control over the VHDL output. You can use these functions in AMPLE scripts to automatically add VHDL-specific properties to schematics and symbols before the code is generated or you can use them interactively to add VHDL information to the design in the Schematic and Symbol editors.
Adding VHDL Info to a Symbol

Table 2-1 provides a list of actions you might want to perform in the DA Symbol Editor to add VHDL information to a Symbol. The VHDL information is added by attaching __da_hdl properties to the logical symbol body or to the selected or specified symbol pin(s). The illustration on page 1-26 shows where the property values are inserted into the code when the entity source is generated. Details on the meanings of the property values can be found in Table 3-2 starting on page 3-14.
2-1
Adding VHDL Info to a Symbol
The VHDL Generation Process
Table 2-1. Adding VHDL Information to a Symbol Action to Perform Symbol Editor Menu Path
Set the VHDL mode for the selected (or (Symbol Body & Pins Popup) VHDL Info > Set Pin Mode: specified) symbol pin(s). Set the VHDL data type for the selected (Symbol Body & Pins Popup) VHDL Info > Set Pin Type: (or specified) symbol pin(s). Insert the following VHDL (ADD Popup) information into the entity source code. Set VHDL Info... (Performs the same operation as the next seven individual operations.) Set the default VHDL data type that will (ADD Popup) be assigned to newly created symbol Set VHDL Info > Default Pin Type: pins on this symbol. Set the default architecture name for this (ADD Popup) symbol. Use this name in binding Set VHDL Info > Default Architecture: indications for all instances of this symbol. Insert the following VHDL library statement into the entity source code. Insert the following VHDL use statement into the entity source code. Insert the following VHDL constant statement into the entity source code. Insert the following VHDL statement into the entity source code. Insert the following generics into the entity source code. Import VHDL information from the specified Entity source file. (ADD Popup) Set VHDL Info > Libraries: (ADD Popup) Set VHDL Info > Packages: (ADD Popup) Set VHDL Info > Constants: (ADD Popup) Set VHDL Info > Statements: (ADD Popup) Set VHDL Info > Generics: (ADD Popup) Set VHDL Info > Import from Entity:
2-2
Adding VHDL Info to a Schematic
Table 2-1. Adding VHDL Information to a Symbol Action to Perform Symbol Editor Menu Path
Check the validity of the VHDL source Check > Export VHDL... code that will be generated from this design. Report all Errors, Warnings, and Notes in the Transcript Window. Generate VHDL source code from this design. File > Export VHDL...
When you add __da_hdl properties to a symbol from the Design Architect user interface, the properties are added as logical symbol properties and are nongraphic and not visible. You may see the properties by executing the Report > Object As Specified form. Select the Logical Symbol button, OK the form and a report window lists the properties. If you add generics to a symbol and want the values to be visible, you must add each __da_generic property using the (ADD popup)Properties(Logical) menu pick.

VHDL-specific information can also be added to a schematic in order to customize the generated architecture source code. Table 2-2 provides a list of actions you might want to perform in the Schematic Editor and the Menu Paths required to perform the action. The VHDL information is included in the design data by attaching __da_hdl properties to the schematic design object itself or to design objects on the schematic sheets. The illustration on page 1-28 shows where the property values are inserted into the generated source code. Details on the meanings of the property values can be found starting on pages 4-28.
2-3
Table 2-2. Adding VHDL Information to a Schematic Action to Perform Set the VHDL signal name for the selected net. Set the VHDL signal type for the selected (or specified) net(s). Set the VHDL instance name for the selected (or specified) instance. Schematic Editor Menu Path (NET Popup) Name Nets: (NET Popup) Set Net Type: (Instance Popup) Properties > Add > Add Single Property... (Specify the value of the INST property)
Set the architecture name or the (Instance Popup) configuration name for this instance. Set Architecture Name: Use this name in the binding indication for the instance. If descend on and the name is $schematic, treat the instance as non-primitive and generate an architecture from the default schematic. Set the architecture name for this schematic. Use this name for the architecture that is generated from this schematic. (ADD Popup) VHDL Info > Set Schematic Architecture:
Set the default architecture name or (ADD Popup) configuration name for this schematic. VHDL Info > Set Default Use this name in the binding indications Architecture: for all instances on this schematic. Set the default VHDL data type that will (ADD Popup) be assigned to newly created floating VHDL Info > Set Default Pin Type: symbol pins on this schematic.
2-4
Specifying VHDL Export Options
Table 2-2. Adding VHDL Information to a Schematic [continued] Action to Perform Schematic Editor Menu Path
Set the VHDL data type for the selected (Draw Popup) (or specified) floating symbol pin(s) VHDL Info > Set Pin Type: on this schematic. Set the VHDL mode for the selected (or (Draw Popup) specified) floating symbol pin(s) on VHDL Info > Set Pin Mode: this schematic. Check the validity of the VHDL source Check > Export VHDL code that will be generated from this design. Report all Errors, Warnings, and Notes in the Transcript Window. Generate VHDL source code from this design. File > Export VHDL

Specifying Export Options from the DA User Interface
VHDL Export Options are set from an applications user interface by selecting the Modify Options... button on the File > Export VHDL dialog box. You may change the options manually by selecting buttons as shown starting on page 1-6, or you may import pre-defined options from an options file by selecting the Load from File... button. Selecting the Reset to Defaults button sets the options to the default values as defined in Table 2-3 on page 2-8. You may add pre-defined options from options you have already set manually by selecting the Merge from File... button. You may then save the entire options configuration by selecting the Save to File... button. Regardless of the method you use to specify the options, the options currently selected are held in memory and are used during the export operation when you click the OK button on the Export VHDL dialog box.
2-5
Specifying Export Options from a Shell Invocation

When VHDLwrite is executed from a shell, VHDLwrite locates the options by applying the following ordered list of rules: 1. Use the value of the options file pathname supplied with the -options switch. 2. Look for a file named vhdlwrite.options in the current working directory. (This working directory may be overridden by the value of the shell environment variable MGC_WD, if set.) 3. Look for a file at the location $HOME/mgc/vhdlwrite/options. 4. Look for the file $MGC_HOME/pkgs/vhdlwrite_da/doc/default_options.
Options File Format

A VHDLwrite options file contains lines of ASCII text, each starting with a keyword followed by arguments on the same line. Blank lines and lines starting with a # are ignored; the maximum line length is twice the limitation imposed by the string length restrictions shown in Table 2-4 on page 2-20.
2-6
# vhdlwrite options file alias_netcon on alias_rippers on descend on fracture_symbol $QSLAB/component_lib/counter_4bit override_vectors as-is primitive_units entity default_scalar_type std_ulogic default_vector_type std_ulogic_vector scalar_vector_table reset scalar_vector_table bit:bit_vector scalar_vector_table std_logic:std_logic_vector scalar_vector_table std_ulogic:std_ulogic_vector lrm 93 map_user_names on mapping_file on configurations inline compilation_script on replace_files all primitive_library $MGC_GENLIB primitive_component $QSLAB/component_lib/analog primitive_component $QSLAB/component_lib/freq_det primitive_component $QSLAB/component_lib/access_chk primitive_schematic $QSLAB/component_lib/my_dff/schematic primitive_schematic $QSLAB/component_lib/my_dff/schematic2 default_libraries Library IEEE; default_libraries LIBRARY my_parts_lib; default_libraries LIBRARY card_reader_lib; default_packages USE ieee.arithematic.All; default_architecture $QSLAB/component_lib behav1 asserts on verbose on #default_configuration $QSLAB/component_lib config1 map_library $QSLAB/component_lib card_reader_lib $QSLAB/card_reader_lib single_file_netlist off automatic_compilation on vital_compliance off compilation_template $MGC_HOME/bin/vcom -93 -work $LIBPATH -source -map card_reader_lib $QSLAB/card_reader_lib #add_generic $QSLAB/component_lib/add_det MODEL string $hdl
2-7
The following table provides details on the meaning of the option file keywords and arguments. (d) indicates the default value if the keyword is not specified or commented out with the character #.
Table 2-3. Options File Keywords and Arguments Keyword add_generic Argument(s) and Meaning [conditional] component component[:interface_name] <generic_name> <generic_type> [:=<default_value>] [conditional] library <library_pathname> <generic_name> <generic_type> [:=<default_value>] Ensure that the entity description corresponding to either the component[:interface_name] or any component in the specified <library_pathname> contains a generic declaration for <generic_name>. If the property __da_generic_ <generic_name> already exists in the component interface, the <generic_type> and <default_value> specifications in this statement override. If :interface_name is omitted, the default component interface is used as the source for the entity. If the keyword conditional is present, the generic is added only if the component interface has a property with the name <generic_name>. add_quoted_generic This option has the same syntax as the add_generic option but differs in that it forces the values of the specified generic to always be doublequoted. This option has been added to support LMC Swift model libraries.
2-8
Table 2-3. Options File Keywords and Arguments [continued] Keyword alias_netcon Argument(s) and Meaning off on (d) If off, do not create aliases in the generated VHDL for unnamed netcon bits. If on, create aliases for unnamed netcon bits. Turning alias_netcon off can be useful if, for example, aliases generated by VHDLwrite do not work in another vendors design flow. off on (d) If off, do not create aliases in the generated VHDL for unnamed nets that are ripped off a bus. If on, create aliases for these unnamed nets. Turning alias_rippers off can be useful if, for example, aliases generated by VHDLwrite do not work in another vendors design flow. on off (d) If on, VHDLwrite includes assert statements in the VHDL source code that reflect assumptions which are made about the design. VHDLwrite includes assert statements only when scanning unevaluated design data (data not looked at through a design viewpoint). on off (d) If on, VHDLwrite automatically executes the compilation script after the VHDL export operation is complete. If on, the compilation_script option is forced on.
alias_rippers
asserts
automatic_compilation
2-9
Table 2-3. Options File Keywords and Arguments [continued] Keyword auto_type_conv Argument(s) and Meaning <driver_type reader_type type_conversion_func> Specifies that an object with a driver_type be matched with an object with a reader_type. The type_conversion_func must be supplied by the use and made visible through the default_packages option. Refer to page 2-21 for examples. on off (d) If on, VHDLwrite, coalesces symbol pins of the form (Q(0),Q(1),...,Q(7)) into a single VHDL port Q with a range of (0 to 7). on off (d) If descend is on, generate a compilation shell script for this design hierarchy by the name of top_level_entity_compile.sh. Place in the user specified output_to directory(if specified) or in the root (top-level) component container. Specifies the formatting description for the compile statement in the compilation script. The default value, which is suitable for the ModelSim compiler, is $MGC_HOME/bin/vcom -work '$LIBPATH' file inline (d) If file is specified, generate a package of component declaration statements and place them in a separate file. If inline, generate in-line component declaration statements.
coalesce_wide_pins
compilation_script
compilation_template
component_declarations
2-10
Table 2-3. Options File Keywords and Arguments [continued] Keyword configurations Argument(s) and Meaning file none inline (d) If descend is on and file is specified, generate configuration statements and place them in a separate file. If none, do not generate configuration statements. If inline, generate in-line configuration statements. <library_pathname architecture_name> If the __da_hdl_arch_name property on an instance and a __da_default_arch_name on a symbol is not specified, this architecture name in used for binding indications for instances of symbols in this library. This option is overridden by a default_configuration for the same library. <library_pathname configuration_name> Specifies that configuration statements for instances of symbols in library_pathname should use the configuration specified by configuration_name. This option overrides a default_architecture for the same library. <VHDL LIBRARY statement;> If the __da_hdl_libraries property is missing from the symbol or has no value, use this VHDL LIBRARY statement. If more than one of these statements is included, the values are appended to each other. The default is LIBRARY ieee;. <VHDL USE statement;> If the __da_hdl_packages property is missing or has no value, use this VHDL USE statement. If more than one of these statements is included, the values are appended to each other. The default is USE ieee.std_logic_1164.ALL;
default_architecture
default_configuration
default_libraries
default_packages
2-11
Table 2-3. Options File Keywords and Arguments [continued] Keyword default_scalar_type Argument(s) and Meaning <type> (a string) Specifies the default scalar VHDL data type for any signal or port that has not been assigned a specific type. The default is STD_LOGIC. <type> (a string) Specifies the default vector VHDL data type for any wide signal or wide port that has not been assigned a specific type. The default is std_logic_vector. <component[/interface_name]> <generic_name> Ensure that the entity description corresponding to the <component[:interface_name]> does not contain a generic declaration for <generic_name>. If the property __da_generic_<generic_name> already exists, it is effectively ignored. As a special case, if <generic_name> is literally *, VHDLwrite considers the entity to have no generics. If :interface_name is omitted, the default component interface is used as source of the entity. off on (d) If off, generate VHDL only for the specified component. If on, descend the hierarchy and generate VHDL source for every non-primitive component in the design.
default_vector_type
delete_generic
descend
2-12
Table 2-3. Options File Keywords and Arguments [continued] Keyword fracture_symbol Argument(s) and Meaning <component_name> Specifies the name of a fractured component having several component interfaces belonging to it. The fractured component must have a graphical model beneath the default component interface (this graphical model is one of the symbols that make up the fractured component). The default component interface should also have the functional model (i.e. the architecture itself) represented as a schematic, beneath it if one exists. Additionally, all the instances that need to be grouped together in the netlisted VHDL must have the REF property set to a string value, constructed as follows: a) It must have a prefix that is unique to the fractured symbol. b) It may optionally have a dash (-) followed by a suffix. The suffix, if used, should be unique for each instance in the group that will be aggregated to form the fractured symbol. c) The identical prefix must be used for REF values of all instances you want grouped together to form one instance of the fractured symbol. Use of the REF property allows the fractured component to be instantiated multiple times on the same sheet. However, the REF property must be set according to the above requirements whether you instantiate several times or only once. 93 87 (d) LRM refers to the VHDL Language Reference Manual. If 87 is specified, only basic identifiers are allowed in the generated VHDL source code. If 93 is specified, extended (quoted) identifiers are permitted.
lrm
2-13
Table 2-3. Options File Keywords and Arguments [continued] Keyword map_entity_name Argument(s) and Meaning component <component_pathnam:interface_name]> {<entity_name> | <property_name>} library <library_pathname> <(property_name)> Specifies the entity name for the component corresponding to the <component[/interface_name]> or any component in <library_pathname>. If a component is mapped both individually and as a member of a library, the individual mapping specification overrides. If <property_name> is specified, the value of the property is used as the entity name. If the property value can not be found, VHDLwrite issues a diagnostic message and uses the component name as the entity name. <Mentor_library_pathname VHDL_library_name> [VHDL_library_pathname] Associates the Mentor Graphics component library located at <Mentor_library_pathname> with the VHDL logical library <VHDL_library_name> located at <VHDL_library_pathname>. <VHDL_library_name> is used in the generated VHDL source code. Both <VHDL_library_name> and <VHDL_library_pathname> are used in the compilation script. If <VHDL_library_pathname> is omitted and $LIBPATH is used in the value of compilation_template, VHDLwrite substitutes <VHDL_library_name>. off on (d) If off is specified, user-defined names which are invalid VHDL identifiers are not mapped to valid VHDL.
map_library
map_user_names
2-14
Table 2-3. Options File Keywords and Arguments [continued] Keyword mapping_file Argument(s) and Meaning off on(d) If off, a mapping file showing the mapping of schematic identifiers to VHDL identifiers is not generated. The file is named the same as the architecture file with a .vxt extension. to downto as-is (d) If to is specified, override the bit order for vectors to ascending on a global basis. If downto, override the bit order to descending on a global basis. If as-is, leave the bit order for all vectors as-is. <component_pathname> Treat the specified component as primitive. The pathname may be a hard or soft pathname. <library_pathname> Treat all the components in the specified library as primitive. The path to the component must exactly match the given argument. For example, if $LIB/cmos/gen_lib is specified, the component $LIB/cmos/gen_lib/nand will be considered primitive, while $LIB/cmos/buffer will not. <netlist_pathname> Treat the specified single-object EDDM-based netlist as primitive.
override_vectors
primitive_component
primitive_library
primitive_netlist
2-15
Table 2-3. Options File Keywords and Arguments [continued] Keyword primitive_schematic Argument(s) and Meaning <schematic_pathname> Treat the specified schematic as primitive. For example, if $QSLAB/component_lib/add _convert/schematic is specified, VHDLwrite considers instances of add_convert to reference Black Box models and generates an entity and a null architecture (if specified). entity architecture none (d) If entity is specified, only generate an entity for primitive components. If architecture, only generate an architecture for primitive components. If none, don't generate anything. If primitive_units is not specified, generate both an entity and a black box architecture for primitive components. all none non-primitives (d) If all is specified, overwrite all existing files by the same name in the output_to directory. If none, don't overwrite any already- existing files. If nonprimitive, only overwrite existing files for nonprimitive components. Already existing compilation scripts are replaced unless replace_files none is specified. Already existing architectures are not replaced if the architecture which would be written is a black box.
primitive_units
replace_files
2-16
Table 2-3. Options File Keywords and Arguments [continued] Keyword scalar_vector_table Argument(s) and Meaning <scalar>:<vector> Add this to the contents of the scalar-vector mapping table which is referenced when a signal goes through a bus ripper. This argument may contain one or more blank-separated fields of the form scalar:vector where scalar is the scalar data type of a single element of an array type signal. reset Clear the scalar-vector mapping table. (The initial, default values of this table are shown in Table 4-3 on page 4-11). single_file_netlist on off (d) If on, VHDLwrite generates a single design file that contains the source code for all of the entities and architectures. on off (d) If on, VHDLwrite enables the use of the first letter of the pin name to determine the port mode. See Table 4-5 on page 4-13. on off (d) If on, issue progress reports as execution proceeds.
use_quicksim_port_ mode_rule
verbose
2-17
Table 2-3. Options File Keywords and Arguments [continued] Keyword vital_compliance Argument(s) and Meaning on off (d) If on, VHDLwrite generates source code that is compliant with the VITAL(VHDL Initiative Toward ASIC Libraries) Model Development Specification. If on, then (1) LRM 87, but insure no use of reserved words introduced in the 93 LRM and (2) the length of entity, architecture, and configuration names is limited to 28 characters.
The option statements are read in sequential order as they appear in the options file. VHDLwrite supports multiple occurrences of any of the option statements and interprets them according to the following rules:
For primitive_units and single-valued options (like override_vectors), the

last occurrence of the statement in the file overrides all others.
For default_packages or default_libraries, the first user-supplied value

replaces the VHDLwrite-supplied default; additional user-supplied values are concatenated.
For occurrences of add_generic and delete_generic, VHDLwrite appends

the option and its arguments to a generic modification list for the indicated component. This list is traversed when VHDLwrite builds the generic list for an entity.
For occurrences for primitive_library and primitive_schematic,

VHDLwrite accumulates all user-supplied values.
2-18
Verifying the Design

A number of automated checks must be run (without errors) on each symbol and schematic in the design before VHDLwrite will generate VHDL source files for the design objects. The following subsections describe these required checks.
Checking the Symbols

VHDLwrite depends on the checking that is done with the Check > Symbol and Save > Symbol functions in DA. A warning message is issued for symbols that haven't been checked; however, this does not prevent VHDLwrite from trying to generate valid VHDL source code. You verify that a symbol is valid by opening the DA Symbol Editor window on the symbol and running Check > Symbol and File > Save Symbol. If you added custom VHDL information to the symbol, saving the symbol is a required step in order to include the changes in the generated entity source code. Re-saving a symbol after changes are made may invalidate other models registered to the component interface(especially if symbol pins are added, renamed, or deleted. It is always a good idea to check and re-save (or re-validate) the corresponding schematic models after a symbol has been re-saved.
Checking the Schematics

VHDLwrite depends on the checks that are made with Check > Sheet on all sheets individually or Check > Schematic on the entire schematic. This does not, however, prevent VHDLwrite from trying to generate a valid architecture from the schematic. If you add custom VHDL information to the schematic, saving the schematic is a required step in order to include the changes in the generated architecture source code.
Checking for VHDL Syntax Errors

VHDLwrite performs simple design checks to increase the likelihood that the generated VHDL will be syntactically correct. The following subsections describe exactly what checking is performed when File > Export VHDL > Check Only or Check > Export VHDL is performed.
2-19
Case-insensitivity VHDLwrite checks whether any generated entity names would collide if considered case-insensitive. If a potential collision is detected, VHDLwrite issues a warning message. Identifiers Identifiers which are names of instances, components, ports, signals, types, constants, packages, libraries, generics, entities, or architectures must conform to the following rules:
Identifiers must not be a VHDL reserved word Identifiers must not be expressions; for example (x+5) Identifiers must not contain illegal characters. If they do and are userdefined, VHDLwrite will, based on the setting of the map_user_names keyword in the options file, either map the identifier to valid VHDL or issue an error message. If these identifiers are generated internally by the system, VHDLwrite always maps them to valid VHDL. Refer to the section titled Mapping Names on page 3-2 for details.
Identifiers must not exceed the string length restrictions of any Mentor
Graphics tool. The tool list includes Design Architect, ModelSim, and the CUI and AMPLE subsystems of the Falcon Framework. Restrictions are summarized in Table 2-4. Note that there are length restrictions for both identifiers and source lines: Table 2-4. String Length Restrictions Pattern Design Architect VHDLwrite ModelSim Generated VHDL Property names must have less than 512 characters. Property values have no character length restrictions. Maximum identifier length is 1023 characters. Maximum source line length is 1024 characters. Maximum identifier length is 1023 characters. No limitation on source line length.
2-20
Table 2-4. String Length Restrictions [continued] Pattern AMPLE Common User Interface Types How VHDLwrite determines the VHDL data type for pins and nets is described in detail starting on page 4-6. VHDLwrite verifies that: Generated VHDL Limited only by available virtual memory. Limited only by available virtual memory.
every pin-to-net connection has the same type using a literal string
compare
user-specified data types do not contain parentheses. the range of an instance pin (if specified) is the same for the connected net
(if specified). If both ranges are constants then VHDLwrite compares the actual widths; otherwise, the comparison is performed using a literal string compare If VHDLwrite detects a mismatch, an error message is issued. Auto Type Conversion VHDLwrite has an option that allows one type to be converted to another through the use of a specified conversion function. The conversion function must be included in a package and made visible through a USE statement. The syntax of the options is: auto_type_conv driver_type
Example 1
reader_type type_conversion_function
Assume that an output pin has a port type of qsim_state and the connected net has a type qsim_12state. A type mismatch will occur unless the following options statement is included:
2-21
auto_type_conv qsim_state qsim_12state qsim_2_qsim_12state_function In this example, the qsim_2_qsim_12state_function must be created by the user, compiled in a package and made visible through the use of a default_packages option. Notice that the parenthesis should not be specified as part of the function name because they get automatically inserted when the function gets inserted into the port map.
Example 2
An input pin with port mode qsim_state is connected to a net with type bit. The net is now the driver and the pin is the reader. The auto_type_conv option statement will look something like the following: auto_type_conv bit
Example 3
qsim_state
bit_2_qsim_state_function
Consider a pin of mode inout that has a type std_logic. The pin is connected to a net of type std_ulogic. Because this is an inout pin, two entries need to be made in the options file as follows: auto_type_conv std_logic std_ulogic auto_type_conv std_ulogic std_logic Nets VHDLwrite scans schematic sheets and issues a warning for nets that are connected to more than one instance pin with a direction of out or inout. Referenced but Undeclared Generics VHDLwrite checks for referenced but undeclared generics in all expressions written into the generated VHDL. Consider instance-specific values for a property declared as a VHDL generic: for those generic property values which are expressions, VHDLwrite checks for parameters (variables) not mentioned in the appropriate entity's generic declaration. For example, if G is declared as a generic and an instance has property G with value A+1, VHDLwrite checks whether A is also declared as a generic. A warning message is issued for referenced but std_logic_2_std_ulogic_function std_uogic_2_std_logic_function
2-22
undeclared generics. Note that for this example, VHDLwrite does generate the generic map for G (with value A+1). As another illustration, VHDLwrite checks for referenced but undeclared generics in expressions that select individual signals in a wide net(bus). For example, if a signal is referenced as A[I + 1], VHDLwrite checks that I is declared as a generic in the appropriate entity declaration. Asserts If you specify asserts on in the options file for an unevaluated design (a design not viewed through a design viewpoint), VHDLwrite inserts assert statements into the generated VHDL which reflect VHDLwrite's assumptions. There are some situations in which VHDLwrite cannot determine whether the generated VHDL is necessarily consistent with VHDLwrite assumptions, but for which VHDLwrite can generate assert statements that reflect those assumptions. Consider the parameterized wide signal referenced in the section Multiple Occurrences of Arrayed Net Names on page 4-12. If there are both constant and parameterized range values, some range specifications have the form field:field, and there is exactly one parameterized range specification of the form field:field. VHDLwrite uses that information to generate the VHDL text. For example, if the schematic contains A[7], A[3:6], A[M], and A[M:N], then VHDLwrite uses M downto N. There must be exactly one parameterized range specification of the form field:fieldif both A[M:N] and A[I:J] are present, VHDLwrite reports an error and does not generate the VHDL source code for this design unit.
Note
2-23
Generating the VHDL Source Files

VHDL source files are generated when the File > Export VHDL dialog box or the vhdlwrite shell command is executed. The output files are placed in each component container or in the source directory you specify in the dialog box.
!
Caution
When VHDLwrite finds an error in the design source, an error message is issued to the transcript and VHDLwrite continues to generate the VHDL source files as accurately as it can. This means that you should always examine the transcript after an export operation for possible error messages.
Output Source File Naming Conventions

Table 2-5 summarizes the naming conventions for VHDLwrite output files. In the table, the following is true:
top_level_entity is the name of the root-level(top) component in a design

hierarchy.
EntityName is derived from the name of the component and the component
interface. The names are mapped, if necessary, to meet the requirements of uniqueness and VHDL syntax. Refer to page 3-2 for details on mapping names to valid VHDL. If both the component name and the component interface name are the same, then EntityName is the same as the component name.
ArchitectureName can be assigned to a schematic with the

$set_default_architecture_name() function and retrieved from the schematic with the $get_default_architecture_name() function. The name is not assigned to an __da_hdl property that is attached to a design object, but rather stored internally by the system software. If a default ArchitectureName has not been specifically assigned, the name defaults to
2-24
structure. Refer to page 5-66 for details about assigning an architecture name to a schematic. Table 2-5. Naming Conventions for Output Files File Contents global signals entity Output Filename global_signals_top_level_entity.vhd ComponentName_ComponentInterfaceName_ent.vhd or ComponentName_ent.vhd (if the interface name is identical to the component name) EntityName_ArchitectureName_arch.vhd EntityName_ArchitectureName_arch.vxt (records how schematic identifiers are mapped to VHDL identifiers) top_level_entity_ArchitectureName_sfn.vhd top_level_entity_cfg.vhd comp_decls_lib_name_pkg.vhd
architecture architecture name mapping single-file netlist configuration component declarations for components in library lib_name compilation shell script
top_level_entity_compile.sh
If all the output files are placed in a separate VHDL source directory, the possibility of name collisions (for example, assigning the same filename to two different entity source files) is eliminated by prefixing each output filename in the above table with the string X_, where X is defined as the network-wide path to the component container. Occurrences of slash (/) are replaced by underline (_) and leading underline characters are removed. For example, VHDLwrite
2-25
Compiling the VHDL Source
places the entity declaration for a Mentor Graphics component located at /user/joe/lib/ram into a file named user_joe_lib_ram_ent.vhd. VHDLwrite issues a message that indicates the name of the toplevel entity so that you will know what name to specify in the simulator invocation. VHDLwrite also issues a message that indicates the name of the EDDM component structure found at the top of the design.
Note
If the mapping_file option is enabled, VHDLwrite generates a name-mapping file which describes the name mappings used in architectures built from schematics.
Overwriting Output Source Files

VHDLwrite does not alter the last-modification time of output files when their contents (exclusive of header comments) have not changed. In other words, if VHDLwrite would generate a file and (1) the file already exists and (2) the file contents are the same as what VHDLwrite would generate(exclusive of header comments), then VHDLwrite ensures that the last-modification time of that file does not change due to VHDLwrite execution.

VHDLwrite optionally generates a Bourne shell script which compiles all the generated VHDL source in the following order: 1. a package declaring global signals 2. all entities 3. all component declaration packages, if any. 4. all architectures 5. a configuration file (if present)
2-26
You may specify the compiler and switches with the compilation_template option. You may also automatically execute the script at the end of an Export operation by specifying on for the automatic_compilation option. If the keywords shown in Table 2-6 are included in the template, the indicated text is substituted in the compiler invocation line. Table 2-6. Keyword Substitution in Compilation Template Keyword $SOURCE $LIBNAME Substituted Text The name of a generated VHDL source file. The name of the VHDL design library associated with the Mentor Graphics component library(a Unix directory) containing the component from which the entity and/or architecture was generated. (The association is made with the map_library option. See page 1-20.) The pathname of the VHDL design library associated with the Mentor Graphics component library(a Unix directory) containing the component from which the entity and/or architecture was generated. If no value is known, VHDLwrite substitutes the value for $LIBNAME. Value of the lrm option as specified in the options file.
$LIBPATH
$LRM
If no substitution for $SOURCE is performed, the name of the generated VHDL source file is appended to the shell script line. For $SOURCE and $LIBPATH, any softpath is converted to a hardpath before the value is written. If the shell script contains lines compiling a configuration file or an single-file netlist (Autologic I output), the values of $LIBNAME and $LIBPATH are those associated with the top-level entity. As an example, assume that VHDLwrite generates an entity source file named card_reader_ent.vhd. Also assume that the map_library option was used to associate the VHDL design library named card_reader_lib located at /user/joe/card_reader_lib with the card_reader component. The following compilation_template option statements produce the corresponding lines in the compilation shell script:
2-27
compilation_template $MGC_HOME/bin/vcom -work /tmp/work

shell script line: $MGC_HOME/bin/vcom -work /tmp/work card_reader_ent.vhd
compilation_template $MGC_HOME/bin/vcom $SOURCE -work

$LIBNAME shell script line: $MGC_HOME/bin/vcom card_reader_ent.vhd -work card_reader_lib
compilation_template $MGC_HOME/bin/hdl $SOURCE $LIBPATH

shell script line: $MGC_HOME/bin/hdl card_reader_ent.vhd /user/joe/card_reader_lib The name of the above shell script is card_reader_entity_compile.sh. If the automatic_compilation option is specified as on and no errors are reported by VHDLwrite, then VHDLwrite executes the shell script after netlisting is complete. If the automatic_compilation option is specified as on and errors are reported by VHDLwrite, then a warning is issued stating that the automatic compilation was suppressed. If you are running QuickSim Pro, and the environment variable MTI_HOME is set, ModelSim commands will be invoked from the directory $MTI_HOME/modeltech/bin.
Note
The following provides a general outline of how to manually compile the VHDL source for ModelSim using the generated compilation script. After the VHDLwrite netlisting operation is complete, do the following: 1. Identify a location for creating a new working library. For example /tmp/worklib. The directory worklib must not currently exist at location /tmp. 2. Execute the following command:
$vlib /tmp/worklib
This creates a new working library that will receive the compiled VHDL. 3. Next, execute the following command:
2-28
$QSLAB/card_reader_source/card_reader_entity_compile.sh vcom -work /tmp/worklib
This line executes the card_reader_entity_compile.sh shell script. All the card_reader source files generated from VHDLwrite are compiled oneat-a- time and placed in the /tmp/worklib directory.
2-29
2-30
Chapter 3 Symbol-to-VHDL Entity Mapping
Generating an Entity
VHDLwrite uses the information located in the specified component interface of the specified component to generate the source text for the entity. If the component has a schematic with no corresponding symbol (typically a top-level schematic in the design hierarchy), VHDLwrite generates an entity declaration with a port_clause inferred from external and global nets in the schematic and no generic_clause. All ports are generated with a port mode using the rules as described in the section Determining Port Mode (direction) on page 4-12, but applied to the external nets and a VHDL type which is obtained from the net as described in the section Determining the VHDL Data Type on page 4-6. To ensure that there is a correct port mode declaration for an entity being generated from a schematic (with no corresponding symbol), you should attach a PINTYPE property to all external nets with a value of IN, OUT, or INOUT. If VHDLwrite encounters a bundle pin while generating a VHDL entity from a component interface, a warning message will be issued and VHDLwrite will create VHDL ports from the individual leaf member pins.
3-1
Mapping Names
Symbol-to-VHDL Entity Mapping
Mapping Names
The following name mapping discussion applies to mapping schematics to architectures as well as mapping symbols to entities.
Note
Basic and Extended VHDL Identifiers

Effective with the 1993 revision of the Language Reference Manual (LRM), the VHDL language supports both basic and extended identifiers. VHDL basic identifiers are restricted to letters, digits, and the underline character (_). VHDL basic identifiers must begin with a letter, cannot have two consecutive underline characters, and must not end with an underline character. Mentor Graphics identifiers are not so restricted. If you specify basic identifiers in the VHDLwrite options file, then VHDLwrite maps each Mentor Graphics identifier into a valid VHDL identifier. Internal names (system assigned names like N$3) are always mapped if necessary. You can control whether user-defined names must be legal VHDL identifiers without mapping (see the map_user_names keyword in Table 2-3 on page 2-8). VHDL extended identifiers are made up of any sequence of graphic characters, enclosed in backslashes (\); therefore, name mapping issues do not arise due to a Mentor Graphics identifier which is not a valid VHDL extended identifier. VHDLwrite tracks both original and mapped names and ensures that name mapping does not result in unintended design modifications. For example, consider a design with two distinct nets - one named N_0361 by the user and one internally-named N$1 by the Mentor Graphics software. If VHDLwrite blindly renamed N$1 to be N_0361, the result would be an unintended shorting together of the two originally-distinct nets.
Rules for Name Mapping

VHDLwrite maps identifier names according to the following rules:
3-2
Mapping Names
A Mentor Graphics name that is a valid VHDL identifier maps to itself. If

this identity mapping results in a too-long identifier, VHDLwrite truncates the name, appends a sequence number, and issues a diagnostic message.
Illegal characters map to an underline character (_) followed by the

decimal equivalent of the ASCII character code output as 3 decimal digits with leading zero-fill. For example, VHDLwrite maps the character % to _037.
Identifiers which do not begin with a letter are prefixed with MGC. If the identifier string has two consecutive underline characters,
VHDLwrite separates them with the letter x. If the string ends with an underline character, VHDLwrite appends the letter x to the end.
A mapped name which is too long is truncated, a sequence number is

appended, and a diagnostic message is issued. For example, if the maximum length is 20 characters and the original name is A%%latching_enable, the mapped name is constructed as A_037_037latching_enable which is more than 20 characters long. The application of this rule results in the string A_037_037latchin0001.
If a mapped name is the same as the map of a different original name, a

trailing sequence number is used to prevent the name collision and a diagnostic message is issued. If the mapped name is too long, it is truncated before the sequence number is appended. In this last case, if the qspro_fail_on_collisions option is set to on, VHDLwrite issues an error message.
Note
Attribute original_name When VHDLwrite performs name mapping (when the user-defined original name differs from the mapped name) it tries to associate a VHDL attribute called original_name with each mapped descriptive entity. For example,
3-3
Mapping Names
attribute original_name : string; signal A_0371 : bit_vector(3 downto 0); attribute original_name of A_0371 : signal is "A%1";
The original_name attributes are suppressed if a mapping file is generated. (Whether or not to generate a mapping file is specified in the options file.)
Mapping Entity Names

VHDLwrite may modify the name of an entity to assure design-wide uniqueness. The map_entity_name option may also be used to specify the entity name for instances of either a specific component interface or any component in a specific library. The name may be specified either as a string literal, such as the following:
map_entity_name component $MGC_GENLIB/74259 counter_4bit
or the entity name may also be specified as an instance-specific property, such as the following:
map_entity_name library $MGC_LSLIB (COMP)
The map_entity_name option does not determine which component interface is referenced by an instance; the option controls only the name of the entity built from that component interface. Using this option may cause VHDLwrite to construct multiple entities (with different names) from the same component interface. VHDLwrite assumes that the map_entity_name option is applied only to primitive instances (for which noor only a black boxarchitecture is generated). VHDLwrite does not construct multiple architectures (with different names) for the same schematic or EDDM netlist, corresponding to each possibility-name-mapped entity built from a component interface. You can add a __da_hdl_entity_name property to the symbol/component interface that will specify the name of the entity that will be generated. The value of the property must be a string that specifies the name to be used.
3-4
Libraries
Libraries
VHDLwrite supports designs that reference multiple libraries through the map_library option. This option creates an association between a Mentor Graphics component library (the Unix directory where mgc_component objects reside) and a VHDL design library. For example, consider the following options file statement:
map_library $QSLAB/component_lib my_parts_lib $QSLAB/my_parts_lib
In this case, VHDLwrite will use the VHDL design library my_parts_lib. If no map_library option is known for a Mentor Graphics component library, VHDLwrite uses work as the VHDL library name. The library names supplied in the map_library option affect the generated VHDL in the following ways:
The VHDL library name appears in the configuration for any instances of
components from that Mentor component library.
The set of VHDL libraries referenced by the instance configurations in the

given architecture body are made visible with LIBRARY statements at the top of the architecture.
If the single_file_netlist option was turned on, but the resulting VHDL
needs to be compiled into different libraries, then the single_file_netlist option is disabled and a diagnostic message is issued.
If the compilation_template includes the $LIBNAME variable, then the

appropriate library name is specified to the compiler (as the location for the compiled VHDL) when compiling an entity or architecture contained in that Mentor Graphics component library.
If the component_declarations option is specified as in-file, then all

generated component declarations for components that are in a mapped library are placed in a separate VHDL source package (one package per mapped library).
3-5
Handling Generics
If the property __da_hdl_lib_name exists on the symbol body/component interface, then the value of this property is used in lieu of any map_library option that might have applied to this component. The user is required to compile the VHDL source code to create the VHDL LIbrary.
Note
Handling Generics
A generic named X is represented in design data in two ways: 1. The presence of either of the properties __da_generic_X or __da_generic_quoted_X on a logical symbol body indicates that the VHDL entity should include X as a generic; the property value specifies the generic's VHDL data type and (optionally) the generic's default value. If the property value does not include a default value, VHDLwrite uses the value of the logical symbol body property X as the default. If a default value cannot be found, no value is included in the generated VHDL. The property name __da_generic_X is used instead of simply X to allow generics with the name MODEL, COMP, etc. Otherwise, user-specified generic names may collide with long-standing Mentor Graphics property names. The property __da_generic_quoted_X tells VHDLwrite to add quotes around the value during netlisting; otherwise, its purpose is the same as __da_generic_X. 2. The occurrence-specific generic value is obtained from the property X on particular instance bodies on the schematic sheet. Note that the VHDLwrite options file may be used to modify the list of generics associated with an entity, without changing logical symbol body properties in the design.
3-6
Handling Generics
Generic Example 1
A symbol named ANALOG has the following properties: Property Owner Logical Symbol Body Symbol Body Property Name __da_generic_OSC_RISE Value time := 10 ns Type string
OSC_RISE
20 ns
string
In this example, the __da_generic_OSC_RISE property defines a type time and a default value 10 ns. The generic declaration in the entity source will look like the following:
entity ANALOG is generic(osc_rise : time := 10 ns)
The value of the symbol body property OSC_RISE is not used as the default value because the default value is included as part of the value of __da_generic_OSC_RISE. When this entity is included as an instance in another design unit architecture, the value of the Symbol Body Property OSC_RISE will be used as the value of the generic. The generic map will look like the following:
generic map (osc_rise => 20 ns)
Generic Example 2
A symbol named ANALOG has the following properties: Property Owner Logical Symbol Body Property Name __da_generic_OSC_RISE Value time Type string
3-7
Handling Generics
Property Owner Symbol Body
Property Name OSC_RISE
Value 20 ns
Type string
In this example, the __da_generic_OSC_RISE property does not have a default value, so the value of OSC_RISE on the symbol body is used as the default. The generic declaration in the entity source will look like the following:
entity ANALOG is generic(osc_rise : time := 20 ns)
Generic Example 3
A symbol named ANALOG has the following properties: Property Owner Logical Symbol Body Symbol Body Property Name __da_generic_OSC_RISE Value time Type string
OSC_RISE
delay1
string
In this example, the __da_generic_OSC_RISE property does not have a default value, so the value of OSC_RISE on the symbol body is used as the default. The generic declaration in the entity source will look like the following:
entity ANALOG is generic(osc_rise : time := delay1)
If ANALOG is the root entity, VHDLwrite assumes that delay1 is an undeclared generic and issues a warning message. If ANALOG is instantiated in the architecture of another design unit like CARD_READER, then VHDLwrite assumes that delay1 is the name of another generic that is declared in the entity for CARD_READER. This is an example of
3-8
Handling Generics
passing by name. If generic delay1 is not declared in the CARD_READER entity, then VHDLwrite issues an error message. The generic map for an ANALOG instance will look like the following:
generic map(osc_rise => delay1)
Note
The VHDLwrite option add_generic could be used in this case to add the delay1 generic declaration to the generated entity for CARD_READER. This would eliminate the need to edit the CARD_READER symbol to add the property __da_generic_delay1. (See page 1-14 for details.)
Generic Example 4
A symbol named ANALOG has the following properties: Property Owner Logical Symbol Body Symbol Body Property Name __da_generic_edge Value string Type string
edge
leading_edge
string
In this example, the __da_generic_edge property is of type string with no default value specified. The value of the edge property attached to the Symbol Body is used as the default. The entity source will look like the following:
entity ANALOG is generic(edge : string := leading_edge)
Notice that because the generic edge is of type string, the value of the symbol body property edge must include the quotes. Otherwise, the quotes wont be included in the generated VHDL and a syntax error will result when this entity is compiled.
3-9
Handling Generics
Note
The VHDLwrite option add_generic could be used in this case to add the edge generic declaration to the generated entity for ANALOG. This would eliminate the need to edit the ANALOG symbol to add the property __da_generic_edge. (See page 1-14 for details.) Additionally, if you use the add_quoted_generic option, you would not need to edit the symbol to add quotes to the value of the edge property.
Generic Example 5
A symbol named ANALOG has the following properties: Property Owner Logical Symbol Body Symbol Body Property Name __da_generic_quoted_edge Value string := leading_edge trailing_edge Type string
edge
string
In this example, the __da_generic_quoted_edge property defines a type string and a default value leading_edge. The value of the edge property attached to the Symbol Body is not used as the default value because the default value is included as part of the value of __da_generic_quoted_edge. The entity source will look like the following:
entity ANALOG is generic(edge : string := leading_edge)
Notice that the value of the __da_generic_quoted_edge property does not require quotesthey are added by VHDLwrite. This is in contrast to the previous example where you saw that the symbol body property edge had to include quotes for them to be included in the generated VHDL.
3-10
Symbol Properties Mapped to VHDL

Table 3-1 outlines how symbol properties are mapped to VHDL. Table 3-1. Symbol Properties Mapped to VHDL Property Owner Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol Body (Graphic al) Symbol Body (Logical) Property Name PIN Usage Name of pin/port and optional range specification Example Values DIN X(0:15) B(3) BIT_VECTOR QSIM_STATE INTEGER nibble one of {IN, OUT, INOUT, BUFFER}
__da_hdl_port_type Data type of pin
__da_hdl_port _subtype __da_hdl_port _mode PINTYPE
Constrained data type Signal direction of pin
Signal direction of pin if one of {IN, ENA, __da_hdl_port_mode OUT, IXO, IO} property is not present Model selection $hdl
MODEL
__da_hdl_entity _name
Specifies the name to use flip_flop for the entity declaration that is generated from this symbol. See page 1-28 and page 3-4
3-11
Table 3-1. Symbol Properties Mapped to VHDL [continued] Property Owner Symbol Body (Logical) Property Name __da_hdl_lib_name Usage Specifies the logical library name that should contain the compiled form of the entity generated from this symbol. See page 1-26 and page 3-6 Library statements. See page 1-26. Package statements. See page 1-26. Generic NAME; property value is generic's default, unless overridden by __da_generic_NAME property. See page 1-26. Generic declarations; the property name corresponds to the generic NAME; the value specifies the generic's type and (optionally separated by :=) a default value. See page 1-26. time := 2 ns Example Values my_hdl_lib
Symbol Body (Logical) Symbol Body (Logical) Symbol Body (Logical)
__da_hdl_libraries
Library /usr/jackw/my_li b; Use my_lib.all;
__da_hdl_packages
NAME
Symbol Body (Logical)
__da_generic _NAME
3-12
Generating a Symbol from a VHDL Entity
Table 3-1. Symbol Properties Mapped to VHDL [continued] Property Owner Symbol Body (Logical) Property Name __da_generic _quoted_NAME Usage Same as __da_generic _NAME except that VHDLwrite adds quotes around the value during netlisting. Constants not contained in a package. See page 1-26. Example Values time := 2 ns
__da_hdl_constants
Constant pi : real := 3.14; Assert X > 0;
Symbol __da_hdl_statements Contents of Body entity_statement_part. (Logical) See page 1-26. Symbol Body (Logical) __da_hdl_arch _name Default architecture or configuration name for instances referencing this symbol. See page 1-26. Default type for newly created ports in this symbol. See page 1-26.
behav configuration confg
__da_hdl_default _port_type
std_logic

VHDLwrite provides the capability to generate a symbol and a component structure from a compiled entity. You might want to do this if, for example you have an existing VHDL entity and you want to quickly create an equivalent Mentor Graphics symbol and instantiate it on a sheet. The symbol generation function takes VHDL information from the specified Entity object and the Generate Symbol dialog box to make the new symbol. The process for generating a symbol is illustrated on page 1-40.
3-13
Table 3-2 below shows what properties are added to the new symbol body. Table 3-2. Symbol Body Properties Added to a Generated Symbol Property Name __da_hdl_libraries __da_hdl_packages __da_generic_NAME NAME __da_hdl_lib_name __da_hdl_entity_name __da_hdl_arch_name __da_suppress_units Stability Protected Protected Fixed Variable Protected Protected Variable Fixed Visible Hidden Visible Visibility Example Value LIBRARY my_work_lib; USE my_work_lib.ALL; time delay my_work_lib nan2 behav configuration confg entity
In the table above, the stability of the __da_hdl_libraries property is set to Protected so that Library Management System users can override these values with LMS catalog entries. Table 3-3 shows what properties are added to the pins of a generated symbol. Table 3-3. Properties Added to Generated Symbol Pins Property Name PIN Stability Fixed Visibility Visible Example Value DIN X(0:15) B(3) bit_vector std_logic integer nibble
__da_hdl_port_type
Fixed
Hidden
__da_hdl_port _subtype
Fixed
Hidden
3-14
Importing VHDL Info to Symbols
Table 3-3. Properties Added to Generated Symbol Pins Property Name __da_hdl_port _mode __da_hdl_port_init Stability Fixed Fixed Visibility Hidden Hidden Example Value one of {IN, OUT, INOUT, BUFFER} 1

If you already have an existing symbol that closely matches an already compiled entity, you can updated the information on the symbol to match the compiled entity. The VHDL information from the entity is annotated onto the symbol pins and symbol body so that when VHDLwrite is used later to generate VHDL from the symbol, the generated code will match the code in the original entity. The process for updating the symbol is illustrated on page 1-44. Before making any design changes to an existing symbol, VHDLwrite first verifies that the pins on the symbol match the ports in the entity. If they do not match, an error message is issued and no symbol edits are made. The properties added to the symbol are listed in the preceding tables. This import function checks to see if a PARTNER hdl model has been registered with the component interface for this symbol and that it is the only model with the label hdl. If it is not present, then a partner model is registered and labeled hdl. If any other model has the label hdl, then a non-fatal error message is issued.
3-15
3-16
Chapter 4 Schematic-to-VHDL Architecture Mapping
This section describes the mapping of schematic constructs to VHDL source text.
Instances on a Schematic Sheet

VHDLwrite generates an entity and an architecture for each instance on a schematic sheet, unless told to do otherwise in the command invocation or from the options file. VHDLwrite descends through all schematic models in the design hierarchy (unless told not to do so). A primitive instance is an instance with no schematic model, an instance that is declared primitive in the design viewpoint, or an instance whose schematic is declared primitive, or whose symbol is in a library that is declared primitive in the VHDLwrite options file. When a primitive instance is found, it is treated as a black box and an empty architecture body called black box is generated (unless told not to do so). VHDLwrite cannot descend through a primitive instance. You can use the primitive_units keyword in the options file to control the action when VHDLwrite encounters a primitive instance. The argument entity tells VHDLwrite to only generate an entity; architecture tells VHDLwrite to only generate an architecture, entity and architecture generates both, and none generates none. A VHDL entity can always be generated from the component interface of either a primitive or non-primitive instance. However, if you specify in the Export VHDL dialog box that the VHDL source file is to be placed in the component
4-1
Instances on a Schematic Sheet
Schematic-to-VHDL Architecture Mapping
container of a primitive library component that is write-protected, an error results and the VHDL source text won't be generated.
Descent through Unevaluated Design Data

VHDLwrite uses the following rules when generating architecture source text for instances in unevaluated design data:
VHDLwrite verifies which instances are valid hierarchical electronic data

model components with component interfaces. VHDLwrite ignores all instances that are not. (For example, logical cabling components are ignored.)
You can specify in a VHDLwrite options file that a particular component or

all components in a particular library are to be considered primitive. If VHDLwrite examines an instance of a symbol from such a library, it treats the instance as a black box model.
Each instance is examined to determine the value of its MODEL property.

If the instance does not have a MODEL property (for example, the property may have be deleted from the instance), then the specified component interface or the default component interface of which this is an instance is examined for the MODEL property. If the MODEL property is an expression or cannot be found in either location, then a warning diagnostic message is issued and the referenced component is treated as a primitive.
If the MODEL property is found, then all of the mgc_schematic models

registered with that component interface are examined to see if one of them has a label which matches the value of the MODEL property. In the case of multiple matches (for example, more than one schematic may have the label $schematic), the schematic model last written to disk is chosen and a diagnostic Note message is issued. If there are no matches, the component is treated as a primitive and a warning diagnostic message is issued.
4-2
Schematic-to-VHDL Architecture Mapping Overriding Architecture or Config Name
Descent through Evaluated Design Data (Viewpoint Specified)

For each instance in evaluated data (data under a viewpoint), VHDLwrite descends based on the Primitives List declared in the viewpoint. If an instance is not primitive according to the viewpoint, but is declared primitive in the VHDLwrite options file, the instance is treated as primitive by VHDLwrite. VHDLwrite issues a diagnostic message whenever such an override occurs. Due to the flexibility of schematic data (for example, expanding frames), VHDLwrite may generate multiple architectures for a single schematic.
Overriding Architecture or Config Name

If a default architecture name is specified for an instance, VHDLwrite treats the instance as primitive and determines the overriding architecture or configuration name by applying the following rules: (Refer to Figure 4-1) 1. If a __da_hdl_arch_name property is attached to the instance and it has a non-empty value, then that value is used for that instance. This property can be added by selecting the instance in the Schematic Editor and executing the menu (Instance Popup) Architecture Name. In Figure 4-1, the references to the architecture for the LATCH instance in the lower-left corner will be made to behav_hi_speed. For example, the binding in a configuration statement points to ...work.LATCH(behav_hi_speed).
4-3
Overriding Architecture or Config Name Schematic-to-VHDL Architecture Mapping
OU
T0
N0
_ MY
IN 1
DE
G SI
OU
T1
OU
T2
__da_hdl_default_arch_name
IN
custom
Schematic Design Object

LA TC H TC H TC H
LA
4
Options File
# vhdlwrite options file descend on makefile on compilation_script on verbose on asserts on default_architecture $LIB behav default_configuration $LIB2 config1
Q T LA CH
LA
6
$schematic
__da_hdl_arch_name
Instance Body
1 3
R
LA
H TC
S
__da_hdl_arch_name
Q
behav_hi_speed
Symbol Body
Q
2
__da_hdl_arch_name
Q
behavior
Figure 4-1. Overriding the Architecture or Configuration Name
4-4
Schematic-to-VHDL Architecture Mapping Overriding Architecture or Config Name
2. If a valid name is not found in step 1, VHDLwrite searches the symbol body for the non-empty value of a __da_hdl_arch_name property. In Figure 4-1, the architecture name referenced from the top two instances of LATCH is behavior. 3. If a valid architecture name is not found in the first two search steps, VHDLwrite looks to see if the referenced symbol is in a library specified in a default_configuration statement in the options file. If so, the specified configuration name is referenced. 4. If a valid name is not found, VHDLwrite looks to see if the referenced symbol is in a library specified in a default_architecture statement in the options file. If so, the specified architecture name is referenced. 5. If a valid name is still not found, VHDLwrite looks to see if the schematic design object itself has a default architecture name assigned. In the figure to the left, if a valid architecture name was not found up to this point, the name custom would be used. After applying the above rules, if a non-empty value is found and it matches the pattern configuration <name> (or if an applicable default_configuration library option is found), VHDLwrite binds the instance to the specified configuration. Otherwise, the non-empty value is assumed to be an architecture name, and 1. if the name is $schematic, the instance is forced to use a schematic-based model (if possible; if one cannot be found, a black box architecture is used) 2. if the name is anything other than $schematic, that name is used as the architecture name for the instance and VHDLwrite considers the instance to be primitive (i.e., VHDLwrite ignores the existence of any schematic model). If all instances of a given component are declared to have an overriding architecture name, then those instances are assumed to be primitive and therefore subject to the primitive_units option.
Note
4-5
Parameterization
Parameterization
VHDLwrite outputs instance-specific properties specified in the entity's generic declaration. Since the VHDL language and Mentor Graphics' system have different rules for parameter value resolution, VHDLwrite generates generic map statements for every instance-specific generic with a resolvable value on the schematic.
Determining the VHDL Data Type

Port Data Type
VHDLwrite determines the VHDL data type of input and output ports by applying the following rules:
If the port name does not have the form A[] or A(), the data type is
assumed to be scalar. If the port has the __da_hdl_port_type property attached, VHDLwrite takes the property value to be the port's data type; the property value should be either a VHDL scalar type or subtype (for example integer), or a scalar type with a range constraint (a subtype indication). An example is integer range 0 to 127".
!
Caution
VHDLwrite does not verify that the __da_hdl_port_type property value is appropriate (or even syntactically correct); if the value is incorrect, VHDLwrite will silently generate invalid VHDL.
If the port does not have the __da_hdl_port_type property, VHDLwrite

uses the value of the default_scalar_type keyword that is specified in the options file. See Table 2-3 on page 2-8 for details.
If the port name does have the form A[] or A(), the data type is
assumed to be an unconstrained array and the array bounds come from the port name. If the port has the __da_hdl_port_type property, VHDLwrite takes its value to be the name of an unconstrained array type. For example, a port
4-6
with name A[3:0] and __da_hdl_port_type property value bit_vector will generate the VHDL text
port(A : in bit_vector(3 downto 0);
!
Caution
Again, VHDLwrite does not verify that the __da_hdl_port_type or __da_hdl_port_subtype property values are appropriate (or even syntactically correct).
If the port does not have the __da_hdl_port_type property, but does have a __da_hdl_port_subtype property, then the value is assumed to be a constrained subtype that has been defined elsewhere in a package. In this case, the array bounds are not taken from the pin name. For example, A[3:0] __da_hdl_port_subtype = nibble
where nibble is defined in a package as subtype nibble is bit_vector(3 downto 0) results in a port declaration of port(A: in nibble). Table 4-1 gives further details about mapping wide pins on schematics to VHDL text. In the table, A represents a signal name. X, I, J, M, and N represent parenthesis-balanced text strings not containing comma (,), colon (:), or semicolon (;). Note that text strings need not be distinct. In other words, I and J could represent the same string. Table 4-1. Mapping Wide Pins to VHDL Text Pattern (X) A[(X)] Generated VHDL No VHDL is generated and an error diagnostic message is issued because an identifier cannot be an expression. This signal is assumed to be a one-dimensional array. The range specification is deduced from other references to signal A.
4-7
Table 4-1. Mapping Wide Pins to VHDL Text [continued] Pattern A[I] Generated VHDL Signal A : Xtype(range-specification); where Xtype is the value of the __da_hdl_port_type property (if present); otherwise, Xtype is the value of the VHDLwrite default_vector_type keyword argument found in the options file. In either case, Xtype is assumed to have the type unconstrained array. The range-specification is deduced from other references to signal A. VHDLwrite assumes this is a signal with a disjoint range and an error diagnostic message is issued. This pattern results in an error even if there is a reference elsewhere in the design to A[M:N]. The ellipses (...) mean that the sequence comma, parenthesis-balanced text string may be arbitrarily repeated. Signal A : Xtype(M downto N); where Xtype is the value of the __da_hdl_port_type property (if present); otherwise, Xtype is the value of the VHDLwrite default_vector_type option. In either case, Xtype is assumed to have the type unconstrained array. If the __da_hdl_port_type property is present, signal A is assumed to be an unconstrained multidimensional array with the type equal to the value of that property: signal A : Xtype(M downto N, I downto J); where Xtype is the value of the __da_hdl_port_type property. If the __da_hdl_port_type property is not present, signal A is assumed to be a multidimensional array of the type specified by the VHDLwrite default_scalar_type option: type Xtype is array(integer range <>, integer range <>) of <type_name>; signal A : Xtype(M downto N, I downto J); In this case, Xtype is a unique name generated by VHDLwrite.
A[I,J ...] or A(I,J ...)
A[M:N] or A(M:N)
A[M:N;I:J] or A(M:N;I:J)
4-8
Note
It is invalid to declare an arrayed signal by choosing a non-arrayed pin name (for example A) and putting both the array bounds and the array type on the __da_hdl_port_type property (for example, bit_vector(3 downto 0)). VHDLwrite reports an error in this situation, which specifies that user-specified data types do not contain parentheses.
Net Data Type

Because nets on a schematic do not need to be explicitly named by the user, VHDLwrite may need to determine whether a net is a wire or bus in order to determine the net's VHDL data type. VHDLwrite decides whether a net is a wire or a bus by applying the following rules:
If the net has a user-supplied name (in the form of an added NET property)
of the form A[] or A(), the net is assumed to be a bus or a bus element and carries a signal of type array; if the user-supplied name has another form, the net is assumed to be a wire and carries a signal of the type in the scalar category.
If the net does not have a user-supplied name, VHDLwrite examines the
pins to which the net is connected and any equivalent nets. If at least one connected pin or equivalent net has a name with an array specification, the net is assumed to be a bus or a bus element and carries a signal of type array. If all the connected pins and equivalent nets do not have an array specification, the net is assumed to be a wire and carries a signal of the type in the scalar category. If VHDLwrite encounters a net bundle while generating a netlist from a source schematic, VHDLwrite will issue an error diagnostic and the design will not be netlisted. If VHDLwrite encounters a net bundle while generating a netlist from a design viewpoint, the net bundle will be ignored, a warning message will be issued and the leaf member nets of the net bundle will result in VHDL signal or alias declarations.
Note
4-9
VHDLwrite determines the VHDL data type of nets by applying the following rules:
If the net has the __da_hdl_signal_type property, VHDLwrite takes its

value to be the net's data type. If the net is a wire, the property value should be either a VHDL base type or subtype in the scalar category. For example, integer is a scalar base type and integer range 0 to 127" is a subtype. If the net is a bus, the data type is assumed to be an unconstrained array and the property value is taken as the name of an unconstrained array type. The case of a multidimensional signal is handled in the same way as it is outlined in Table 4-1.
If the net does not have the __da_hdl_signal_type property, VHDLwrite

infers the VHDL data type of the net from the VHDL data type of the pins and bus rippers connected to that net. VHDLwrite follows a signal through a bus ripper as defined in table 4-2. In the table, Ripper Rule Pattern X, M, and N are alphanumeric strings: Table 4-2. Inferred Signal Width & Data Type for Bus-Ripped Signals Ripped-Rule Pattern X or (X) Generated VHDL A scalar signal extracted from a vector signal; the data type of the ripped signal is obtained from Table 4-3 (the scalar/vector table). VHDLwrite issues an error message if the data type is not in the scalar/vector table. A vector signal extracted from a vector signal; the data type of the ripped signal is the same as the data type of the source bus. This is presumed to be a disjoint range and an error message is issued. An error message is issued.
M:N M,N Anything Else
4-10
Schematic-to-VHDL Architecture Mapping Mapping the Range Direction for Buses
If a bus ripper extracts a scalar signal from a vector signal, VHDLwrite uses a special scalar/vector table to determine the appropriate data types. The initial default table values are defined as follows: Table 4-3. Initial Default Scalar/Vector Data Type Scalar bit std_logic std_ulogic Vector bit_vector std_logic_vector std_ulogic_vector
This table can be modified by using the scalar_vector_table keyword in the VHDLwrite options file as described in Table 2-3 on page 2-8.
Mapping the Range Direction for Buses

The choice of to or downto in range specifications is made based on the following ordered list of rules: 1. If a global override was specified by the user in the VHDLwrite invocation form, then VHDLwrite uses it. If both range limits are integer constants, VHDLwrite orders the limits so as to avoid a null range. 2. If both range limits are integer constants, VHDLwrite chooses between to or downto so as to avoid a null range. If the range limits are the same (for example A[0:0]), VHDLwrite uses downto. 3. VHDLwrite uses downto if the above conditions are not met.
Multidimensional Signals
VHDLwrite generates multidimensional signals only when net names are expressed in the form of a multidimensional array (e.g., A[0; 1; 2; 3]); reference can be made only to the entire array (A) or a single element (A[0; 1; 1; 1]).
4-11
Multiple Occurrences of Arrayed Net Names
Schematic-to-VHDL Architecture
Multiple Occurrences of Arrayed Net Names

A bus on a Mentor Graphics schematic has a net name that consists of a base name concatenated with per-dimension range information (for example A[0:13]). If there are multiple occurrences of an arrayed net name (buses within a bus) with different per-dimension range information, VHDLwrite decides on the VHDL representation for each dimension based on the following rules:
If all occurrences have constant range information (A[7], A[4:6]),

VHDLwrite determines the schematic-wide minimum and maximum range values and uses those in the VHDL signal declaration.
If there are both constant and parameterized range values, but all
parameterized range specifications have the form field (and not field:field), VHDLwrite ignores the parameterized values and applies the previous rule. (In other words, VHDLwrite assumes that the parameterized range values are within the interval defined by the constant range values.)
If there are both constant and parameterized range values, some range
specifications have the form field:field, and there is exactly one parameterized range specification of the form field:field, VHDLwrite uses that information to generate the VHDL text. For example, if the schematic contains A[7], A[3:6], A[M], and A[M:N], then VHDLwrite uses M downto N. Note that there must be exactly one parameterized range specification of the form field:field - if both A[M:N] and A[I:J] are present, VHDLwrite reports an error and does not generate the VHDL source text.
Determining Port Mode (direction)

VHDLwrite determines pin direction based on the following ordered list of rules: 1. If the pin has a __da_hdl_port_mode property attached, the property value is used.
4-12
Determining Port Mode (direction)
2. If the pin has a PINTYPE property attached, this property value is used as described in the following table: Table 4-4. Mapping PINTYPE to VHDL Mode PINTYPE IN ENA OUT IXO IO IN IN OUT INOUT INOUT VHDL Mode
3. If the first letter of the pin name (value of the PIN property) is in the following table, VHDLwrite uses the indicated signal direction and issues a warning message. Table 4-5. Mapping PIN Name to Signal Direction First Letter of PIN Name c,C,e,E,i,I,p,P,r,R,s,S,w,W o,O t,T IN OUT INOUT Signal Direction
This rule mimics the behavior of QuickSim II. Since many users do not follow the QuickSim II naming conventions, this rule can be selectively disabled using the use_quicksim_port_mode_rule option described in Table 2-3 on page 2-8. 4. If none of the above conditions exist, the signal direction is undefined, an error diagnostic message is issued, and the VHDL source text is not generated. 5. (Last rule) - signal direction is undefined and an error message is issued. In this case, VHDLwrite uses the (illegal) port mode indeterminate in the generated VHDL.
4-13
Generating an Entity from a Schematic Schematic-to-VHDL Architecture Mapping
Generating an Entity from a Schematic

Many root-level (top-level) component structures in a design hierarchy contain a schematic, but no symbol. If VHDLwrite is asked to generate an entity declaration from such a structure, an entity declaration is generated with:
a port_clause inferred from external and global nets in the schematic no generic clause
All ports are generated with a port mode using the rules described in the previous section, but applied to the external nets and a VHDL type obtained from the external nets. To ensure that there is a correct port mode declaration for an entity being generated from a schematic (with no corresponding symbol), you should attach a PINTYPE property to all external nets with a value of IN, OUT, or INOUT.
Handling Pins with Mode Out

Figure 4-2 illustrates a very common construct found on schematic diagrams.
Pin of Mode OUT DATA_OUT U1A portout U1B Pin of Mode IN
Figure 4-2. Handling Pins of Mode OUT The output pin on instance U1A is of mode OUT and is connected not only to the portout named DATA_OUT but to the input pin of U1B which is of mode IN. The semantics of the VHDL language dictate that in order to resolve the signal, the value of DATA_OUT portout must be read. However, DATA_OUT is of mode OUT and can only be written. VHDLwrite treats all pins of mode OUT by applying the following rules:
4-14
Mapping Net Connectors
1. A local signal is created whose name is the same as the port with local_ prefixed to the name and whose type is the same as that of the port 2. All references to the port are replaced by references to the local signal 3. A concurrent signal assignment statement of the form,
portName <= local_portName;
is included in the architecture.
Mapping Net Connectors

Net connectors are used on Mentor Graphics schematics to make differentlynamed nets electrically equivalent. In VHDL, the alias declaration is used to specify an alternate name for an existing object. For example:
signal Address : bit_vector(0 to 31); alias SignBit : bit is Address(31); alias PageOffset : bit_vector(11 downto 0) is Address(0 to 11);
(Note that an alias and the original signal may have opposite range directions.) For nets with more than one name, VHDLwrite chooses a representative net name for the VHDL signal declaration and declares the other net names with VHDL alias declarations. VHDLwrite uses the following ordered list of rules for selecting the representative net name: 1. If there is a global net name, use it. If there is more than one global net name, choose among them by alphabetical order. 2. If there is more than one user-given net name, select a representative net name based on the following subset of rules: a. If exactly one of the net names is external (connected to a port), use it. b. Sort based on the following three rules, picking the name that sorts first.
4-15
Mapping Bus Rippers
Given two names that are both bus members, pick the one whose
parent is widest.
Given a name that is a member of a bus and one that is not, pick the
name that is a member of a bus.
Pick the name that comes first in alphabetical order.

3. If there are multiple internal names and no user-given names, sort the names according to the three subrules above and pick the one that sorts first. A multidimensional array cannot be aliased. When a net connector is used with a multidimensional net, VHDLwrite issues an error message.
Mapping Bus Rippers

The use of bus rippers or net connectors may result in a design that has no mapping to VHDL. Consider the following design fragment:
A(0:1) A(1)
B(0:3) B(0)
Figure 4-3. Mapping Bus Rippers Signal A(1) is ripped from bus A(0:1), signal B(0) is ripped from bus B(0:3), and a net connector connects A(1) and B(0). In VHDL terms, the problem is that although there appear to be 6 signals - A(0), A(1), B(0), B(1), B(2), B(3) - only 5 of them are distinct. If VHDLwrite starts by
4-16
Mapping Bus Rippers
declaring signal A first, the generated VHDL would be as follows and there would not be a full declaration of the signal B(0:3):
signal A : bit_vector(0 to 1); alias B : bit_vector (0 to 0) is A(1);
Therefore, for any situation in which bus rippers or net connectors would require declaring only part of a bus, VHDLwrite issues an error message. If the rippers RULE property value is parameterized, as shown in Figure 4-4, VHDLwrite assumes that the subsequent evaluation of that parameterization results in valid VHDL.
A(0:1)
B(0:3)
A(X)
B(Y)
Figure 4-4. Mapping Parameterized Bus Rippers
4-17
Complex Bus Structures
Complex Bus Structures

In some cases, a design contains a complex bus structure which does not map directly into a single VHDL signal or alias declaration. Figure 4-5 shows three examples of such structures.
A(31:0) X B(15:0) C(15:0)
31
7:0 7:0
30
29
31:24
28 Z(31:0)
15:8
BIT24IN 24 M(31:0)
Figure 4-5. Schematic with Complex Bus Structures When VHDLwrite encounters such structures, it must split up one or more busses into smaller busses, each with its own unique name (original name plus a unique 4digit suffix). For the design above, the resulting VHDL is as follows:
signal A : STD_LOGIC_VECTOR(31 downto 0); alias C0001 : STD_LOGIC_VECTOR(7 downto 0) is A(7 downto 0); alias C0002 : STD_LOGIC_VECTOR(15 downto 8) is A(31 downto 24); signal Z0003 : STD_LOGIC_VECTOR(31 downto 31); signal Z0004 : STD_LOGIC_VECTOR(30 downto 30); alias Z0005 : STD_LOGIC_VECTOR(29 downto 29) is Z0003(31);
4-18
Mapping Net Bundles
alias Z0006 : STD_LOGIC_VECTOR(28 downto 28) is Z0004(30); signal Z0007 : STD_LOGIC_VECTOR(27 downto 0); signal M0008 : STD_LOGIC_VECTOR(31 downto 25); alias M0009 : STD_LOGIC_VECTOR(24 downto 24) is BIT24IN; signal M0010 : STD_LOGIC_VECTOR(23 downto 0);
Notice that B(15:0) is never declared. This is a situation where a bus is exactly equivalent to another bus that is exploded into smaller sub-busses. Rather than repeat the same declarations for B that were generated for C, VHDLwrite will simply substitute the appropriately declared portion of C in any instance port maps that originally referenced bus B.
Mapping Net Bundles

If VHDLwrite encounters a net bundle, VHDLwrite will issue an error diagnostic and the design will not be netlisted.
Mapping Global Nets

VHDLwrite distinguishes among global nets based on the value of the net's INIT property. For global nets with an INIT property having a value of OSF or 1SF, VHDLwrite does not create a truly-global VHDL signal. Instead, VHDLwrite creates a local signal of the same name in each architecture that would have referenced the global net. VHDLwrite initializes the local signal to the corresponding 0SF or 1SF value both statically (at compile time) and with a concurrent signal assignment statement (during simulation). For example, assume that a schematic references the global net VCC with an INIT property of 1SF. VHDLwrite adds the following statements to the generated VHDL source file:
signal VCC : std_logic := '1'; ... begin ... VCC <= '1';
4-19
Mapping Frames
If portions of a bus are connected to one or more of these global nets, VHDLwrite generates a choices static initialization statement similar to the following:
signal W : std_logic_vector (0 to 15) := (0 to 5 => '1');
VHDLwrite handles all other global nets in the following way:
They are declared in a special package named global_signals_

<top_level_entity>, where <top_level_entity> is name to the root component structure of the design
The VHDL statement,

USE work.global_signals_top_level_entity.all;
is used inside all entity declarations for the given design (You may specify a library other than work using the work_library keyword in the options file.)
The syntax,
global_signals_top_level_entity.signal_name
is used for all references to these other global nets. This special package is created (and referenced) only if the schematic design has global nets which do not have an INIT property or have an INIT property with a value other than 0SF or 1SF. This convention for handling global nets does not work transparently with the current release of Mentor Graphics synthesis tools because the synthesis-generated VHDL (obviously) does not declare the USE of this VHDLwrite generated special package.
Note
Mapping Frames
FOR, IF, CASE, and OTHERWISE frames are schematic constructs provided by Design Architect to allow repetitive or conditional inclusion of circuitry in a final netlist. The following sections describe how VHDLwrite maps these constructs into VHDL source code.
4-20
Mapping Frames
Mapping FOR Frames

A frame expression must be specified in one of the following two ways:
FOR var := expression1 TO expression2 FOR var := expression1 DOWNTO expression2

(where expression1 and expression2 may be identical) VHDLwrite maps the frame expression to the equivalent VHDL generate_ parameter_specification. The mapping is straightforward; if var is an illegal VHDL identifier, VHDLwrite will, based on the setting of the map_user_names keyword in the options file, either map var to a legal VHDL identifier or issue an error message. The generated VHDL has the following general form:
LABEL: for var in expression1 DIRECTION expression2 generate BLOCK_LABEL: block begin -- example component instantiation CELL port map (expressions probably involving var); -- other stuff end block; end generate;
In the above general form, VHDLwrite automatically generates LABEL (from the internal name of the FOR Frame) and applies it to the VHDL generate statement. This label enables a configuration statement to reference the generated component instantiations. DIRECTION is either TO or DOWNTO and CELL represents the appropriate component-instantiation statement.
Complications and Subtleties

VHDL requires that signals be fully declared before they are used. For signals which appear both inside and outside a frame, VHDLwrite needs to determine whether the framed circuitry increases the signal width. For example, consider a sheet that declares SIG(0:23) and which also contains framed circuitry that references SIG(X). Conceptually, the VHDL signal declaration for SIG would need to be something like the following:
4-21
Mapping Frames
signal SIG : bit_vector( min(0, expression1, expression2) TO max(23, expression1, expression2)
);
(where expression1 and expression2 refer to the frame expression). This is not legal VHDL. VHDLwrite assumes for this situation that the framed circuitry does not increase the signal width and issues a diagnostic note. VHDLwrite must identify those signals that appear only inside a frame body and place suitable declarations at the level of the surrounding block. The nature of these declarations depends on whether a signal was explicitly named by the user. Signals with the same user name are shorted together, while unnamed signals are unique per frame iteration. VHDLwrite handles unnamed signals by making the generate body contained within a block statement. For example, consider the frame in Figure 4-6:
Unnamed Wire A(I) 0 0 B(I) 0 0
FOR I := 0 TO N-1
Figure 4-6. For Frame The generated VHDL source text will have the following form:
--added to declaration section signal A : bit_vector(0 TO N-1); signal B : bit_vector(0 TO N-1); --added to architecture body LABEL: for I in 0 TO N-1 generate BLOCK_LABEL: block signal UniqueSignal : STD_LOGIC;
4-22
Mapping Frames
begin CELL port map (A(I), UniqueSignal); CELL port map (UniqueSignal, B(I)); end block; end generate;
A reference to an arrayed signal may use an expression - most commonly involving the FOR-loop variable (e.g., SIG(I + 1)). Using expressions complicates the generation of the signal declaration (which must span the full range of the array). VHDLwrite handles these situations as follows:
If all references to an arrayed signal have the form

SIG(<constant>) or SIG(<FOR-loop variable>) then VHDLwrite ignores the <constant>s and generates
signal SIG: <type>(expression1 to expression2);
where <type> is the appropriate signal data type.

SIG(<constant>) or SIG(<FOR-loop variable>[<constant_offset>]) then VHDLwrite ignores the <constant>s and generates
signal SIG : <type>(expr1 to expr2); where <type> is the appropriate signal data type and expr1 to expr2 are the
sum of the <FOR-loop expression1,2> and the minimum/maximum of the <constant_offset>s (depending on whether DIRECTION is "TO" or "DOWNTO").

SIG(<constant>) or SIG(<FOR-loop variable>) but there is at most one more-complex signal reference - e.g., SIG(2*I + 1), then VHDLwrite constructs the signal declaration by replacing occurrences of the FOR-loop variable in the signal reference by the frame's expression1 and expression2. In Figure 4-6, if instead of A(I) the reference was to A(2*I + 1), the signal declaration would be
signal A : bit_vector((2*0 + 1) TO (2*N + 1));
If all the references to an arrayed signal are not addressed by the above descriptions, VHDLwrite issues an error message.
4-23
Mapping Repeating Instances
Mapping IF Frames
An IF frame does not raise any additional issues relative to FOR-frame processing.
Mapping CASE and OTHERWISE Frames

VHDLwrite maps CASE frames to IF frames with the same frame expression. The OTHERWISE frame is mapped to an IF frame whose expression is the Boolean negation of the expressions used in all the CASE frames for the same parameter.
Mapping Repeating Instances

Since repeating instances (a new feature in Design Architect version 8.5_1) are written to the EDDM as FOR frames, they will be handled just as FOR frames are currently handled in the unevaluated mode of VHDLwrite.
Schematic Constructs that Do Not Map

There are many symbol and schematic constructs that do not map to VHDL. The first step in generating VHDL source code from a schematic-based design is to perform a quick visual check for these incompatible constructs. The design must then be modified to work around these constructs. The following subsections provide a partial list of constructs that will cause errors and stop the output of VHDL.
Net Bundles
If VHDLwrite encounters a net bundle while generating a netlist from a source schematic, VHDLwrite will issue an error diagnostic and the design will not be netlisted. If VHDLwrite encounters a net bundle while generating a netlist from a design viewpoint, the net bundle will be ignored, a warning message will be issued and
4-24
Schematic-to-VHDL Architecture Mapping Schematic Constructs that Do Not Map
the leaf member nets of the net bundle will result in VHDL signal or alias declarations.
Pin-to-Net Bundle Connections

When VHDLwrite is generating a VHDL port map for an instance from the pinnet connections, the scalar and bus connectivity will be preserved in all cases except the case where a bus pin is connected to a net bundle as shown in Figure 4-7.
Z{Y,X,W} V{U,T,S,R}
A(0:2) B{ C(0:2), D}
Figure 4-7. Bus/Bundle Connections that Do Not Map
Two Ports Shorted Together

Figure 4-8 illustrates a schematic construct with two differently-named ports shorted together using a net connector.
A
Figure 4-8. Two Ports Shorted Together VHDL does not allow the declaration of electrically-equivalent ports in an interface. VHDLwrite detects this situation and issues an error message.
4-25
Schematic Constructs that Do Not Map Schematic-to-VHDL Architecture Mapping
Unnamed Nets Connected to Wide Pins

Figure 4-9 illustrates two parameterized wide pins connected together by a parameterized bus.
X(0:N-1) P(0:N-1) Q(M-1:0)
N=4
M=4
Figure 4-9. Unnamed Nets that Connect Two Wide Pins N and M are defined as generics and attached to the body of each symbol. Although the component interface definitions of pins P and Q will see the appropriate generic values of N and M, the signal declaration for X has a different scope because it is inside an architecture body. This means that the elaboration of the signal range of X will not see the generic N and its value 4. This causes VHDLwrite to issue an error message.
Global Net Ripped from a Bus

Figure 4-10 illustrates a schematic having a bus A(0:10) with a single bit B ripped and connected to a global net such as VCC. A VHDL signal declaration must describe all of a net, hence there is no way to map this connection to VHDL without making all of signal A global. If VHDLwrite detects this situation, it issues an error message.
A(0:10) (4) B VCC
Figure 4-10. Global Net Ripped from a Bus
4-26
Schematic-to-VHDL Architecture Mapping Schematic Constructs that Do Not Map
Multidimensional Ports
Multidimensional ports, for example A(M:N;I:J), require that a special type-mark be declared in an auxiliary package. VHDLwrite does not support such an auxiliary package. If a multidimensional port is found, VHDLwrite issues an error message.
Pin Names Referencing a Bus

Consider the symbol illustrated in Figure 4-11:
INPUT(3) Q(0:3)
SYMBOL Q(7) CLOCK RESET(0:7) DATA
Figure 4-11. Pin Names Referencing a Bus INPUT(3) references a single bit of an otherwise undefined bus with the basename INPUT. A port in a VHDL-compliant component interface must declare the whole bus; since there are no other references to any part of INPUT, VHDLwrite assumes that the net has a width of 1 and that the corresponding VHDL declaration is something like the following:
port (INPUT : in std_logic_vector(3 to 3); ...);
Q(0:3) and Q(7) reference bits of an otherwise-undefined wide net with basename Q. A port in a VHDL-compliant interface must declare all of a wide net; If the coalesce_wide_pins option is off, then VHDLwrite generates an error message. Even if the set of ports referencing the wide net Q implied a non-disjoint bit vector - e.g., Q(0:3) and Q(4) - VHDLwrite would still generate an error; a VHDL-compliant interface would have to declare the single port Q(0:4). If the coalesce_wide_pins option is set to on, then VHDLwrite will determine the full range for the port Q and declare the port accordingly. If the range is disjoint, VHDLwrite uses the minimum and maximum as the range. Also, VHDLwrite will
4-27
Schematic Properties Mapped to VHDL Schematic-to-VHDL Architecture Mapping
check the port mode for each pin to ensure that there are no conflicting values. If a conflict is detected, an error message is issued.
Schematic Properties Mapped to VHDL

Table 4-6 includes all properties that VHDLwrite considers when it generates VHDL source from a schematic. All other properties are ignored and do not appear, in any form, in the generated VHDL. Table 4-6. Schematic Properties Mapped to VHDL Property Owner Net Property Name NET Usage signal name and optional range specification for this internal signal. See page 1-28. custom instance name. See page 1-28. Example Values data_bus(15:0)
Instance
INST
ROM64kx1
Instance
__da_hdl_arch_ name
name of the architecture hi_speed_arch or configuration name that this instance is bound to. See page 1-28. generated VHDL will not contain an inline configuration or component instantiation for instances to which this property is attached and has the value TRUE. TRUE
Instance
__da_omit_ instance
4-28
Schematic-to-VHDL Architecture Mapping Schematic Properties Mapped to VHDL
Table 4-6. Schematic Properties Mapped to VHDL [continued] Property Owner Instance Property Name __da_suppress_ units Usage The allowed values for this property are {entity, architecture, or both (entity and architecture)}. If this property is present on an instance, it causes the specified design unit to be omitted from the generated VHDL. This property does not change how the design is traversed. Example Values
Instance Instance
__da_primitive _instance (any property declared on the symbol body as a generic) (inserted into the appropriate generic statements in the component declaration, configuration, and instantiation statements) points to functional model. See page 1-28. default architecture or configuration name to be used for all instances on this sheet schematic custom configuration cfg
Instance
MODEL
Schematic __da_hdl_default Design _arch_name Object Schematic __da_hdl_arch Design _name Object
name to use for the gate_schematic architecture generated from this schematic. If not present, the name defaults to structure.
4-29
Schematic Properties Mapped to VHDL Schematic-to-VHDL Architecture Mapping
Table 4-6. Schematic Properties Mapped to VHDL [continued] Property Owner Property Name Usage default type for new floating symbol pins added to this schematic data type of net (usually a global net) Example Values std_logic
Schematic __da_hdl_default Design _port_type Object Net __da_hdl_signal_ type
std_ulogic
4-30
Chapter 5 Function Dictionary
Introduction
This section provides reference information for the functions that support VHDLwrite functionality. This base functionality is typically accessed and executed through menu items, forms, palette icons and keys. For complete descriptions of additional user interface, printer, and AMPLE functions, refer to the following related manuals:
Common User Interface Reference Manual contains information about all

of the Common User Interface functions.
Common User Interface Manual describes how to use the user interface
features that are common to all Mentor Graphics products. This manual tells how to manage and use windows, the popup command line, function keys, strokes, menus, prompt bars, and dialog boxes.
Printer Interface Reference Manual describes the printer and plotter user
interface and functions, such as selecting a priority level, scaling or magnifying a design, or specifying a page layout.
AMPLE Reference Manual contains information about AMPLE statements

and functions that are common to all applications.
AMPLE User's Manual describes how to use the Mentor Graphics AMPLE
language. This manual contains flow-diagram descriptions and explanations of important concepts, and shows how to write AMPLE functions.
5-1
Function Dictionary
Function Descriptions
All function descriptions in this section use the following standard format.
$title_of_function(). The title of a reference page is the function's name.

The title is followed by a brief sentence describing the function.
Valid windows and scopes. This line shows in which windows the
function may be called, followed by the scopes in which the function is defined. This is provided for users who customize the userware.
Usage. The function usage line shows exact and literal AMPLE syntax
along with the argument order. A function call usually begins with a dollar sign, with the arguments enclosed in parentheses. Arguments are separated by commas. Required arguments are in standard font; optional arguments are in italic font. A place-holder is shown in the usage line for any argument that has more than one listed value. The exact names are listed and explained Arguments subsection for that function. If the function is linked to an equivalent command, the exact and literal AMPLE syntax and the order of required arguments is shown. Uppercase characters indicate the minimum set of characters that you must type. You can omit all spaces from the minimal typing. Required arguments are in standard font; optional arguments are in italic font. A place-holder is shown in the usage line for arguments that can have more than one listed value or that can have multiple values entered. If a function can be executed from a palette, the palette name is in square brackets, followed by the name of the icon. When necessary for clarity, the window name, in parentheses, precedes the palette and icon names. One or more menu paths are shown for functions that can be called from selection sensitive popup menus. Selection free menu paths and/or pulldown menu paths are shown for logical cable functions and other functions that are not available through the selection sensitive menus. However, not all menu paths are listed for functions which can be called
5-2
Function Dictionary
through multiple menu paths. The window name, in parentheses, precedes the menu path. An arrow at the end of a menu path indicates there is a cascading submenu not shown in the function usage.
Description. This subsection describes the function's behavior, along with

any of its undo capabilities.
Arguments. This subsection displays a bulleted list of required and

optional arguments and provides a description of each argument. For each argument, prompt text (that is, the text in the prompt bar and/or dialog box that corresponds to the argument) is shown in parentheses. Some arguments are defined as one-of-n names or switches. In such instances, both the function and command usage lines contain a placeholder for the argument name or the switch. The command usage appears in parentheses and indicates the minimum typing requirements. In the description of the argument, its possible values are listed as name literals. If a default one-of-n value or switch exists, that choice is preceded by a right arrow ().
Example(s). This subsection contains examples of function usage and,

where applicable, command usage and menu usage.
Related Functions. This subsection lists related functions. When viewed in

the Bold Browser, each item is a hyperlink to the function description.
Related Internal State Functions. This subsection lists related internal

state functions. When viewed online, each item is a hyperlink to the description of the function.
5-3
Function Dictionary
Table 5-1. Summary of VHDLwrite Functions VHDLwrite Function $delete_all_hdl_entity_ generics() Function Description and Design Architect Menu Path (Symbol Editor)(ADD Popup) Delete VHDL Info > All Generics Removes all the __da_generic properties from the logical symbol body in the currently open and active Symbol Editor window. (Symbol Editor)(ADD Popup) Delete VHDL Info > Default Architecture (Schematic Editor)(ADD Popup) VHDL Info > Delete Default Architecture Removes the default architecture name for the currently open and active symbol or the currently open and active schematic.
(Scope: symbol) $delete_default_archite cture_name()
(Scope: da_window)
$delete_default_pin_hdl (Symbol Editor)(ADD Popup) _type() Delete VHDL Info > Default Pin Type (Schematic Editor)(ADD Popup) VHDL Info > Delete Default Pin Type Removes the default VHDL data type that will be assigned to the newly created symbol pins in the currently opened and active Symbol Editor (Scope: da_window) or Schematic Editor window. $delete_hdl_entity_cons (Symbol Editor)(ADD Popup) Delete VHDL Info > Constants tants() Removes the __da_hdl_constants property from the logical symbol body in the currently open and active Symbol Editor window. (Scope: symbol)
5-4
Function Dictionary
Table 5-1. Summary of VHDLwrite Functions [continued] VHDLwrite Function Function Description and Design Architect Menu Path
$delete_hdl_entity_gene (Symbol Editor)(ADD Popup) Delete VHDL Info > One Generic: ric() Removes the specified __da_generic_<NAME> property from the logical symbol body in the currently open and (Scope: symbol) active Symbol Editor window. $delete_hdl_entity_libr aries() (Symbol Editor)(ADD Popup) Delete VHDL Info > Libraries Removes the __da_hdl_libraries property from the logical symbol body in the currently open and active Symbol Editor window. (Symbol Editor)(ADD Popup) Delete VHDL Info > Packages Removes the __da_hdl_packages property from the logical symbol body in the currently open and active Symbol Editor Window.
(Scope: symbol) $delete_hdl_entity_pac kages() (Scope: symbol)
$delete_hdl_entity_state (Symbol Editor)(ADD Popup) ments() Delete VHDL Info > Statements Removes the __da_hdl_statements property from the logical symbol body in the currently (Scope: symbol) open and active Symbol Editor window. $delete_instance_archit ecture_name() (Scope: schematic) (Schematic Editor)(Instance Popup) Delete Architecture Name Deletes the __da_hdl_arch_name property from the specified (or selected) instances.
5-5
Function Dictionary
Table 5-1. Summary of VHDLwrite Functions [continued] VHDLwrite Function $delete_net_hdl_type() Function Description and Design Architect Menu Path (Schematic Editor)(NET Popup) Delete Net Type Removes the __da_hdl_signal_type property from the specified (or selected) net(s) in the currently open and active Schematic Editor window.
(Scope: schematic)
$delete_pin_hdl_mode() (Symbol Editor)(Symbol Body & Pins Popup) Delete VHDL Info > Pin Mode: (Schematic Editor)(Draw Popup) VHDL Info > Delete Pin Mode Removes the __da_hdl_port_mode property from the specified (or selected) symbol pin(s) in the currently open and active Symbol Editor (Scope: da_window) or Schematic Editor window. $delete_pin_hdl_type() (Symbol Editor)(Symbol Body & Pins Popup) Delete VHDL Info > Pin Type: (Schematic Editor)(Draw Popup) VHDL Info > Delete Pin Type Removes the __da_hdl_port_type property from the specified (or selected) symbol pin(s) in the currently open and active Symbol Editor or Schematic Editor window.
(Scope: da_window)
$delete_schematic_arch (Schematic Editor)(ADD Popup) VHDL Info > Delete Schematic Architecture itecture_name() Removes the architecture name from the currently open and active schematic. This architecture name is used when an architecture is generated from this schematic. (Scope: schematic)
5-6
Function Dictionary
$dx__import_entity_inf (Symbol Editor)(ADD Popup) o() Set VHDL Info... > Import from Entity: This function imports information from a compiled VHDL entity so that the symbol matches the entity and has VHDL information annotated on its pins and symbol body (Scope: symbol) properties. $export_vhdl() (DA Session)File > Export VHDL (Symbol Editor)Check > Export VHDL (Symbol Editor)File > Export VHDL (Schematic Editor)Check > Export VHDL (Schematic Editor)File > Export VHDL Generates and exports a VHDL netlist for the specified design starting from the specified point in the hierarchy down to either a) the most primitive level or b) the current level only. (DA Session)File > Generate > Symbol (Schematic Editor)Misc > Generate > Symbol This function generates a symbol of a specified shape and size using the information provided. Optional arguments determine whether or not a Symbol window is opened to display the generated symbol.
(Scope: lcable_session) or (Scope: da_session) $generate_symbol()
(Scope: lcable_session) (Scope: da_session) or (Scope: schematic)
5-7
Function Dictionary
$get_default_architectu (Symbol Editor)(ADD Popup) Set VHDL Info > Default Architecture: re_name() (Schematic Editor)(ADD Popup) VHDL Info > Set Default Architecture: Returns the value of the __da_hdl_default_ architecture_name property for the currently open and active symbol or the currently open and active schematic. This name is used in (Scope: da_window) binding indications for instances. $get_default_pin_hdl_t ype() (Symbol Editor)(ADD Popup) Set VHDL Info > Default Pin Type: (Schematic Editor)(ADD Popup) VHDL Info > Set Default Pin Type: Returns the default VHDL data type that will be assigned to the newly created symbol pins in the currently opened and active Symbol Editor or Schematic Editor window. If a default value has not been set, then a null string is returned. (Symbol Editor)(ADD Popup) Set VHDL Info > Constants: Returns the value of the __da_hdl_constants property from the logical symbol body in the currently open and active Symbol Editor window.
(Scope: da_window) $get_hdl_entity_consta nts()
(Scope: symbol)
$get_hdl_entity_generic (Symbol Editor)(ADD Popup) Set VHDL Info > Generics: s() Returns the values of the all the __da_generic_ <NAME> properties from the logical symbol body in the currently open and active Symbol Editor window. The values are returned as a (Scope: symbol) vector of vectors.
5-8
Function Dictionary
$get_hdl_entity_generic (Symbol Editor)(ADD Popup) Set VHDL Info > Libraries: s() Returns the value of the __da_hdl_libraries property from the logical symbol body in the currently open and active Symbol Editor (Scope: symbol) window. $get_hdl_entity_packag (Symbol Editor)(ADD Popup) Set VHDL Info > Packages: es() Returns the value of the __da_hdl_packages property from the logical symbol body in the currently open and active Symbol Editor window. (Scope: symbol) $get_hdl_entity_statem ents() (Symbol Editor)(ADD Popup) Set VHDL Info > Statements: Returns the value of the __da_hdl_statements property from the logical symbol body in the currently open and active Symbol Editor window. (Schematic Editor)(Instance Popup) Set Architecture Name: Returns the value of the __da_hdl_arch_name property from the specified (or selected) instance. (Schematic Editor)(NET Popup) Set Net Type: Returns the VHDL data type for the specified (or selected) net.
(Scope: symbol) $get_instance_architect ure_name()
(Scope: schematic) $get_net_hdl_type()
(Scope: schematic)
5-9
Function Dictionary
Table 5-1. Summary of VHDLwrite Functions [continued] VHDLwrite Function $get_pin_hdl_mode() Function Description and Design Architect Menu Path (Symbol Editor)(Symbol Body & Pins Popup) VHDL Info > Set Pin Mode: (Schematic Editor)(Draw Popup) VHDL Info > Set Pin Mode: Returns the VHDL mode of the specified (or selected) symbol pin, if previously set by the $set_pin_hdl _mode() function. Otherwise, returns the value of the PINTYPE property, if present. Otherwise, a null string is returned. (Symbol Editor)(Symbol Body & Pins Popup) VHDL Info > Set Pin Type: (Schematic Editor)(Draw Popup) VHDL Info > Set Pin Type: Returns the VHDL data type for the specified (or selected) symbol pin. (Schematic Editor)(ADD Popup) VHDL Info > Set Schematic Architecture: Returns the architecture name assigned to the currently open and active schematic. Returns structural for a schematic that has not been explicitly named with the $set_schematic_ architecture_name() function.
(Scope: da_window) $get_pin_hdl_type()
(Scope: da_window) $get_schematic_archite cture_name()
(Scope: schematic)
5-10
Function Dictionary
Table 5-1. Summary of VHDLwrite Functions [continued] VHDLwrite Function $set_default_architectu re_name() Function Description and Design Architect Menu Path (Symbol Editor)(ADD Popup) Set VHDL Info > Default Architecture: (Schematic Editor)(ADD Popup) VHDL Info > Set Default Architecture: Sets the default architecture name for the currently open and active symbol or the currently open and active schematic. If attached to a symbol body, this name is used as the architecture name in binding indications for all instances of this symbol. If attached to a schematic design object, this name is used as the architecture name in binding indications for all instances on this schematic.
(Scope: da_window)
$set_default_pin_hdl_ty (Symbol Editor)(ADD Popup) Set VHDL Info > Default Pin Type: pe() (Schematic Editor)(ADD Popup) VHDL Info > Set Default Pin Type: Sets the default VHDL data type assigned to symbol pins subsequently created in the currently open and active Symbol Editor Window or Schematic Editor window. (Scope: da_window) $set_hdl_entity_constan (Symbol Editor)(ADD Popup) Set VHDL Info > Constants: ts() Adds the specified VHDL constant statement as the value of the __da_hdl_constants property on the logical symbol body in the currently open and active Symbol Editor window. (Scope: symbol)
5-11
Function Dictionary
$set_hdl_entity_generic (Symbol Editor)(ADD Popup) Set VHDL Info > Generics: s() Adds entity-specific generics in the form of __da_generic_<NAME> properties on the logical symbol body in the currently open and (Scope: symbol) active Symbol Editor Window. $set_hdl_entity_info() (Symbol Editor)(ADD Popup)Set VHDL Info... Sets entity-specific information for the currently open and active symbol, if in a Symbol Editor window, or for the symbol corresponding to the currently open and active schematic, if in a Schematic Editor window.
(Scope: symbol)
$set_hdl_entity_librarie (Symbol Editor)(ADD Popup) Set VHDL Info > Libraries: s() Adds the specified VHDL library statement as the value of the __da_hdl_libraries property on the logical symbol body in the currently open and active Symbol Editor window. (Scope: symbol) $set_hdl_entity_packag es() (Symbol Editor)(ADD Popup) Set VHDL Info > Packages: Adds the specified VHDL use statement as the value of the __da_hdl_packages property on the logical symbol body in the currently open and active Symbol Editor window.
(Scope: symbol)
$set_hdl_entity_stateme (Symbol Editor)(ADD Popup) Set VHDL Info > Statements: nts() Adds the specified VHDL statement as the value of the __da_hdl_statements property on the logical symbol body in the currently open and active Symbol Editor window. (Scope: symbol)
5-12
Function Dictionary
Table 5-1. Summary of VHDLwrite Functions [continued] VHDLwrite Function $set_instance_architect ure_name() Function Description and Design Architect Menu Path (Schematic Editor)(Instance Popup) Set Architecture Name: Sets the value of the __da_hdl_arch_name property on the specified (or selected) instances. This name is used as the architecture name in binding indications for this instance. If specified as $schematic, VHDLwrite ed to descend and generate an architecture for the default schematic model. (Schematic Editor)(NET Popup) Set Net Type: Sets the VHDL data type for the specified (or selected) net(s). (Symbol Editor)(Symbol Body & Pins Popup) VHDL Info > Set Pin Mode: (Schematic Editor)(Draw Popup) VHDL Info > Set Pin Mode: Sets the VHDL mode for the specified (or selected) symbol pin(s). Values may be in, out, inout, or buffer. (Symbol Editor)(Symbol Body & Pins Popup) VHDL Info > Set Pin Type: (Schematic Editor)(Draw Popup) VHDL Info > Set Pin Type: Sets the VHDL data type for the specified (or selected) symbol pin(s).
(Scope: schematic) $set_net_hdl_type()
(Scope: schematic) $set_pin_hdl_mode()
(Scope: da_window) $set_pin_hdl_type()
(Scope: da_window)
5-13
Function Dictionary
$set_schematic_architec (Schematic Editor)(ADD Popup) VHDL Info > Set Schematic Architecture: ture_name() Sets the architecture name for the currently open and active schematic. This architecture name is used when an architecture is generated from (Scope: schematic) this schematic.
5-14
Function Dictionary
$delete_all_hdl_entity_generics()
Scope: symbol (VHDLwrite Personality Module) Window: Symbol Editor Usage $delete_all_hdl_entity_generics() DEL ALl Hdl entity generics (Symbol Editor)(ADD Popup) Delete VHDL Info > Constants Description Deletes all __da_generic_<NAME> properties from the logical symbol body in the currently open and active Symbol Editor window. If entity-specific generics are specified in an add_generic statement in the options file, they will still be added to the VHDL entity source code when it is generated. Arguments None Example(s)
$delete_all_hdl_entity_generics() del al h
Related Functions
$set_hdl_entity_generics() $get_hdl_entity_generics()
5-15
Function Dictionary
$delete_default_architecture_name()
Scope: da_window (VHDLwrite Personality Module) Window: Symbol Editor and Schematic Editor Usage $delete_default_architecture_name() DELete DEfault Architecture name (Symbol Editor)(ADD Popup) Delete VHDL Info > Default Architecture (Schematic Editor)(ADD Popup)VHDL Info > Delete Default Architecture Description Deletes the default architecture name assigned to the schematic (the value of the __da_hdl_default_arch_name property on the schematic design object) in the currently open and active Schematic Editor window or deletes the __da_hdl_ arch_name property from the logical symbol body of the currently open and active Symbol Editor window.
!
Caution
The result of this function takes effect immediately, unlike most other VHDLwrite functions whose effects are not made persistent (written to disk) until an explicit SAVE operation is made in the Schematic window only.
Arguments None Example(s)

$delete_default_architecture_name() del de a
Related Functions
$set_default_architecture_name() $get_default_architecture_name()
5-16
Function Dictionary
$delete_default_pin_hdl_type()
Scope: da_window (VHDLwrite Personality Module) Window: Symbol Editor and Schematic Editor Usage $delete_default_pin_hdl_type() DELETE DEfault PIn Hdl Type (Symbol Editor)(ADD Popup) Delete VHDL Info > Default Pin Type (Schematic Editor)(ADD Popup) VHDL Info > Delete Default Pin Type Description Removes the string specifying the default VHDL data type for subsequently created symbol pins. The symbol pin may be a pin in the currently open active Symbol Editor window or a floating symbol pin in the currently open an active Schematic Editor window. (A floating symbol pin is a pin instantiated on a schematic sheet but not yet included in a Make Symbol operation.) Arguments None Example(s)
$delete_default_pin_hdl_type() delete de p
Related Functions
$set_default_pin_hdl_type() $get_default_pin_hdl_type()
5-17
Function Dictionary
$delete_hdl_entity_constants()
Scope: symbol (VHDLwrite Personality Module) Window: Symbol Editor Usage $delete_hdl_entity_constants() DELETE HDL ENtity Constants (Symbol Editor)(ADD Popup) Delete VHDL Info > Constants Description Removes the __da_hdl_constants property from the logical symbol body in the currently open and active Symbol Editor window. Arguments None Example(s)
$delete_hdl_entity_constants() delete hdl en c
Related Functions
$set_hdl_entity_constants() $get_hdl_entity_constants()
5-18
Function Dictionary
$delete_hdl_entity_generic()
Scope: symbol (VHDLwrite Personality Module) Window: Symbol Editor Usage $delete_hdl_entity_generic(generic_name) DELETE HDL ENtity Generic generic_name (Symbol Editor)(ADD Popup) Delete VHDL Info > One Generic: Description Removes the specified __da_generic_<NAME> property from the logical symbol body in the currently open and active Symbol Editor window. Arguments
generic_name
A string specifying the generic name. Example(s)
$delete_hdl_entity_generic(" RISE") del hdl en g RISE
Related Functions
$set_hdl_entity_generics() $delete_all_hdl_entity_generics() $get_hdl_entity_generics()
5-19
Function Dictionary
$delete_hdl_entity_libraries()
Scope: symbol (VHDLwrite Personality Module) Window: Symbol Editor Usage $delete_hdl_entity_libraries() DELETE HDL ENtity Libraries (Symbol Editor)(ADD Popup) Delete VHDL Info > Libraries Description Removes the __da_hdl_libraries property from the logical symbol body in the currently open and active Symbol Editor window. Arguments None Example(s)
$delete_hdl_entity_libraries() $delete hdl en l
Related Functions
$set_hdl_entity_libraries() $get_hdl_entity_libraries()
5-20
Function Dictionary
$delete_hdl_entity_packages()
Scope: symbol (VHDLwrite Personality Module) Window: Symbol Editor Usage $delete_hdl_entity_packages() DELETE HDL ENtity Packages (Symbol Editor)(ADD Popup) Delete VHDL Info > Packages Description Removes the __da_hdl_packages property from the logical symbol body in the currently open and active Symbol Editor Window. Arguments None Example(s)
$delete_hdl_entity_packages() del hdl en p
Related Functions
$set_hdl_entity_packages() $get_hdl_entity_packages()
5-21
Function Dictionary
$delete_hdl_entity_statements()
Scope: symbol (VHDLwrite Personality Module) Window: Symbol Editor Usage $delete_hdl_entity_statements() DELETE HDL ENtity Statements (Symbol Editor)(ADD Popup) Delete VHDL Info > Statements Description Removes the __da_hdl_statements property from the logical symbol body in the currently open and active Symbol Editor window. Arguments None Example(s)
$delete_hdl_entity_statements() del hdl en s
Related Functions
$set_hdl_entity_statements() $get_hdl_entity_statements()
5-22
Function Dictionary
$delete_instance_architecture_name()
Scope: schematic (VHDLwrite Personality Module) Window: Schematic Editor Usage $delete_instance_architecture_name(instance_handle_names) DELete INstance Architecture Name instance_handle_names (Schematic Editor)(Instance Popup) Delete Architecture Name Description Deletes the __da_hdl_arch_name property from the instances specified by the instance handle names. If no instance handle names are specified, the property is selected from the selected instances in the currently open and active Schematic Editor window. Arguments
instance_handle_ names
One or more valid instance handle names of type string. For example I$22. Example(s)
$delete_instance_architecture_name([I$22, I$45, I$156]) del in a I$22 I$45 I$156
Related Functions
$set_instance_architecture_name() $get_instance_architecture_name()
5-23
Function Dictionary
$delete_net_hdl_type()
Scope: schematic (VHDLwrite Personality Module) Window: Schematic Editor Usage $delete_net_hdl_type(net_handles) DELete NEt Hdl Type net_handles (Schematic Editor)(NET Popup) Delete Net Type Description Removes the __da_hdl_signal_type property from the specified or selected net(s) in the currently open and active Schematic Editor window. Arguments
net_handles
A string specifying the handle name(s) for net(s) in the currently open and active Schematic Editor window. If net_handles is VOID (not specified), the property is deleted from the currently-selected nets. Example(s) The following example removes the VHDL data type for nets N$12 and N$14. The signals generated from the nets will then take on the data type of the connected pins.
$delete_net_hdl_type("std_logic_vector", [N$12, N$14]) del ne h N$12 N$14
Related Functions
$set_net_hdl_type() $get_net_hdl_type()
5-24
Function Dictionary
$delete_pin_hdl_mode()
Scope: da_window (VHDLwrite Personality Module) Window: Symbol Editor and Schematic Editor Usage $delete_pin_hdl_mode(pin_handles) DELETE PIN HDl Mode pin_handles (Symbol Editor)(Symbol&Pins Popup) Delete VHDL Info >Pin Mode: (Schematic Editor)(Draw Popup)VHDL Info > Delete Pin Mode Description Removes the __da_hdl_port_mode property from the specified (or selected) symbol pin(s) in the currently open and active Symbol Editor or Schematic Editor window. Arguments
pin_handles
A string or vector specifying the handle name(s) for symbol pin(s). If pin_handles is VOID (not specified), the __da_hdl_port_mode property is removed from the currently-selected pins. Example(s)
$delete_pin_hdl_mode(P$42) delete pin hd m
Related Functions
$set_pin_hdl_mode() $get_pin_hdl_mode()
5-25
Function Dictionary
$delete_pin_hdl_type()
Scope: da_window (VHDLwrite Personality Module) Window: Symbol Editor and Schematic Editor Usage $delete_pin_hdl_type(pin_handles) DELETE PIN HDl Type pin_handles (Symbol Editor)(Symbol&Pins Popup) Delete VHDL Info >Pin Type: (Schematic Editor)(Draw Popup)VHDL Info > Delete Pin Type Description Removes the __da_hdl_port_type property from the specified (or selected) symbol pin(s) in the currently open and active Symbol Editor or Schematic Editor window. Arguments
pin_handles
A string or vector specifying the handle name(s) for symbol pin(s). If pin_handles is VOID (not specified), the __da_hdl_port_type property is removed from the currently-selected pins. Example(s)
$delete_pin_hdl_type( [P$22, P$23, P$24]) delete pin hd t P$22 P$23 P$24
Related Functions
$set_pin_hdl_type() $get_pin_hdl_type()
5-26
Function Dictionary
$delete_schematic_architecture_name()
Scope: schematic (VHDLwrite Personality Module) Window: Schematic Editor Usage $delete_schematic_architecture_name() DELete SChematic Architecture name (Schematic Editor)(ADD Popup) VHDL Info > Delete Schematic Architecture Description Removes the architecture name from the currently open and active schematic. This architecture name is used when VHDLwrite generates an architecture from this schematic.
!
Caution

$delete_schematic_architecture_name() del sc a
Related Functions
$set_schematic_architecture_name() $get_schematic_architecture_name()
5-27
Function Dictionary
$dx__import_entity_info()
Scope: symbol (VHDLwrite Personality Module) Window: Symbol Editor Usage $dx__import_entity_info(component_name, symbol_name, hdl_ini_file_path, lib_logical_name, hdl_entity_name, architecture_or_configuration_name) IMPort ENtity Info component_name, symbol_name hdl_ini_file_path, lib_logical_name, hdl_entity_name, architecture_or_configuration_name (Symbol Editor)(Add popup) Set VHDL Info... > Import from Entity: Description This function modifies the properties on an existing symbol so that it matches a specified compiled entity and has VHDL information annotated on the symbol pins and symbol body so that VHDLwrite can netlist it later. Before making any design changes to an existing symbol, the function first verifies that the pins on the symbol match the ports in the entity. If they do not match, an error message is issued and no edits are made. The properties added to the symbol are listed in Table 3-2 on page 3-14. This function also checks to see if a PARTNER hdl model has been registered with the interface for this symbol and that it is the only model with the label hdl. If it is not present, then a partner model is registered and labeled hdl. If any other model has the label hdl, then a non-fatal error message is issued. See $generate_symbol() on page 5-33 for additional information. Arguments
component_name
Name of the component that the uses the symbol.
symbol_name
Name of the symbol that will be modified to match the entity.
5-28
Function Dictionary
hdl_ini_file_path
An optional string specifying the physical path to the modelsim.ini file. The default is the value obtained from $hdl_get_ini_file() function.
lib_logical_name
A string specifying the logical name for the ModelSim library containing the compiled entity.
hdl_entity_name
A string specifying the entity name to extract VHDL information from for addition to the symbol.
architecture_or_configuration_name
An optional name of the architecture or configuration to use as the default architecture or configuration. The default value is an empty string. Example(s)
$dx__import_entity_info(/usr2/joe/hdl.ini, hdl_lib, nand3,);
5-29
Function Dictionary
$export_vhdl()
Scope: da_session (VHDLwrite Personality Module) Window: IDW Component, IDW Hierarchy, Notepad, Schematic Editor, Session, Symbol Editor, Transcript, Userware, and VHDL Editor Usage Function: $export_vhdl(component_path_or_viewpoint_path, model_label, units_to_generate, output_to, output_to_path, check_only, message_control) Command: EXPort VHdl component_path schematic_path options_file_path units_to_generate check_only output_to output_to_path root_component no_messages Menu Path: (DA Session)File > Export VHDL (Symbol)Check > Export VHDL (Symbol)File > Export VHDL (Schematic)Check > Export VHDL (Schematic)File > Export VHDL (AutoLogic Session)File > Export VHDL
Description This function generates VHDL source code from the specified component structure and places the code in the location specified in the options file.
!
Caution
When VHDLwrite finds an error in the design source, an error message is issued to the transcript. In addition, VHDLwrite continues to generate the VHDL source files as best it can. This means that you should always examine the transcript after an export operation for possible error messages and, if found, realize that the generated code may contain errors.
Arguments
component_path_or_viewpoint_path
A required string that specifies the pathname of the component or viewpoint from which to generate VHDL source. A specific component interface may be
5-30
Function Dictionary
specified within the component by appending :name to the end of the path name. For example, $DESIGN/cpu:design1 specifies a component interface named design1 within a component named cpu located at the pathname specified by the soft prefix $DESIGN.
model_label
An optional string that specifies which model within this component to use for generating the architecture. It is a label in the component interface model table. If this option is not specified, then the default schematic model from the specified component interface is used.
units_to_generate
An optional switch specifying which VHDL design units to generate for this component. Possible options are: @entity: Only generate an entity. @arch: Only generate an architecture. @both: Generate both an entity and architecture for each component.
output_to
An optional switch controlling whether to place the generated VHDL source files in each component container or place them in a separate directory. Possible options are: @each_component: Place the generated VHDL in each component container. @source_directory: Place the generated VHDL in the directory specified by the output_to_path string.
output_to_path
An optional string that specifies the pathname to the directory where the generated VHDL is placed. If this string is not specified, the generated VHDL is placed in the working directory specified by the value of the $MGC_WD environmental variable. If $MGC_WD is not defined, the files are placed in the currently working directory (.).
5-31
Function Dictionary
check_only
An optional switch controlling whether the design is only checked (and VHDL is not generated) or whether VHDL is generated and written to disk. Possible options are: @check: Only check the design and don't generate VHDL. @nocheck: Check the design and write VHDL source files to disk.
message_control
An optional switch controlling whether to turn off the transcription of notes and warnings. Possible options are: @nonotes: Do not send note messages to the transcript. @nowarnings: Do not send warning messages to the transcript. Error messages are always sent to the transcript. Example(s) Example 1
$export($DESIGN/card_reader, , , , @check)
Only perform a VHDLwrite check on the component $DESIGN/card_reader. Example 2

$export($DESIGN/card_reader/designvpt1, @entity_only, @source_directory,$QHLAB/card_re ader_src2, , , [@nonotes, @nowarnings])
Export VHDL source files from the design viewpoint located at $DESIGN/card_reader/designvpt1. Only generate entity files from the symbols. Place the VHDL files in a directory at path $QHLAB/card_reader_src2. Do not transcript notes and warnings messages. Only transcript error messages. Related Functions None
5-32
Function Dictionary
$generate_symbol()
Scope: da_session (VHDLwrite Personality Module), lcable_session,schematic Window: DA Session, Schematic Editor Usage Function: $generate_symbol(destination_path, symbol_name, source_type, source_path, source_name, shape, shape_args, replace_option, save_window, activate_symbol, sort, body_props, pin_spacing, hdl_ini_le_path, lib_logical_name, hdl_entity_name, architecture_or_conguration_name)
Command: GENerate SYmbol destination_path, symbol_name, source_type, source_path, source_name, shape, shape_args, replace_option, save_window, activate_symbol, sort, body_props, pin_spacing, hdl_ini_le_path, lib_logical_name, hdl_entity_name, architecture_or_conguration_name Menu Path: (DA Session)File > Generate > Symbol (Schematic)Misc > Generate SYmbol Of these arguments, the hdl_ini_file_path, lib_logical_name, architecture_or_configuration_name, and the hdl_entity_name are new arguments compared to the original $generate_symbol() function defined in Design Architect. Also, the behavior of the source_type argument has been enhanced.
Note
Description This function generates a symbol of a specified shape and size using the information provided. Optional arguments determine whether or not a Symbol window is opened to display the generated symbol. This function overrides the default $generate_symbol() function in Design Architect to provide the additional option of generating a symbol from a compiled VHDL entity. For the selected entity (and architecture or configuration) in the specified ModelSim library, this function creates a symbol that matches the entity and has VHDL information annotated on its pins and symbol body so that VHDLwrite can netlist it later.
5-33
Function Dictionary
The properties added to the symbol are listed in Table 3-2 on page 3-14. After you have optionally made edits to the symbol, the symbol may be checked and saved. This function also checks to see if a PARTNER hdl model has been registered with the component interface for this symbol and that it is the only model with the label hdl. If it is not present, then a partner model is registered and labeled hdl. If any other model has the label hdl, then a non-fatal error message is issued. If the activate_symbol switch is activate, then the newly saved symbol becomes the active symbol for instantiation in the Design Architect Schematic Editor. This function assumes that the specified modelsim.ini file already has the correct library mapping for the selected ModelSim library. Arguments
destination_path (Directory)
A string data type that specifies the pathname of the component in which the generated symbol is placed. If the source_type argument is @entity, this string specifies the pathname of a directory that will contain the component and the component name will be set to the entity name specified in the source_name argument.
symbol_name (Symbol Name)

Optional name for the symbol. If source_type is @file or @schematic, this argument defaults to the leaf name of the component. If source_type is @entity, the symbol name is set to match the entity name specified in the hdl_entity_name argument, and the dialog box does not display this field. A warning is issued if this argument is specified and its value does not match the value specified in the hdl_entity_name argument.
source_type (Choose Source)

A name data type that specifies the type of source information to use for symbol generation. Possible choices are: @file: Use a pin list file created with the $create_pin_list() function in Design Architect.
5-34
Function Dictionary
@schematic: Use a schematic for input. If a Schematic window is active, @schematic becomes the default. @entity: Use the compiled entity at the pathname specified at source_path.
source_path (Component Name | Pinlist File)

A string data type that specifies the pathname to the source object, either a pin list file or schematic. If the source_type argument is @entity, this argument is ignored.
source_name (Schematic Name)

If source_type is @file, this string is set to an empty string. If source_type is @schematic, this string specifies the name of the schematic in the component specified in source_path and defaults to schematic. If source_type is @entity, this argument is ignored.
shape (Shape)
A string data type that specifies the shape to generate. Possible values are: and, or, xor, box, buf, andor, orand, adder, or trap.
shape_args
A vector data type that specifies the characteristics of the shape. The format of this argument varies based on the type of shape selected. The default is [2,2]. The following list shows the possible formats in relation to each possible shape: Shape and or xor box buf andor orand adder trap shape_args Format max_body_pins] [max_body_pins] [max_body_pins] [min_width, min_height] [min_height] [num_input_gates] [num_input_gates] [min_width, min_input_height, min_output_height] [min_width, min_input_height, min_output_height]
5-35
Function Dictionary
replace_option (Replace existing)

A required switch specifying what to do if the destination symbol already exists. If set to @replace, then the existing symbol is deleted and a symbol with the same name is created in its place. If set to @noreplace, and the symbol exists, then an error message is issued.
save_window (Once generated)

If set to @save, then the generated symbol is checked and saved without opening a window. If set to @window, then the generated symbol is displayed in a window without being checked or saved first. If set to @save_window, then the generated symbol is first checked and saved, then displayed in an edit window.
activate_symbol (Activate symbol)

This is a required switch that controls whether the generated symbol is made the active symbol for instantiation in Design Architect. If set to @activate, then the save_window option must not be set to @window. The default is @activate.
sort (Sort Pins)

An optional name that determines whether the pins on the symbol are sorted in alphabetical order: @sort or @nosort.
body_props
A required vector of vectors that contains properties to place on the body of the symbol. The format of this argument is: [ [ name, label, value, type, region], [ ... ] ] The following list defines the fields for each property: name label value type region The property name. An optional text label to be inserted as comment graphic text in front of the property value. For example, <name>=. The property value. The type of the property value: string, number, expression, triplet, or tripletcase. An integer (0-7) that indicates the region on the symbol in which to place the property. As shown in the following figure,
5-36
Function Dictionary
the region numbering starts at Region 0 the top-center of the symbol and increases in a clockwise direction.
Region 7 Region 0 Region 1
<text><value> <text><value>
<text><value>
A C B Region 6
Region 2
<text><value>
Region 5
Region 4
Region 3
The default for this argument is an empty vector.
pin_spacing (Pin spacing (in pin grids))

An optional integer data type that specifies the number of pin-grid spaces between pins. The default is 2.
hdl_ini_file_path
An optional string specifying the physical path to the modelsim.ini file. The default is the value obtained from $hdl_get_ini_file(). This argument is ignored unless the source_type is entity.
lib_logical_name
Optional string specifying the logical name for the ModelSim library containing the compiled entity.
hdl_entity_name
Optional string specifying the entity name to generate the symbol from. This argument is ignored unless the source_type is entity.
5-37
Function Dictionary
architecture_or_configuration_name
An optional name of the architecture or configuration to use as the default architecture or configuration. The default is an empty string. Example(s)
$generate_symbol(/home/joe/gates, , @entity, , , box, [2,2], @replace, @save_window, @activate, @nosort, [], 2, /usr2/joe/hdl.ini, hdl_lib, nand3,);
5-38
Function Dictionary
$get_default_architecture_name()
Scope: da_window (VHDLwrite Personality Module) Window: Symbol Editor and Schematic Editor Usage $get_default_architecture_name() GET DEfault Architecture Name (Symbol Editor) (ADD Popup) VHDL Entity Info > Default Architecture (Schematic Editor) (ADD Popup) VHDL Info > Default Architecture Description Returns the default architecture name assigned to this schematic (the value of the __da_hdl_default_arch_name property on the schematic design object) if in the schematic editor or value of the __da_hdl_arch_name property from the logical symbol body of this symbol (if in the symbol editor). Arguments None Example(s)
$get_default_architecture_name() get de a
Related Functions
$set_default_architecture_name() $delete_default_architecture_name()
5-39
Function Dictionary
$get_default_pin_hdl_type()
Scope: da_window (VHDLwrite Personality Module) Window: Symbol Editor and Schematic Editor Usage $get_pin_hdl_type(pin_handle) GET PIn Hdl Type pin_handle (Symbol Editor) (ADD Popup) VHDL Entity Info > Pin Type Description Returns a string specifying the default VHDL data type that is assigned to newly created symbol pins on this symbol or schematic. If a default has not been set with the $set_default_pin_hdl_ type() function, then a null string is returned. Arguments None Example(s)
$get_default_pin_hdl_type()
may return a string value such as:

std_ulogic
Related Functions
$set_default_pin_hdl_type() $delete_default_pin_hdl_type()
5-40
Function Dictionary
$get_hdl_entity_constants()
Scope: symbol (VHDLwrite Personality Module) Window: Symbol Editor Usage $get_hdl_entity_constants() GET HDL ENtity Constants (Symbol Editor) (ADD Popup) VHDL Entity Info Description Returns the value of the __da_hdl_constants property that is attached to the logical symbol body in the open and active Symbol Editor Window. Arguments None Example(s)
$get_hdl_entity_constants()
Related Functions
$set_hdl_entity_constants() $delete_hdl_entity_constants()
5-41
Function Dictionary
$get_hdl_entity_generics()
Scope: symbol (VHDLwrite Personality Module) Window: Symbol Editor Usage $get_hdl_entity_generics() GET HDL ENtity Generics (Symbol Editor) (ADD Popup) VHDL Entity Info Description Returns the value of the __da_generic<generic_name> properties that are attached to the logical symbol body in the open and active Symbol Editor Window. The returned value is a string vector of string vectors. For example:
["RISE","time","5"], ["FALL","time",""], [MODEL,"string",""]

$get_hdl_entity_generics()
Related Functions
$set_hdl_entity_generics() $delete_all_hdl_entity_generics() $delete_hdl_entity_generic()
5-42
Function Dictionary
$get_hdl_entity_libraries()
Scope: symbol (VHDLwrite Personality Module) Window: Symbol Editor Usage $get_hdl_entity_libraries() GET HDL ENtity Libraries (Symbol Editor) (ADD Popup) VHDL Entity Info Description Returns the value of the __da_hdl_libraries property that is attached to the logical symbol body in the open and active Symbol Editor Window. If no value has been specified for this property, a null string ("") is returned. Arguments None Example(s)
$get_hdl_entity_libraries()
Related Functions
$set_hdl_entity_libraries() $delete_hdl_entity_libraries()
5-43
Function Dictionary
$get_hdl_entity_packages()
Scope: symbol (VHDLwrite Personality Module) Window: Symbol Editor Usage $get_hdl_entity_packages() GET HDL ENtity Packages (Symbol Editor) (ADD Popup) VHDL Entity Info Description Returns the value of the __da_hdl_packages property that is attached to the logical symbol body in the open and active Symbol Editor Window. If no value has been specified for this property, a null string ("") is returned. Arguments None Example(s)
$get_hdl_entity_packages()
Related Functions
$set_hdl_entity_packages() $delete_hdl_entity_packages()
5-44
Function Dictionary
$get_hdl_entity_statements()
Scope: symbol (VHDLwrite Personality Module) Window: Symbol Editor Usage $get_hdl_entity_statements() GET HDL ENtity Statements (Symbol Editor) (ADD Popup) VHDL Entity Info Description Returns the value of the __da_hdl_statements property that is attached to the logical symbol body in the open and active Symbol Editor Window. If no value has been specified for this property, a null string ("") is returned. Arguments None Example(s)
$get_hdl_entity_statements()
Related Functions
$set_hdl_entity_statements() $delete_hdl_entity_statements()
5-45
Function Dictionary
$get_instance_architecture_name()
Scope: schematic (VHDLwrite Personality Module) Window: Schematic Editor Usage $get_instance_architecture_name(instance_handle_name); GET INstance Architecture Name instance_handle_name (Schematic Editor) (Instance Popup) Architecture Name Description Returns the __da_hdl_arch_name property from the instance specified by the instance handle name. If an instance handle name is not specified, the value is returned from the currently selected instance. Arguments
instance_handle_ name
One instance handle name of type string. For example I$22. Example(s)
$get_instance_architecture_name(I$22) get in a I$22
Related Functions
$set_instance_architecture_name() $delete_instance_architecture_name()
5-46
Function Dictionary
$get_net_hdl_type()
Scope: schematic (VHDLwrite Personality Module) Window: Schematic Editor Usage $get_net_hdl_type(net_handle) GET NEt Hdl Type net_handle (Schematic Editor) (NET Popup) Net HDL Type Description Returns a string specifying the VHDL data type for the specified (or selected) net. If a net handle name is not specified, the value is returned from the currently selected net. Arguments
net_handle
A string specifying the handle name for a net in the currently open active Schematic Editor window. Example(s)
$get_net_hdl_type(N$22) get ne h N$22
May return
std_logic_vector (a value of type string)
Related Functions
$set_net_hdl_type() $delete_net_hdl_type()
5-47
Function Dictionary
$get_pin_hdl_mode()
Scope: da_window (VHDLwrite Personality Module) Window: Symbol Editor and Schematic Editor Usage $get_pin_hdl_mode(pin_handle) GET PIN HDl Mode pin_handle (Symbol Editor) (Symbol&Pin Popup) VHDL Entity Info > Pin Mode (Schematic Editor) (Draw Popup) VHDL Info > Pin Mode Description Returns a string specifying the VHDL mode(direction) for the specified or selected symbol pin. The symbol pin may be a pin in the currently active symbol window or a floating symbol pin in the currently active schematic window. A floating symbol pin is a pin instantiated on a sheet but not yet included in a Make Symbol operation. Arguments
pin_handle
A string specifying the handle name for a symbol pin in the currently open and active Symbol Editor or Schematic Editor window. Example(s)
$get_pin_hdl_mode(P$22)
May return in (a value of type string) Related Functions

$set_pin_hdl_mode() $delete_pin_hdl_mode()
5-48
Function Dictionary
$get_pin_hdl_type()
Scope: da_window (VHDLwrite Personality Module) Window: Symbol Editor and Schematic Editor Usage $get_pin_hdl_type(pin_handle) GET PIN HDl Type pin_handle (Symbol Editor) (Symbol&Pin Popup) VHDL Entity Info > Pin Type (Schematic Editor) (Draw Popup) VHDL Info > Pin Type Description Returns a string specifying the VHDL data type for the specified or selected symbol pin. The symbol pin may be a pin in the currently active symbol window or a floating symbol pin in the currently active schematic window. (A floating symbol pin is a pin instantiated on a sheet but not yet included in a Make Symbol operation.) Arguments
pin_handle
A string specifying the handle name for a symbol pin in the currently open and active Symbol Editor or Schematic Editor window. Example(s)
$get_pin_hdl_type(P$22)
May return: std_logic_vector (a value of type string) Related Functions

$set_pin_hdl_type() $delete_pin_hdl_type()
5-49
Function Dictionary
$get_schematic_architecture_name()
Scope: schematic (VHDLwrite Personality Module) Window: Schematic Editor Usage $get_schematic_architecture_name() GET SChematic Architecture Name (Schematic Editor) (ADD Popup) VHDL Info > Schematic Architecture Description Returns the architecture name for the currently open and active schematic. If the architecture name has not been explicitly set with the $set_schematic_architecture_name() function, this function returns the default name structural. This value is not saved as a property value but is saved as a value in the data base with the schematic design object. Arguments None Example(s) Executing the following:
$get_schematic_architecture_name() get schematic arch
may return a string value such as: dataflow Related Functions

$set_schematic_architecture_name() $delete_schematic_architecture_name()
5-50
Function Dictionary
$set_default_architecture_name()
Scope: da_window (VHDLwrite Personality Module) Window: Symbol Editor and Schematic Editor Usage $set_default_architecture_name(arch_name); SET DEfault Architecture Name arch_name | configuration config_name (Symbol Editor) (ADD Popup) VHDL Entity Info > Default Architecture (Schematic Editor) (ADD Popup) VHDL Info > Default Architecture Description Sets the default architecture name assigned to this schematic (the value of the __da_hdl_default_arch_name property on the schematic design object) if in the schematic editor or sets the value of the __da_hdl_arch_name property on the logical symbol body of this symbol (if in the symbol editor). If you specify the word configuration before the name, VHDLwrite interprets the name as a configuration name. For example configuration <config_name>. This value is used as the default architecture or configuration name for instances on the schematic, not the default architecture name for the schematic itself. Refer to page 4-3 for the search rules on how VHDLwrite determines the architecture name for an instance.
!
Caution
Arguments
arch_name
A string specifying the default architecture name.
config_name
A string specifying the default configuration name.
5-51
Function Dictionary
Example(s)
$set_default_architecture_name("custom") $set_default_architecture_name("configuration config1") set de a "custom"
Related Functions
$get_default_architecture_name() $delete_default_architecture_name()
5-52
Function Dictionary
$set_default_pin_hdl_type()
Scope: da_window (VHDLwrite Personality Module) Window: Symbol Editor and Schematic Editor Usage $set_default_pin_hdl_type(type_name) SET DEfault PIn hdl type type_name (Symbol Editor) (ADD Popup) VHDL Entity Info > Default Pin Type (Schematic Editor) (ADD Popup) VHDL Info > Default Pin Type Description Sets a string specifying the default VHDL data type for newly created symbol pins. The symbol pin may be a pin in the currently active symbol window or a floating symbol pin in the currently active schematic window. (A floating symbol pin is a pin instantiated on a sheet but not yet included in a Make Symbol operation.) Arguments
type_name
A string specifying the VHDL data type to be assigned to newly created symbol pins. Example(s)
$set_default_pin_hdl_type(std_ulogic) set de p std_ulogic
Related Functions
$get_default_pin_hdl_type() $delete_default_pin_hdl_type()
5-53
Function Dictionary
$set_hdl_entity_constants()
Scope: symbol (VHDLwrite Personality Module) Window: Symbol Editor Usage $set_hdl_entity_constants(constant_statement) SET HDL ENtity Constants constant_statement (Symbol Editor) (ADD Popup) VHDL Entity Info (Symbol Editor) (ADD Popup) VHDL Entity Info > Constants Description Adds entity-specific VHDL constant statements to this symbol. The argument must be a valid VHDL statement or statements appended together with semicolons. This information is added to the logical symbol body as the __da_hdl_constants property value.
!
Caution
VHDLwrite does not verify that the argument is appropriate VHDL or even syntactically correct.
Arguments
constant_statement
A string specifying the valid VHDL constant statement(s). Example(s)
$set_hdl_entity_constants("constant pi 3.14; constant mm .001;")
Related Functions
$get_hdl_entity_constants() $delete_hdl_entity_constants()
5-54
Function Dictionary
$set_hdl_entity_generics()
Scope: symbol (VHDLwrite Personality Module) Window: Symbol Editor Usage $set_hdl_entity_generics(generics) SET HDL ENtity Generics generics (Symbol Editor) (ADD Popup) VHDL Entity Info (Symbol Editor) (ADD Popup) VHDL Entity Info > Generics Description Adds entity-specific generics to this symbol in the form of __da_generic<name> property values. The values specified in this function override any entity-specific values by the same name that may be specified in an add_generic or delete_generic statement in the VHDLwrite options file. If only a generic name is specified and a logical symbol body property exists by the same name, then the value of the logical symbol body property is passed into the generated VHDL code as a generic. Arguments
generics
A string vector of string triples specifying generics. The triplet specifies 1) the generic name 2) the generic type and 3) the default value. For example:
"["RISE","time","5"],["FALL","time",""], [MODEL,"string",""]
Example(s)
$set_hdl_entity_generics("["RISE" , "time" , "5"] , ["FALL" , "time" , ""]")
Related Functions
$get_hdl_entity_generics() $delete_all_hdl_entity_generics() $delete_hdl_entity_generic()
5-55
Function Dictionary
$set_hdl_entity_info()
Scope: symbol (VHDLwrite Personality Module) Window: Symbol Editor Usage $set_hdl_entity_info(libraries, packages, constants, statements, generics) SET HDL ENtity Info libraries, packages, constants, statements, generics (Symbol Editor) (ADD Popup) VHDL Entity Info Description Adds entity-specific information to this symbol in the form of __da_hdl property values. The values specified in this function override any entity-specific values by the same name that may be specified in an add_generic or delete_generic statement in the VHDLwrite options file. If only a generic name is specified along with its type and a logical symbol body property exists by the same name, then the value of the logical symbol body property value is passed into the generated VHDL code as a generic value. Arguments
libraries
A string specifying a VHDL libraries statement(s). For example:
"library IEEE , /usr/jackw/my_vhdl_lib;" or "library IEEE;library /usr/jackw/my_vhdl_lib;"
packages
A string specifying valid VHDL package statement(s). For example:
"use IEEE.std_logic.all;use /usr/jackw/my_vhdl_lib.all;"
constants
A string specifying the valid VHDL constant statement(s).
"constant pi :real:= 3.14; constant mm ;real:= .001;"
5-56
Function Dictionary
statements
A string specifying valid VHDL statement(s). For example:
"assert RISE>5;assert FALL<10;"
generics
A string vector of string triples specifying generics. The triplet specifies 1) the generic name 2) the generic type and 3) the default value. For example:
"["RISE","time","5"],["FALL","time",""]"
Example(s)
$set_hdl_entity_info(,,,,"["RISE" , "time" , "5"] , ["FALL" , "time" , ""]") set hdl ent info "library IEEE;", "use IEEE.all";, "pi:real:=3.14"
Related Functions
$get_hdl_entity_constants() $get_hdl_entity_generics() $get_hdl_entity_libraries() $get_hdl_entity_packages() $get_hdl_entity_statements() $delete_all_hdl_entity_generics() $delete_hdl_entity_constants() $delete_hdl_entity_generic() $delete_hdl_entity_libraries() $delete_hdl_entity_packages() $delete_hdl_entity_statements()
5-57
Function Dictionary
$set_hdl_entity_libraries()
Scope: symbol (VHDLwrite Personality Module) Window: Symbol Editor Usage $set_hdl_entity_libraries(library_statements) SET HDL ENtity Libraries library_statements (Symbol Editor) (ADD Popup) VHDL Entity Info (Symbol Editor) (ADD Popup) VHDL Entity Info > Libraries Description Adds entity-specific VHDL library statement(s) to this symbol. The argument must be a valid VHDL statement or statements appended together with semicolons. This information is added to the logical symbol body as the __da_hdl_libraries property value.
!
Caution
Arguments
library_statements
A string specifying a VHDL libraries statement(s). For example:
"library IEEE , /usr/jackw/my_vhdl_lib;" or "library IEEE;library /usr/jackw/my_vhdl_lib;"
Example(s)
$set_hdl_entity_libraries("library IEEE;library /usr/jackw/my_vhdl_lib;")
Related Functions
$get_hdl_entity_libraries() $delete_hdl_entity_libraries()
5-58
Function Dictionary
$set_hdl_entity_packages()
Scope: symbol (VHDLwrite Personality Module) Window: Symbol Editor Usage $set_hdl_entity_packages(package_statements) SET HDL ENtity Packages package_statements (Symbol Editor) (ADD Popup) VHDL Entity Info (Symbol Editor) (ADD Popup) VHDL Entity Info > Packages Description Adds entity-specific VHDL package statements to this symbol. The argument must be a valid VHDL statement or statements appended together with semicolons. This information is added to the logical symbol body as the __da_hdl_packages property value.
!
Caution
Arguments
package_statements
A string specifying valid VHDL package statement(s). For example:
"use IEEE.std_logic.all;use /usr/jackw/my_vhdl_lib.all;"
Example(s)
$set_hdl_entity_packages( "use IEEE.std_logic.all;use /usr/jackw/my_vhdl_lib.all;")
Related Functions
$get_hdl_entity_packages() $delete_hdl_entity_packages()
5-59
Function Dictionary
$set_hdl_entity_statements()
Scope: symbol (VHDLwrite Personality Module) Window: Symbol Editor Usage $set_hdl_entity_statements(statement_statements) SET HDL ENtity Statements statement_statements (Symbol Editor) (ADD Popup) VHDL Entity Info (Symbol Editor) (ADD Popup) VHDL Entity Info > Statements Description Adds entity-specific body statements to this symbol. The argument must be a valid VHDL statement or statements appended together with semicolons. This information is added to the logical symbol body as the __da_hdl_statements property value.
!
Caution
Arguments
statement_statements
A string specifying valid VHDL statement(s). For example:
"assert RISE>5;assert FALL<10;"
Example(s)
$set_hdl_entity_statements("assert X > 0;assert Y < 10;")
Related Functions
$get_hdl_entity_statements() $delete_hdl_entity_statements()
5-60
Function Dictionary
$set_instance_architecture_name()
Scope: schematic (VHDLwrite Personality Module) Window: Schematic Editor Usage $set_instance_architecture_name(arch_name instance_handles) SET INstance Architecture name arch_name instance_handles (Schematic Editor) (Instance Popup) Architecture Name Description This function sets the __da_hdl_arch_name property on the instances specified by the instance handle names. If an instance handle name is not specified, the property/value is assigned to the currently selected instance. Arguments
arch_or_config_name
An architecture or configuration name of type string. For example behavioral. If you specify the word configuration before the name, VHDLwrite interprets the name as a configuration name. For example configuration <config_name>.
instance_handles
One or more instance handle names of type string. For example I$22. Example(s)
$set_instance_architecture_name("behavioral", [I$22, I$45]) set in a "behavioral" I$22 I$45
Related Functions
$get_instance_architecture_name() $delete_instance_architecture_name()
5-61
Function Dictionary
$set_net_hdl_type()
Scope: schematic (VHDLwrite Personality Module) Window: Schematic Editor Usage $set_net_hdl_type(type_name, net_handles) SET NEt Hdl type type_name net_handles (Schematic Editor) (NET Popup) Net Type Description This function sets the __da_hdl_net_type property on the nets specified by the net handle names. If a net handle name is not specified, the property/value is assigned to the currently selected nets. Typically, this property is not necessary, because VHDLwrite assumes that the net type is the same as the symbol pin to which the net is connected. If you set the net data type to a value different than the data type assigned to the connected symbol pins, an error will result and VHDLwrite will not generate a source file for the design unit. Arguments
type_name
A required string specifying the VHDL data type to be assigned.
net_handles
A required string specifying the handle name(s) for net(s) in the currently open and active Schematic Editor window. If net_handles is VOID (not specified), the type_name is assigned to the currently-selected nets. Example(s) The following function sets the VHDL data type for nets N$12 and N$14 to std_logic_vector:
$set_net_hdl_type("std_logic_vector", [N$12, N$14]) SET NE H "bit" N$2
5-62
Function Dictionary
Related Functions
$get_net_hdl_type() $delete_net_hdl_type()
5-63
Function Dictionary
$set_pin_hdl_mode()
Scope: da_window (VHDLwrite Personality Module) Window: Symbol Editor and Schematic Editor Usage $set_pin_hdl_mode(mode, pin_handles) SET PIN HDl Mode mode pin_handles (Schematic Editor) (NET Popup) VHDL Info > Pin Mode Description Sets the VHDL mode (direction) for the specified or selected symbol pins. The symbol pin(s) may be pin(s) in a Symbol Editor window or floating in a Schematic Editor window. (A floating symbol pin is a pin instantiated on a sheet but not yet included in a Make Symbol operation.) Arguments
mode
Must be one of the following names specifying the VHDL mode (signal direction): @in, @out, @inout, or @buffer
pin_handles
A string or string vector specifying the handle names for symbol pins in the currently open and active Symbol Editor or Schematic Editor window. If pin_handles is VOID (not specified), the specified direction is assigned to the currently- selected pins. Example(s)
$set_pin_hdl_mode(@in, P$42)
Related Functions
$get_pin_hdl_mode() $delete_pin_hdl_mode()
5-64
Function Dictionary
$set_pin_hdl_type()
Scope: da_window (VHDLwrite Personality Module) Window: Symbol Editor and Schematic Editor Usage $set_pin_hdl_type(type_name, pin_handles) SET PIN HDl Type type_name pin_handles (Symbol Editor) (ADD Popup) VHDL Entity Info > Pin Type (Schematic Editor) (NET Popup) VHDL Info > Pin Type Description Sets the VHDL data type for the specified symbol pins. The symbol pins may be in the currently active symbol window or floating in the currently active schematic window. A floating symbol pin is a pin instantiated on a sheet but not yet included in a Make Symbol operation. Arguments
type_name
A string specifying the VHDL data type for the pins in the currently active symbol window or schematic window.
pin_handles
A string or string vector specifying the handle names for symbol pins in the currently open and active Symbol Editor or Schematic Editor window. If pin_handles is VOID (not specified), the VHDL type is assigned to the currently- selected pin(s). Example(s)
$set_pin_hdl_type("in", [P$22, P$23, P$24])
Related Functions
$get_pin_hdl_type() $delete_pin_hdl_type()
5-65
Function Dictionary
$set_schematic_architecture_name()
Scope: schematic (VHDLwrite Personality Module) Window: Schematic Editor Usage $set_schematic_architecture_name(architecture_name) SET SChematic Architecture name architecture_name (Schematic Editor) (ADD Popup) VHDL Info > Schematic Architecture Description Sets the architecture name for the currently open and active schematic. If the architecture name has not been explicitly set with the $set_architecture_name() function, then the default name is structural. This data is not saved as a property value but is saved as a value in the data base with the schematic design object. This string is used as the architecture name instead of structural for this schematic.
!
Caution
Arguments
architecture_name
A string specifying the VHDL architecture name. Example(s) The following function sets the architecture name for the currently active schematic to the string behavioral:
$set_schematic_architecture_name("behavioral")
5-66
Function Dictionary
Related Functions
$get_schematic_architecture_name() $delete_schematic_architecture_name()
5-67
Function Dictionary
5-68
Chapter 6 Shell Command Dictionary
Introduction
VHDLwrite can be invoked from a shell as described on the following pages.
6-1
Shell Command Dictionary
vhdlwrite
Usage vhdlwrite <component_pathname [:component_interface]> or <viewpoint_pathname> [-help] [-model_label] [-options_file <path_to_optionsfile>] [-option_summary] [-output_to [component | directory <path_to_directory>]] [-check_only] [-ent_only | -arch_only] [-nodescend] [-nonotes] [-nowarnings] [-nowrap] [-replace [all | none | non-primitives]] Description The vhdlwrite shell command invokes the VHDLwrite application in standalone mode. If a switch is specified in this command (such as -nodescend) and a keyword in the options file is set differently (such as descend on), the switch overrides the keyword in the options file. Arguments
component_pathname [:component_interface] or viewpoint_pathname

Generate VHDL source files from the specified component or viewpoint. Use the default component interface unless :component_interface is specified.
-help
Display a help message
-model_label <label_name>]
Use the connectivity model with the specified <label_name> to generate the toplevel architecture. If this option is not specified, then the schematic labeled default in the specified component interface table is used.
6-2
-options_file <path_to_optionsfile>
Use the options in the specified options file to generate VHDL source files.
-option_summary
Display a summary of all option values.
-output_to [component | directory <path_to_directory>]

If component is specified, place the generated VHDL source files in each component container. If directory is specified, place the files in the directory specified by the pathname. If the -output to switch is not specified, the generated VHDL source files are placed in the working directory specified by the value of the $MGC_WD environmental variable. If $MGC_WD is undefined, the files are placed in the currently working directory (.).
-check_only
Perform all the Export VHDL validity checks and output Notes, Warnings, and Error Messages. Do not generate any VHDL source files.
-entity_only | -arch_only
Only generate an entity or an architecture for this design. If this option is missing, generate both.
-nodescend
Generate VHDL only for the specified component. Do not descend the design hierarchy.
-nonotes
Do not output any Note messages
-nowarnings
Do not output any Warning messages
-nowrap
Tell VHDLwrite that the output display window does not automatically wrap long diagnostic messages.
-replace [all | none | non-primitives]

If all is specified, overwrite all existing files by the same name in the output_to directory. If none, don't overwrite any already- existing files. If non-primitive,
6-3
only overwrite existing files for non-primitive components. Already existing makefiles and compilation scripts are replaced unless replace_files none is specified. The default is non-primitive. Returned Value 0 - Success! No warnings or errors reported 1 - Probable success. At least one warning, but no errors reported 2 - Errors! At least one error reported 3 - Failure! Environment and/or operating system error(s) found Example(s)
Example 1
$MGC_HOME/bin/vhdlwrite $DESIGN/card_reader -nodescend -ent_only Meaning Generate VHDL source from the $DESIGN/card_reader component. Use the default component interface. Only generate an entity and do not descend the design hierarchy. Because -options is not specified, look for an options file called vhdlwrite.options in the current working directory. If not found, look for an options file located at $HOME/mgc/vhdlwrite/options. If there is no options file, use the defaults specified by the system software.
Example 2
vhdlwrite $DESIGN/card_reader -check_only -options $DESIGN/optionsfile Meaning (Assume that $MGC_HOME/bin has been added to the $PATH environmental variable.) Perform all the Export VHDL validity checks on the $DESIGN/ card_reader component. Use the options file at the path $DESIGN/optionsfile. Output Notes, Warnings, and Error Messages. Do not generate any VHDL source files.
Example 3
vhdlwrite $DESIGN/card_reader -model_label schematic2 -arch_only -replace all Meaning Only generate an architecture source file from the $DESIGN/card_reader component. Use the schematic called schematic2 as the design source. Replace all files by the same name that are in the target output directory.
6-4
Example 4
vhdlwrite $DESIGN/card_reader/designvpt1 Meaning Generate both entities and architectures from the design viewpoint designvpt1 using the component $DESIGN/card_reader.
6-5
6-6
Index
INDEX
C
$LIBNAME Keyword, 2-27 $LIBPATH Keyword, 2-27 $LRM Keyword, 2-27 $SOURCE Keyword, 2-27 __da_hdl_entity_name Property, 3-4 __da_hdl_lib_name Property, 3-6 Case_insensitivity, 2-20 Checking for VHDL Syntax Errors, 2-19 Schematics, 2-19 Symbols, 2-19 coalesce_wide_pins Option, 2-10, 4-27 Compilation Options, 1-16, 1-22 Compilation Template $LIBNAME Keyword, 2-27 $LIBPATH, 2-27 $LRM, 2-27 $SOURCE Keyword, 2-27 keyword substitution, 2-27 compilation_script Option, 2-10 compilation_template Option, 2-10, 2-27, 2-28 Compiling Source Files for QuickHDL, 1-34 Compiling VHDL Source Files, 2-26 component_declarations Option, 2-10 Configuration Names specifying, 1-18 configurations Option, 2-11
A
add_generic Option, 2-8 add_quoted_generic Option, 2-8 Adding VHDL Information to a Schematic, 2-3 to a Symbol, 2-1 Adding VHDL Information to a Symbol, 1-26 Adding VHDL Information to Schematic, 1-27 alias declaration use of, 4-15 Architecture Names specifying, 1-18 Architectures and Configurations Options, 1-18 Arrayed Net Names Multiple Occurences of, 4-12 Asserts, 2-23 asserts Options, 2-9 auto_type_conv Option, 2-10 Automatic Type Conversion examples, 2-21 automatic_compilation Option, 2-9, 2-27, 2-28
D
Data Type Net, 4-9 Port, 4-6 default architecture Option, 2-11 default_configuration Option, 2-11 default_libraries Option, 2-11 default_packages Option, 2-11 default_scalar_type Option, 2-12 default_vector_type Option, 2-12 delete_generic Option, 2-12 Design Verification, 2-19 Design Viewpoint concept of, 1-38 declaring primitives, 4-1 descent through evaluated design data, 4-3
B
Basic VHDL Identifiers, 3-2 Bundles mapping, 4-24 Bus Rippers mapping, 4-16 Bus Structures Complex, 4-18
Index-1
Index
INDEX [continued]
E
Entity Names Mapping, 3-4 Extended VHDL Identifiers, 3-2 $get_hdl_entity_statements(), 5-9, 5-45 $get_instance_architecture_name(), 5-9, 5-46 $get_net_hdl_type(), 5-9, 5-47 $get_pin_hdl_mode(), 5-10, 5-48 $get_pin_hdl_type(), 5-10, 5-49 $get_schematic_architecture_name(), 5-10, 5-50 $set_default_architecture_name(), 5-11, 5-51 $set_default_pin_hdl_type(), 5-11, 5-53 $set_hdl_entity_constants(), 5-11, 5-54 $set_hdl_entity_generics(), 5-12, 5-55 $set_hdl_entity_info(), 5-12, 5-56 $set_hdl_entity_libraries(), 5-12, 5-58 $set_hdl_entity_packages(), 5-12, 5-59 $set_hdl_entity_statements(), 5-12, 5-60 $set_instance_architecture_name(), 5-13, 5-61 $set_net_hdl_type(), 5-13, 5-62 $set_pin_hdl_mode(), 5-13, 5-64 $set_pin_hdl_type(), 5-13, 5-65 $set_schematic_architecture_name(), 5-14, 5-66
F
FOR Frames Mapping, 4-21 Format Options FIle, 2-6 Frame Example, 1-36 Frames complications and subtleties, 4-21 Mapping, 4-20 Functions $delete_all_hdl_entity_generics(), 5-15 $delete_default_architecture_name(), 5-16 $delete_default_pin_hdl_type(), 5-17 $delete_hdl_entity_constants(), 5-18 $delete_hdl_entity_generic(), 5-19 $delete_hdl_entity_libraries(), 5-20 $delete_hdl_entity_packages(), 5-21 $delete_hdl_entity_statements(), 5-22 $delete_instance_architecture_name(), 5-23 $delete_net_hdl_type(), 5-24 $delete_pin_hdl_mode(), 5-25 $delete_pin_hdl_type(), 5-26 $delete_schematic_architecture_name(), 5-27 $dx__import_entity_info(), 5-28 $export_vhdl(), 5-30 $generate_symbol(), 5-33 $get_active_symbol_history(), 5-21 $get_default_architecture_name(), 5-39 $get_default_pin_hdl_type(), 5-40 $get_hdl_entity_constants(), 5-41 $get_hdl_entity_generics(), 5-42 $get_hdl_entity_libraries(), 5-43 $get_hdl_entity_packages(), 5-44
G
Generating a Symbol from a compiled entiry, 1-40, 1-44 from a pinlist, 1-41 from a schematic, 1-41 Generating an Entity from a schematic, 3-1 from a symbol, 3-1 Generics adding to a symbol, 2-3 instance specific, 4-6 referenced but undeclared, 2-22 Generics Options, 1-14 Generics, Specifying on Symbol, 3-6 Global Nets
Index-2
Index
INDEX [continued]
Mapping, 4-19, 4-24, 4-25 Multidimensional Signals, 4-11
I
Identifiers, 2-20 Basic, 3-2 Extended, 3-2 IF Frames Mapping, 4-24 Invoking VHDLwrite from a Shell, 1-32
N
Name Collisions, 2-20, 2-25 Name Mapping Options, 1-18, 1-20 Naming Conventions Output Source FIles, 2-24 Net Bundles, 4-24 Net Data Type, 4-9 Non-Mapping Schematic Constructs Global Net Ripped from a Bus, 4-26 Multidimensional Ports, 4-27 Pin Names Referencing a Bus, 4-27 Pin-to-Net Bundle Connections, 4-25 Unnamed Nets Connected to Wide Pins, 4-26
K
Keyword Substitution in Compilation Template, 2-27
L
Libraries and Packages Options, 1-10 lrm Option, 2-13
M
map_entity_name Option, 2-14, 3-4 map_library Option, 2-14, 2-27, 3-5 map_user_names Option, 2-14, 2-20 Mapping Wide Pins to VHDL Text, 4-7 Bus Rippers, 4-16 component Symbol to HDL Library, 1-20, 3-5 FOR Frames, 4-21 Frames, 4-20 Global Nets, 4-19, 4-24, 4-25 IF Frames, 4-24 illegal identifiers to VHDL, 3-2 Net Connectors, 4-15 PIN Name to Signal Direction, 4-13 PINTYPE to VHDL Port Mode, 4-13 Range Direction for Buses, 4-11 Repeating Instances, 4-24 Mapping Entity Names, 3-4 mapping_file Option, 2-15, 2-26 Miscellaneous Options, 1-8 Modifying Export Options, 1-6
O
Option Statements multiple occurances of, 2-18 Options add_generic, 2-8 add_quoted_generic, 2-8 Architectures and Configurations, 1-18 asserts, 2-9 auto_type_conversion, 2-10 automatic_compilation, 2-9, 2-27, 2-28 coalesce_wide_pins, 2-10, 4-27 Compilation, 1-16, 1-22 compilation_script, 2-10 compilation_template, 2-10, 2-27, 2-28 component_declarations, 2-10 configurations, 2-11 default_architecture, 2-11 default_configuration, 2-11 default_libraries, 2-11 default_packages, 2-11 default_scalar_type, 2-12 default_vector_type, 2-12 delete_generic, 2-12
Index-3
Index
INDEX [continued]
Generics, 1-14 Libraries and Packages, 1-10 Loading from a FIle, 1-7 lrm, 2-13 map_entity_name, 2-14, 3-4 map_library, 2-14, 2-27, 3-5 map_user_names, 2-14, 2-20 mapping_file, 2-15, 2-26 Merging from a File, 1-7 Miscellaneous, 1-8 Name Mapping, 1-18, 1-20 override_vectors, 2-15 Primitive Control, 1-12, 1-16 primitive_component, 2-15 primitive_library, 2-15 primitive_netlist, 2-15 primitive_schematic, 2-16 primitive_units, 2-16 replace_files, 2-16 Reset to Defaults, 1-7 Saving to a FIle, 1-7 scalar_vector_table, 2-17 single_file_netlist, 2-17 Types, 1-12 use_quicksim_port_ mode_rule, 2-17 verbose, 2-17 vital_compliance, 2-18 Options File example of, 1-24 Format, 2-6 Search Rules, 2-6 Output Source File Naming Conventions, 2-24 Output Source Files last modification time, 2-26 overwriting, 2-26 Overidding library map for an instance, 3-6 override_vectors Option, 2-15 Overriding the Arch or Config Name, 1-30 Overriding the Architecture Name, 4-3 Overriding the Configuration Name, 4-3 Overwriting Output Source Files, 2-26
P
Parameterization, 4-6 Pins with Mode OUT, 4-14 Port Data Type, 4-6 Port Mode Determining, 4-12 generated from external nets on a schematic, 3-1, 4-14 Primitive Control Options, 1-12, 1-16 primitive_component Option, 2-15 primitive_library Option, 2-15 primitive_netlist Option, 2-15 primitive_schematic Option, 2-16 primitive_units Option, 2-16 Properties __da_generic_NAME, 3-12, 3-14 __da_generic_quoted_NAME, 3-13 __da_hdl_arch_name, 3-13, 3-14, 4-28, 4-29 __da_hdl_constants, 3-13 __da_hdl_default_arch_name, 4-29 __da_hdl_default_port_type, 3-13, 4-30 __da_hdl_entity_name, 3-4, 3-14 __da_hdl_lib_name, 3-6, 3-14 __da_hdl_libraries, 3-12, 3-14 __da_hdl_packages, 3-12, 3-14 __da_hdl_port_mode, 3-11, 3-15 __da_hdl_port_subtype, 3-11 __da_hdl_port_type, 3-11, 3-14 __da_hdl_signal_type, 4-30 __da_hdl_statements, 3-13 __da_omit_instance, 4-28 __da_suppress_units, 3-14 INST, 4-28 MODEL, 3-11, 4-29 NET, 4-28
Index-4
Index
INDEX [continued]
PIN, 3-11, 3-14 PINTYPE, 3-11, 3-15 __da_generic_NAME, 3-12, 3-14 __da_generic_quoted_NAME, 3-13 __da_hdl_arch_name, 3-13, 3-14 __da_hdl_constants, 3-13 __da_hdl_default_port_type, 3-13 __da_hdl_entity_name, 3-14 __da_hdl_lib_name, 3-14 __da_hdl_libraries, 3-12, 3-14 __da_hdl_packages, 3-12, 3-14 __da_hdl_port_mode, 3-11, 3-15 __da_hdl_port_subtype, 3-11 __da_hdl_port_type, 3-11, 3-14 __da_hdl_statements, 3-13 __da_suppress_units, 3-14 MODEL, 3-11 PIN, 3-11, 3-14 PINTYPE, 3-11, 3-15
R
Referenced but Undeclared Generics, 2-22 Repeating Instances Mapping, 4-24 replace_files Option, 2-16 Restrictions string length, 2-20 Rules for Name Mapping, 3-2
S
scalar_vector_table Option, 2-17 Schematic Checking, 2-19 Schematic Properties __da_hdl_arch_name, 4-28, 4-29 __da_hdl_default_arch_name, 4-29 __da_hdl_default_port_type, 4-30 __da_hdl_signal_type, 4-30 __da_omit_instance, 4-28 INST, 4-28 MODEL, 4-29 NET, 4-28 Shell Commands vhdlwrite, 6-2 Shell Invocation Specifying Export Options, 2-6 single_file_netlist Option, 2-17 Specifying Architecture Names, 1-18 Specifying Configuration Names, 1-18 Specifying Export Options from a Shell Invocation, 2-6 from an Application User Interface, 2-5 String Length Restrictions, 2-20 Surpressing All VHDL Code for Objects Declared Primitive, 1-17 Symbol Checking, 2-19 Symbol Properties
T
Type Conversion automatic, 2-10 examples, 2-21 Types Options, 1-12
U
use_quicksim_port_ mode_rule Option, 2-17
V
verbose Option, 2-17 Verifying the Design, 2-19 VHDL Data Types, 2-21 VHDL Export Procedure, 1-2 VHDL Sourse Files compiling, 2-26 VHDL Syntax Errors checking for, 2-19 VHDLwrite Options. See Options Viewpoints. See Design Viewpoints vital_compliance Option, 2-18
Index-5
Index
INDEX [continued]
Index-6

VHDL Write User.s and Reference Manual

Transféré par

Informations du document

Copyright

Formats disponibles

Partager ce document

Partager ou intégrer le document

Options de partage

Avez-vous trouvé ce document utile ?

Ce contenu est-il inapproprié ?

Droits d'auteur :

Formats disponibles

VHDL Write User.s and Reference Manual

Transféré par

Droits d'auteur :

Formats disponibles

VHDLwrite Users and Reference Manual

Software Version 8.6_4

VHDLwrite User's and Reference Manual, V8.6_4

TABLE OF CONTENTS [continued]

VHDLwrite User's and Reference Manual, V8.6_4

TABLE OF CONTENTS [continued]

VHDLwrite User's and Reference Manual, V8.6_4

TABLE OF CONTENTS [continued]

VHDLwrite User's and Reference Manual, V8.6_4

TABLE OF CONTENTS [continued]

VHDLwrite User's and Reference Manual, V8.6_4

VHDLwrite User's and Reference Manual, V8.6_4

VHDLwrite User's and Reference Manual, V8.6_4

VHDLwrite User's and Reference Manual, V8.6_4

About This Manual

___________________ * ModelSim EE/PLUS is referred to as ModelSim from now on.

VHDLwrite User's and Reference Manual, V8.6_4

Year 2000 Ready

About This Manual

Year 2000 Ready

A two-digit year of 00 through 68 will be interpreted as years 2000 through

a two-digit year of 69 through 99 will be interpreted as years 1969 through

VHDLwrite User's and Reference Manual, V8.6_4

Chapter 1 VHDLwrite Overview

VHDLwrite User's and Reference Manual, V8.6_4

VHDL Export Procedure

VHDL Export Procedure

(optional) Inspect the Design for Incompatible Constructs

Add Custom VHDL Information to Symbols and Sheets

Verify VHDL Export Options (Modify Options)

(optional) Execute File > VHDL Export > Check Only

Execute File > Export VHDL

(optional) Inspect and Verify VHDL Source Files

VHDLwrite User's and Reference Manual, V8.6_4

VHDL Export Procedure

VHDL Export Procedure

VHDLwrite User's and Reference Manual, V8.6_4

Exporting VHDL to a Source Directory

Exporting VHDL to a Source Directory

(Not used for viewpoint) Directory

Target Source Directory No notes Specified Here

analog_ent card_reader schematic

VHDLwrite User's and Reference Manual, V8.6_4

Exporting VHDL to a Source Directory

Exporting VHDL to a Source Directory

The design may be the path to an mgc_component structure, a design

The target source directory $QSLAB/card_reader_src specifies where the

Both entity declarations and architecture bodies are generated for

VHDLwrite User's and Reference Manual, V8.6_4

Modifying the Export Options

Modifying the Export Options

Merge from File...

Resets the current options settings to system-defined default values

Saves the current option settings to a specified file

VHDLwrite User's and Reference Manual, V8.6_4

Modifying the Export Options

Modifying the Export Options

VHDLwrite User's and Reference Manual, V8.6_4

Merge from File...

OK Reset Cancel Miscellaneous Options

Configurations IN-LINE IN-FILE NONE

Vector Direction AS-IS TO

DOWNTO Coalesce Wide Pins On

QuickSim Port Mode On Off LRM Vital 87 93 Yes No OK