ACROPOLIS TECHNICAL CAMPUS, INDORE 452020

Department of Electronics & Communication Engineering Lab Session No. 11 Page No.1/5 Digital Circuits & System CS - 303 Enrolment No. 0875 Batch No.

Performance Evaluation:
Name
Performing on Extra regular First Submission Second Submission

Grade and Remarks by the Tutor 1. Clarity about the objective of the experiment 2. Clarity about the problem statement 3. Submitted the work in desired format 4. Shown capability to solve the problem 5. Contribution to the team work. Others:

Grade

signature

1.

Title: To design asynchronous, synchronous counters ( Ring and johnson). Aims:

a) b) c) d) To understand the operation of counter circuits by JK flip-flop. To verify the truth table of synchronous and asynchronous counter. To design decade counter using asynchronous counter. To analyze the counter as a frequency divider circuits.

2.

3. Objectives: After completing the experiment, the student should be able:

a. To be able to design any MOD counter using JK flip-flop. b. To be able to design decade counter using asynchronous counter. c. To be able to use counter in designing digital clock and measuring frequency of electrical signal.

4. Problem Statement:
a) To design 4- bit MOD-12 counter using IC 7476. b) To compare the synchronous and asynchronous counter. c) How IC 7493 can be used to produce a 1.2 kHz output from a 18 kHz input signal.

5. Equipments:
DIT board, and its power supply.

ACROPOLIS TECHNICAL CAMPUS, INDORE 452020

Department of Electronics & Communication Engineering Lab Session No. 11 Page No.2/5 Digital Circuits & System CS - 303 Enrolment No. 0875 Batch No.

6. Theory:
Asynchronous Counter: When the output of a flip-flop is used as a clock input for the next flip-flop, we call the counter a ripple counter or asynchronous counter. The A flipflop must change states before it can trigger B flip-flop, and the B flip-flop has to change states before it can trigger the C Flip-flop and so on. The triggers move through the flip-flop like a ripple in water. Because of this, the overall propagation delay time is the sum of the individual delays. For instance, if each flip-flop in this four flip-flop counter has a propagation delay time of 10ns, the overall propagation delay time for the counter is 40ns.

ACROPOLIS TECHNICAL CAMPUS, INDORE 452020

Department of Electronics & Communication Engineering Lab Session No. 11 Page No.3/5 Digital Circuits & System CS - 303 Enrolment No. 0875 Batch No.

Decade Counter: A Four Flip-flop has a natural count of 16. We can thus construct any counter that has a modulus between 16 and 2, inclusive. We might choose to use four flipflops only for counters having a modulus between 16 and 9, since only three flip-flops are required for a modulus of less than 8, and only two are required for a modulus of less than 4. There are a many different methods for constructing a counter having a modified count. A counter can be synchronous, a synchronous, or a combination of these two types; furthermore, there is the decision of which count is skip.

ACROPOLIS TECHNICAL CAMPUS, INDORE 452020

Department of Electronics & Communication Engineering Lab Session No. 11 Page No.4/5 Digital Circuits & System CS - 303 Enrolment No. 0875 Batch No.

Referring the function table of the decade counter it is mainly counts 10 states from 0000 to 1001. As soon as counter reaches to 1010 all flip-flops are get reseted due to and gate and counters start counting again from 0000. Function table for Asynchronous UP / DOWN Counter:

To design 4 bit Ring counter using JK flip-flop. A Ring Counter is a type of counter composed of a circular Shift register. The output of the last shift register is fed to the input of the first register. There are two types of ring counters: A straight ring counter or Overbeck counter connects the output of the last shift register to the first shift register input and circulates a single one (or zero) bit around the ring. For example, in a 4-register counter, with initial register values of 1000, the repeating pattern is: 1000, 0100, 0010, 0001, 1000... . Note that one of the registers must be pre-loaded with a 1 (or 0) in order to operate properly. A twisted ring counter or Johnson counter connects the complement of the output of the last shift register to its input and circulates a stream of ones followed by zeros around the ring. For example, in a 4-register counter, with initial register values of 0000, the repeating pattern is: 0000, 1000, 1100, 1110, 1111, 0111, 0011, 0001, 0000... .

ACROPOLIS TECHNICAL CAMPUS, INDORE 452020

Department of Electronics & Communication Engineering Lab Session No. 11 Page No.5/5 Digital Circuits & System CS - 303 Enrolment No. 0875 Batch No.

Prepared by Megha Motta

Date

Modified on