Interrupts

Interrupt is an input to a processor that indicates the occurrence of an event EXTERNAL EVENTS: change the status of microprocessor pin INTERNAL EVENTS: timer overflow, transmission / reception of a byte through the serial ports RESPONSE OF PROCESSOR: 1. saves the current machine status, 2. Branches to execute a subprogram called I ! ACTION ON OCCURANCE OF AN INTERRUPT: "#$ %umps to the location associated with that interrupt in the program memory and starts executing from there &his location is called VECTOR &his type of interrupt is called '("&)!(* I+&(!!$#& ,fter serving the interrupt, the processor restores the original machine status and continues with the original program -" ./1 supports 5 Vectored interrupt Sources 1. 2. (xternal Interrupt 0 1. (xternal Interrupt 1 2. &imer / "ounter 0 Interrupt /. &imer / "ounter 1 Interrupt 3. erial #ort Interrupts

 4hen an interrupt is generated #" is +ow, the program starts executing the I ! pushed onto a stac5 67 'ector address is from the vectored location loaded in the #" 67 4hile the program I ! ends with !(&I Instruction executes the I !, the corresponding Interrupt vector locations in 90/1 are interrupt flag is made clear spaced out every 9 bytes. o, two cases -" ./1 contains / 8lag bits .I(0, I(1, &80, arise &81, &I 1. &he (ISR +RETI) ! "#tes : 4e put the I ! there itself 2. &he (ISR +RETI) $ ! "#tes% , %ump instruction is written at the vectored address :1 bytes maximum; and remaining I ! is written somewhere else Interrupts in 90/1 and 'ector ,ddresses are listed in the following table Interrupt Flag Affected I(0 &80 I(1 &81 Vector Cause of Interrupt (if enabled) 001< 000B< 0011< 001B< , <I=< to >)4 &ransition on pin )verflow of &imer / "ounter 0 , <I=< to >)4 &ransition on pin )verflow of &imer / "ounter 1 # ! I ) ! I & ? erial #ort !I @ &I 0021< 4hen either &I of !I flag is set Lo)est &i'(est

(xternal Interrupt 0 #in :12; &imer / "ounter 0 Interrupt (xternal Interrupt 1 #in &imer / "ounter 1 Interrupt

 (xample: "onsider the external interrupt 0 1. "#$ is busy in the main program 2. 1 0 &ransition occurs at #in 1. "urrent contents of #" are loaded onto the stac5 2. #" is loaded with the vector address 0001< /. +ext instruction at 0001< would be fetched and executed 3. , *+P instruction is written at vectored location 0001< since only 9bytes are available to write the I ! A. &he I ! lying somewhere in the program memory ends with !(&I instruction. !(&I gets the #" contents from the stac5 and "#$ again starts executing from where the main program was interrupted (xternal interrupts can be configured as either >evel &riggered : ignal must stay low until the interrupt is generated; or (dge &riggered :, transition from <igh to >ow at the interrupt is sufficient; It is also necessary to initialiBe -" ./1 Interrupts by setting Interrupt (nable :I(; register in the 8!

Initi,-i.in' !/50 Interrupts

I( register allows the programmer to enable the interrupts as needed I( is bit addressable IE12 EA IE13 77 IE15 77 IE14 ES IE15 ET0 IE16 EX0 IE10 ET/ IE1/ EX/

EA (En,8-e A--) ES ET0 EX0 ET/ EX/

06 *isable all interrupts 16 ,llows each of the individual interrupts to be enabled (nable/*isable seri,- port interrupt :#rovided (,61; (nable/*isable ti9er interrupt 0 :#rovided (,61; (nable/*isable e:tern,- interrupt 0 :#rovided (,61; (nable/*isable ti9er interrupt / :#rovided (,61; (nable/*isable e:tern,- interrupt / :#rovided (,61;

(, acts as -aster "ontrol Bit for any of the interrupt :If (,60 ;$ *isables the whole interrupt operation ; 8or any particular interrupt to occur, (, and the corresponding bit must be set (xample: (nable (xternal Interrupt 1 +OV IE < 0/// /0// " :Bit (,61 and Bit (C161; &o initialiBe the serial interrupt, I( register must be loaded with 10010000 B

Interrupt Priorities
$ser can program the interrupt priority levels by setting or clearing the bits in 8! called Interrupt #riority !egister :I#; I# !egister is also bit addressable If the bit is set, it will have high priority , high priority interrupt can interrupt the low priority interrupt but not the other way round If reDuest of interrupts of two different priority level occur simultaneously then the interrupt having the high priority will be served If reDuest of interrupts having same priority occur simultaneously, then within each priority level there is a polling structure IP12 X IP13 X IP15 PT6 IP14 PS IP15 PT0 IP16 PX0 IP10 PT/ IP1/ PX/

IP15 IP14 IP15 IP16 IP10 IP1/

#&2 # #&1 #C1 #&0 #C0

&imer 2 priority in case of 90/2 only erial Interrupt priority &imer 1 interrupt (xternal interrupt &imer 0 interrupt (xternal interrupt 0

(xample: ,ssignment of interrupt priority to timer 1 interrupt -)' I( E 1000 1100 < :(nables external interrupt 1 and timer interrupt 1; (&B #&1 :assigns a high priority to the timer interrupt; o, if both of them occur simultaneously, then the timer interrupt will be served (C,-#>(: -)' I( E 1000 1100 B :(nable (C1 and (&1; (&B #&1 (&B #C1 :Both the interrupts have high priority; In this case, the external interrupt will be served as per above table

Ti9ers ,nd Counters

)n chip timing/counting feature is used in !& ,pplications li5e pulse counting, freDuency measurement, pulse width measurement, baud rate generation, 5eeping amount of time between events etc. 90/1 has t)o 13.bit timer/counter =IFFERENCE "ET>EEN , TI+ER ,nd , COUNTER &I-(!: It counts machine cycles and provides a reference time delay or a cloc5 , machine cycle of 90/1 consists of 12 ) " periods or the counting rate or the counting rate 1/12 of the ) " freDuency ,t 12 -<B, cloc5ing period will be eDual to 1Fs ")$+&(!: "ounter of 90/1 is incremented in response to a transition from 1 0 at its corresponding external pins :&0 or &1; &hus, the counter output will be a count or a number representing the occurrences of such 1 0s at external pins 8or counting function 90/1 ta5es 2 machine cycles or 22 ) " periods to detect a 10 transitions at pin &0 or &1 4hen a counter or a timer overflows from 8888 < to 0000 < it sets a flag and generates an interrupt &he 13 bits of timer are referred as higher byte &<x and the lower byte &>x &<1 6 <igher byte of timer 1 &>16 >ower byte of timer 1 C can be 0 or 1 or 2 :90/2;

Ti9er ? Counter +odes

&here are four timer modes &imer or counter function and modes are selected by writing appropriate bits in 8! called &-)* :&imer -ode !egister; "ontrol of &imer / "ounter operation is done through 8! called &")+ :&imer "ontrol !egister;. Ti9er Contro- Re'ister (TCON) "it Address,8-e TCON12 TCON13 TCON15 TCON14 TF0 TR0 TF/ TR/ TCON15 IE0 TCON16 IT0 TCON10 IE/ TCON1/ IT/

Ti9er 0 O@erA-o) F-,' Set )(en ti9er?cou nter o@erA-o)s

Ti9er 0 run contro8it

Ti9er / o@erA-o) A-,'B set )(en ti9er ? counter / o@erA-o)s

Ti9er / run contro8it

Interrupt 0

Ti9er Interrupt 0

Interrupt / A-,'

Ti9er / interruptB IT/;/B -o) -e@etri''er IT/ ; 0B ed'e tri''er on A,--in' ed'e

Ti9er +ode Contro- Re'ister T+O= 12 C,te T+O= 13 C? T+O= 15 +0 T+O= 14 +/ T+O= 15 C,te T+O= 16 C? T+O= 10 +0 T+O= 1/ +/

Ti9er 0 =,&(: 1: &imer is enabled if I+& 61 and &!61 C?: 0: &imer 1: "ounter &imer -ode is determined by -1 -0 Mode Mode Mode Mode 0 1 2 3 M1 0 0 1 1 M0 0 1 0 1

Ti9er /

+ode /
11 bit wide timer : to maintain compatibility with 9029 family ; ame for timer 0 and timer 1 4hen count overflows, it sets the &imer Interrupt 8lag :&81 for timer 1 and &80 for timer 0; &o start timer 0, &!0 bit in &")+ should be set 1 11 bits are formed by using the upper byte &<0 :or &<1; and the lower / bits of &>0 :or &>1; &>x will count from 0.11 ,fter 11, &>x is !( (& to 0 and increment &<x

(C,-#>(: InitialiBe timer 1 in mode 0 +OV T+O=B < 0/// //// " :&16mode 0, &06mode 0, both are configured as timers. &1 is controlled by external pin 11 I+&1 given that =,&( 6 1; SET" TR0 : tart &1; SET" TR/ : tart timer 0; CLR TR0 : top &1; S*+P :Infinite >oop; &-)*.A :=ate ; in &-)* is set to 1 If it is 1 and &!1 6 1 then the timer 1 is controlled by the external input at #in 11 :; 4hen =ate 60 67 )nly &!1 enables the timer

+ode 0
ame as -ode 0 except the timers are of 13 bit ame for &imer 0 and &imer 1 -aximum count in this mode is 8888 < &<x is cascaded with the &>x to form a 13 bit timer &>x is incremented from 0.2// ,fter 2//, &>x is !( (& to 0 and &<x is incremented by 1 If 13.bit timer is set to 0, it will overflow bac5 to 0 after 3//13 machine cycles &ime *elay6:12 C 3//13.Initial 'alue;8reDuency

(C,-#>(: InitialiBe &imer 1 in mode 1 +OV T+O=B <///0 //// " :&imer 1 in mode 1; SET" TR0 : since =ate 60, &!1 can fully control the timer operation, so to start timer1 &! is set to 1 S*+P D :Infinite >oop; &imer overflow can also generate an interrupt on proper initialiBation (C,-#>(: InitialiBe timer 1 in mode 1 +OV SPB <54 & :InitialiBe #; +OV T+O=B < ///0 //// " :&imer 1 in -ode 1; SET" ET0 :(nable timer 1 interrupt; SET" TR0 : tart timer 1; SET" EA :(nable ,ll; S*+P D :Infinite >oop; &his program will start &imer 1 and when it overflows, &1 interrupt is generated which will cause the #" to %ump to the vector location 001B < # must be initialiBed before going to the main program because the default value of # is 0A <. &his is also the address of register !A If any register Ban5 switching is done, it can overwrite some useful register contents If (&1 :(nable &imer Interrupt 1 bit; is set in I( register, it will not enable the timer interrupt In addition, it is necessary to set (, bit in I(

+ode 6
upports the 9.bit Auto Re-o,d oper,tion &<x holds the reload value and &>x is the timer itself &>x starts counting up, when &>x reaches 2// and is subseDuently incremented, instead of resetting to 0, it will be reset to the value stored in &<x &ime *elay between overflows612 C 2/3. &<x8reDuency

ame for &imer 1 and &imer 0 &imer logic is same as that of mode 0 or 1 "onsider &imer 1 in mode 2 &imer register is configured as an 9.bit counter &>1 )verflow from &>1 sets the flag &81 and loads &>1 with contents of &<1 &he software can preload &<1

(C,-#>(: InitialiBe program for &0 in mode 2 +OV T+O=B <//// //0/" :>oad &-)* for &0 in mode 2; +OV T&/B <55 & :>oad &<0 with preset value to be reloaded; +OV TL/B <55 & : tart count 6 preset value; SET" TR/ : tart timer 0; S*+P D &he program must load &-)* and then auto reload value must be written in the timer higher byte &he starting count will also be the same as that of the reload value It is necessary to load the timer high byte with auto reload value, otherwise the timer after each overflow will start from 00 < which causes error in timings or delays generated using this timer -ode 2 is generally used for baud rate generation for serial port operation or where a constant freDuency sDuare wave is needed &he freDuency or the baud rate can be controlled using the preloaded value in &<x register -aximum delay generated using -ode 2 will be corresponding to the ,uto !eload value of 00 < &hus at 12-<B cloc5, it will generate a maximum delay of 2/3Fs delay (C-,#>(: 4,# to generate a 2G<B :0./m period; sDuare wave on #in 1 of #ort 1 &he reload count will be corresponding to 0.2/ms ,t 12 -<B this will be eDual to 03 <

+OV SPB <54& :initialiBe the #; +OV T+O=B //// //0/ " :&0 in mode 2 H auto reload mode; +OV T&/B </3& (#reload value for 25<B sDuare wave) +OV TL/B </3& (starting value in timer register &>0) SET" TR/ ( tart timer 0) LOOP% *" TF/B CO+PL+NT S*+P LOOP CO+PL+NT% CPL P01/ (&oggle bit #1.0) S*+P LOOP (C-,#>(: 4,# to generate a 2G<B :0./m period; sDuare wave on #in 1 of #ort 1 (usin' ti9er interrupt) &imer 0 interrupt has been enabled at the time of starting the timer Ti9er / is initialiBed in mode 2 or auto reload mode T&/ ,nd TL/ both are initialiBed to count 03 < corresponding to 25<B freDuency &he main program is over when &0 is started I-# J instruction can be replaced by >,B(> : I-# >,B(> #!)=!,ORC //// & A*+P STRT :-ain program is at &!&; ORC ///" & A*+P INTETF/ :I ! is at I+&K&80; STRT% +OV SPB <54& :InitialiBe #; SET" ET/ SET" EA +OV T+O=B //// //0/ " :&imer 0 in mode 2 auto reload; +OV T&/B </3& :#reload value for 25<B sDuare wave; +OV TL/B </3& : tarting value in timer register &>0; SET" TR/ : tart timer 0; S*+P D INTETF/% CPL P01/ RETI (,fter its execution, "#$ will again be in an infinite loop) EN= &imer 0 when started is not made off or on afterwards due to auto reload feature

+ode 5
&imer 0 bytes H &<0 and &>0 are used as two 9.bit separate timers H &>0 and &<0 with overflow flags &80 and &81 o, it is also called Sp-it Ti9er +ode

&<0 is loc5ed into timer operation and counts the machine cycles )n overflow it sets &81 &>0 can also be configured and controlled by using C?, =ate, &!0, I+&0 and &80 &!1 controls the operation of &<0 timer &hen how to control timer 1 LL &imer 1 is used differently for any application that does not reDuire the interrupt operation li5e for generating the Baud rate for serial port operation 4hen &imer 0 is in mode 1, its operation is controlled by switching it out or into its mode 1 using &-)* setting &hus -ode 1 acts li5e if it has 1 timer / counters (C,-#>(: =enerate sDuare waves at pins #1.0 #1.2 #1.1 with different freDuencies >et the operating freDuency is 12-<B ,t 12-<B, the timer.cloc5ing period is 1Fs &imer registers &<0 and &>0 are initially loaded with counts so that their overflows define the on time or off time of the sDuare wave and according to that the particular pin status is complemented #!)=!,-: &imer 0 in mode 1 &his program generates 25<B on pin #1.0, 2./5<B on pin #1.2 and 2/<B on pin #1.1 $se of 1 timers : two 9.bit timers H &<0 and &>0 and one 13.bit timer 1; are supported by this mode ORC //// & A*+P STRT ORC ///" & A*+P INTET/ETF/ ORC //0" & A*+P INTET0ETF0 (I ! addess for &imer &>0 interrupt) STRT% +OV T+O=B <//// //00 " (t)o !78it ti9ers) +OV T&/B <53= & +OV TL/B </3= & (>oad timer registers) +OV T&0B <// &

+OV TL0B <// & SET" ET/ ((nable interrupt for &>0) SET" ET0 ((nable interrupt for &<0) SET" EA ((nable ,ll) SET" TR/ ( tart &>0 timer) SET" TR0 ( tart &<0 timer) +OV AB T+O= ANL AB </F & (&imer 0 mode is not affected) ORL AB <//00 //// " ( et &-)* timer 1 in mode 1) +OV T+O=B A ( tart timer 1) (Ti9er 0 )i-- neit(er 'ener,te ,n# interrupt nor set ,n# A-,') (Ti9er 0 (,s st,rted Fust 8# its s)itc(in' into 9ode 5) LOOP% C*NE TL0B </6/ &B A&EA= (&est if &>1 is 20 <, if not, wait) C*NE T&0B </4E &B A&EA= (&est if &<1 is also 2( <, if not, wait) (No) ti9er 0 o@erA-o) (,s occurred) +OV TL0B <//& (>oad count) +OV T&0B <//& (>oad high byte of timer 1) CPL P015 (&oggle pin #1.1 at /0<B) A&EA=% S*+P LOOP INTET/ETF/% CLR EA (*isable all interrupts) CPL P01/ (&oggle pin #1.0 at 25<B) +OV TL/B </3& (>oad count for 2/0Fs in &>0) SET" EA ((nable all interrupts) RETI INTET0ETF0% CLR EA CPL P016 (&oggle pin #1.2 at 2./ 5<B) +OV T&/B <53= ("ount for 200 Fs in &<0) SET" EA ((nable all interrupts) RETI EN= &imer 1 is loaded with 0000< and after starting &imer 1, its contents are tested for being eDual to the count value in the software &he moment timer contents become eDual to the calculated count, the program complements pin #1.1 status In timer mode 1, timer 1 is 13.bit timer and &<0, &>0 are 9.bit timers

Ti9er Count c,-cu-,tions%

Frequency of square a!e ("#$)

%0&1 pin 'ere a!efor( s'ould appear

#1.0 #1.1 #1.1

)i(er

)on * )off in +s (equal to t'e nu(ber of ti(er cloc"s at 12M#$ frequency)

2/0 200 20,000

)i(er count and test condition

2 2./ 2/ <B

&>0 &<0 &imer 1

>oad 03< and test for overflow >oad 19< of /3* and test for overflow >oad timer 1 with 0000 < and test for timer 1 count to be eDual to 2(20 < :20,000 *;

Seri,- Co99unic,tion
$sed for digital communication ,*',+&,=(: >ess number of wires reDuired as compared to parallel communication 90/1 supports full duplex serial port :it can simultaneously transmit :&C*; and receive :!C*; a byte ; 90/1 serial communication is supported by ! 212 tandard :! 6 !ecommended tandard; Baud !ate : !eciprocal of the time to send 1 bit Baud !ate need not always eDual to number of bits per second because each byte is preceded by a start bit and followed by one stop bit to synchroniBe the serial receivers *ata byte is transmitted with > B first 8or error chec5ing purpose #arity Bit can also be added %ust prior to the stop bit -echanism: 1. *ata byte in parallel is converted into serial data stream 2. erial data frame is sent over the line along with start, stop and parity bits &here are 2 modes of serial data transmission 8! called B$8 is used for transmission and reception &he data to be transmitted must be transferred to B$8 &his B$8 address is referred ,nother 8! called ")+ controls the serial communication Bits -0 and -1 in ")+ define serial port mode -2 enables the multi processor communication in modes 2 and 1 &ransmission is initiated by the execution of any instruction that uses B$8 as destination

SCON1 2 S+/

SCON1 SCON1 3 5 S+0 S+6

SCON1 4 REN

SCON1 5 T"!

SCON1 6 R"!

SCON1 0 TI

SCON1 / RI

,it Address
M8 < M( < M* < M" < MB < M, < MM < M9 <

-C./ ,it
-0 -1 -2 !(+ &B9 !B9 &I !I

0escription
erial "ommunication -ode

In modes 2 and 1, if set, this will enable microprocessor communication (nables serial reception Mth data bit that is transmitted in modes 2 and 1 Mth data bit that is received in modes 2 and 1. It is not used in mode 0. In mode 1, if -260, !B9 is the stop bit that is received &ransmit interrupt flag, set by hardware, must be cleared by software !eceive interrupt flag, set by hardware, must be cleared by software

-M0
0 0 1 1

-M1
0 1 0 1

Mode
0 1 2 1

0escription
9.bit shift register mode 9.bit $,!& M.bit $,!& M.bit $,!&

,aud 1ate
fosc/12 'ariable :set by timer 1; fosc / 13 or fosc/12 'ariable :set by timer 1;

+ode /
"alled S(iAt Re'ister +ode )nly !C* pin can be used to transmit or receive data &C* pin outputs the shift cloc5 only (ight data bits are transmitted or received Baud !ate is fixed and is determined by fosc :fosc/12; #!)=!,-: erial transmission mode 0 ORC //// & (#rogram starts at 0000 <) +OV SCONB <//// //// " (-ode 0) :+ow write the data byte to be transmitted in B$8; +OV S"UFB <44& :&ransmit 0100 0100 binary; :,fter transmission, &I 8lag in ")+ will be set by hardware. &his can be tested for assuring the transmission operation; &ERE% *N" TIB &ERE :4ait till all 9 bits are transmitted. !emember &I 8lag must be cleared; CLR TI

+ode 0
10 Bits are transmitted through &C* pin or !C* pin tart Bit :0; @ 9 *ata Bits @ top Bit :1;

)n receiving, the stop bit goes into !B9 in ")+ Baud !ate is variable and is determined by timer 1 overflow rate, so &imer 1 must be initialiBed Baud !ate 6 2 -)*12 C :&imer 1 )verflow !ate; #!)=!,-: InitialiBe serial port in mode 1 ORC //// & +OV SPB <50 & : -)* is 0 after reset; +OV SCONB </0// //// B : erial port in mode 1; +OV T+O=B <//0/ //// " :&imer 1 in auto reload mode; +OV T&0B <65/ = :Baud !ate 6 1200 at 12 -<B; SET" TR0 : tart &imer; +OV S"UF1 <53 & *N" TIB D :4ait till the transmission is over; CLR TI :!eset bit &I after transmission;

If timer 1 is configured in auto reload mode :mode 2; with reload value in &<1, after each overflow contents of &<1 will be loaded into &>1 &his is In this mode, &-)* high nibble will be 0010 B ,t 12 -<B ) " freDuency, the timer cloc5ing time is 1Fs +ow, Baud rate formula is simplified to Baud !ate6 2 -)*12C:)scillator 8reDuency;:12C:2/3. &<1;; E'1 IA &<1 6 210*, -)* 6 0, then Baud !ate at 12 -<B 6 1201 baud. &o get exactly 1200 Baud, osc freDuency must be 11.0/M -<B #!)=!,-: !eceive a serial byte through !C* &o receive a byte in mode 1, !I bit in ")+ is tested for 1 and !(+ bit in ")+ must be 1 -)' ")+, E0101 0000 B :serial port -ode 1 and !(+ bit is set; : -)* is 0 after reset; -)' &-)*, E0010 0000 B :&imer 1 in mode 2; -)' &<1, E210* :Baud !ate 1.2 G at 12 -<B; (&B &!1 : tart &imer 1; ">! !I :!eady to receive; I+B !I , J :4ait till a byte is received in B$8; -)' ,, B$8 :=et the received byte in accumulator;

+ode 6
11 Bits are transmitted with a low start bit , then 9 data bits then Mth bit and a stop bit :1;

Mth bit is programmable as &B9 in ")+ It may be used to give parity of data byte )n reception, this Mth data bit goes into !B9 in ")+ Baud !ate62 -)*32C:)scillator 8reDuency; (C,-#>(: InitialiBe serial port in mode 2 ,t 12-<B, if -* bit is 1, then baud rate will be 1A/,000 ">! &I -)' ")+, E 1000 0000 B : erial #ort mode 2; (&B -)* : -)*61 and baud rate 61A/G at 12 -<B; -)' B$8, E22< I+B, J :4ait till transmission is over; ">! &I

+ode 5
11 Bits are transmitted ame as mode 2 except that baud rate is defined by timer 1 overflow rate Baud rate calculations same as mode 1

+u-tiprocessor Co99unic,tion
etting -2 bit in ")+ register enables to communicate one 90/1 with other 90/1 controllers &his communication is supported in mode 2 and 1 only M Bits are transmitted or received Mth bit goes to !B9 &ransmitting #rocessor 6 -aster and all other 6 slaves Mth bit 6 1 when address byte is sent and Mth bit 6 0 when data is sent