Flash ADC

Fall 2009

S. Hoyos-ELEN-610

Flash ADC Architecture

Vi
VFS 7 7 6 6 5

VFS

Vi

Strobe fs

Reference ladder consists of 2N equal size resistors Input is compared to 2N-1 reference voltages. Massive parallelism Fastest ADC architecture Latency = 1T = 1/fs Throughput = fs Complexity = 2N

Encoder
5

Dout

2 1 0

Do

2 -1 comparators

Fall 2009

S. Hoyos-ELEN-610

Thermometer Code
VFS Vi Strobe fs 0 1

Thermometer code

b2

b1

b0

1 0

111 110

1 1

1 1

010 001 000

2 -1 comparators

1-of-n code
ROM encoder

Fall 2009

S. Hoyos-ELEN-610

A 10-bit Flash ADC

1mV

VDD = 1.8V
10-bit VFS = 1V DNL < 0.5 LSB 0.5mV = 3-5 1023 comparators 1 LSB = 1mV Vos < 0.5 LSB = 0.1-0.2mV

1V

2N-1 very large comparators Large area, large power consumption Very sensitive design Limited to resolutions of 4-8 bits

Fall 2009

S. Hoyos-ELEN-610

Max. Offset vs. Resolution

128

DNL < 0.5 LSB

32

Vos, max [mV]

8 2 0.5 4 VFS = 1V

VFS = 2V

Large VFS relaxes offset tolerance Small VFS benefits conversion speed (settling, linearity)

6 8 N [bits]

10

Fall 2009

S. Hoyos-ELEN-610

Metastability
Vi 0 x 1 0 0 100 011 1 1 1

Logic levels can be regenerated by digital gates.

Fall 2009 S. Hoyos-ELEN-610 6

CI and CF in Latches
M5 Vo+ CL M7 M6 VoCL M8 CM jump Vo+ Vo

Cgs

Cgd

M9

Charge injection and clock feedthrough introduce CM jump in Vo+ and Vo-. Dynamic latches are more susceptible to CI and CF errors.
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ADC Input Capacitance

A VT 0 VT 0 WL
2 2

Cg 10 fF / m 2

N = 6 bits

63 comparators

VFS = 1V
= LSB/4

1 LSB = 16mV
= 4mV

N (bits) 6 8 10

# of comp. 63 255 1023

Cin (pF) 3.9 250 ??!

AVT0 = 10mVm L = 0.24m, W = 26m

Small Vos leads to large device sizes, hence large area and power. Large comparator leads to large input capacitance, difficult to drive and difficult to maintain bandwidth.
Fall 2009 S. Hoyos-ELEN-610 8

Distributed Parallel Sampling

Vi
VFS 7 7 6 6

VFS

Vi

Strobe fs

SHA-less
Signal and clock propagation delay
Encoder

2 1 0

Dout

2N-1 PAs plus latches must be matched. Synchronized strobe signal is critical.

Do

2N-1 PA + Latch

Going parallel is fast, but also give rise to inherent problems

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Preamp Input Common Mode

PA 1 PA j PA j+1

Vi

S1

VR VR
1 j

Sj

VR1

VRj

Input CM difference creates systematic mismatch (offset, gain, Cin, tracking BW, CMRR) among preamps.
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Sampling Aperture Error

M3 M4 M5 M6

Cgd1 M1 M2

Cgd2

VR V o+ Vo-

high low
M8

Mode Track Regen.

Vin

RS

Cgs1

Cgs2 CS M7

M9

Preamp delay and Vth of sampling switch (M9) are both signal-dependent signal-dependent sampling point (aperture error) A major challenge of distributing clock signals across 2N-1 comparators

in flash ADC with minimum clock skew (routing, Vth mismatch of M9)
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Nonlinear Input Capacitance

RS Vout Vin Cin(Vout)

Vin, Vout

Signal-dependent input bandwidth (1/RSCin) introduces distortion.

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Input Signal Feedthrough

Vi

M3

M4

M1

M2 Cgs2

VRj

Vin

RS Cgs1

Feedthrough of Vin to the reference ladder through the serial connection of Cgs1 and Cgs2 disturbs the reference voltages.

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Fully-Differential Architecture
VR+ VRVi+ ViPA Latch

VFS doubled
3-dB gain in SNR Better CMRR Noise immunity
Encoder
Dout

Input feedthrough cancelled Cin nonlinearity partially removed Effect of Vcmi diff. mitigated

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Fully-Differential Comparator
M5 M6

M7 M1 M2 M3 M4

M8

Vo+ Vi-

Vi+

VR+ VR-

M9

Vo-

Fully-diff. PA

Latch

Double-balanced, fully-differential preamp Switches (M7, M8) added to stop input propagation during regeneration Active pull-up PMOS added to the latch
Fall 2009 S. Hoyos-ELEN-610 15

AC-Coupled Preamp
Vi VR X PA C Latch

PA input node X sees constant bias throughout all preamps. Autozeroing eliminates PA offsets (stored in C).

Ref: A. G. F. Dingwall, Monolithic expandable 6 bit 20 MHz CMOS/SOS A/D converter, IEEE Journal of Solid-State Circuits, vol. 14, pp. 926-932, issue 6, 1979.

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Bubbles (Sparkles)
Vi

0 1 0 1

0 1 0

100 011 010

Static and dynamic comparator errors cause bubbles in thermometer code.

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Bubbles (Sparkles)
Vi

Vj+1

0 VR
j+1

VRj+1

1
j+1
j

1 LSB Vj VRj

VR

0
j

t t

Comparator offset

Timing error

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Bubble-Tolerant Boundary Detector

Vi

0 1 0 1 1 1 1 0 1

3-input NAND Detect 011 instead of 01 only Single bubble correction Biased correction

Fall 2009

Ref: J. G. Peterson, A monolithic video A/D converter, IEEE Journal of Solid-State Circuits, vol. 14, pp. 932-937, issue 6, 1979.

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Built-In Bias
A 0 0 0 0 1 0 1 1 1 1 B 0 0 0 0 0 1 1 0 1 1 C 0 0 1 0 0 1 1 1 1 1 D 0 0 0 1 1 0 0 1 1 1

1 2 3

011 001 Case Det. Det. A B Fail

C D

Fail

Fail Fail

Inspecting more neighboring comparator outputs improves performance.

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Majority Voting
C j C j 1C j C j C j 1 C j 1C j 1
*

A 0 0 0 0 1 0 1 1 1 1
0 0 0 0 0 1 1 1 1 1

B 0 0 0 0 0 1 1 0 1 1
0 0 0 0 0 1 1 1 1 1

C 0 0 1 0 0 1 1 1 1 1
0 0 0 0 0 1 1 1 1 1

D 0 0 0 1 1 0 0 1 1 1
0 0 0 1 1 0 0 1 1 1
Case A B C D 011 Det. Fail Fail Majority voting Fail

1 2 3

Ref: C. W. Mangelsdorf, A 400-MHz input flash converter with error correction, IEEE Journal of Solid-State Circuits, vol. 25, pp. 184-191, issue 1, 1990.

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Gray Encoding
G1 T1T3 T5 T7 G2 T2 T6 G3 T4
Only one transition b/t adjacent codes
Thermometer Gray Binary

0 1 1 1 1 1 1 1

0 0 1 1 1 1 1 1

0 0 0 1 1 1 1 1

0 0 0 0 1 1 1 1

0 0 0 0 0 1 1 1

0 0 0 0 0 0 1 1

0 0 0 0 0 0 0 1

0 0 0 0 1 1 1 1

0 0 1 1 1 1 0 0

0 1 1 0 0 1 1 0

0 0 0 0 1 1 1 1

0 0 1 1 0 0 1 1

0 1 0 1 0 1 0 1

T1 T2 T3 T4 T5 T6 T7

G3 G2 G1

B3 B2 B1

One comparator output is ONLY used once No branching!

Gray encoding fails benignly in the presence of bubbles. Codes are also robust over metastability errors.

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