Setup for Measuring the Derating of SMD Components under ESD Stress

Franz Streibl #1 , Stefan Tenbohlen #2 , J org Hartmann 3 , Eric Dudenhoeffer $4

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Universit at Stuttgart, Institute of Power Transmission and High Voltage Technology (IEH) Stuttgart, Germany
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stefan.tenbohlen@ieh.uni-stuttgart.de 1 franz.streibl@ieh.uni-stuttgart.de

Robert Bosch GmbH Stuttgart, Germany

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Teseq AG Luterbach, Switzerland

AbstractThis paper presents a mechanical setup for measuring the derating of surface mounted devices. The derating is caused here by single or multiple electrostatic discharges from common simulator equipment. In the eld, electrostatic discharges potentially damage or destroy the input circuitry of electronic control units. Often only secondary effects such as system malfunctions or reduced electromagnetic compatibility indicate a derating of the input circuitry from previous electrostatic discharges. Within the setup presented here, the device under test is placed into a two-port coaxially interfaced container t for all common electrical characterisation methods, such as impedance and network analysis. The design features standard Pellegrini ange dimensions and is therefore suitable for manual or semi-automatic test implementations within already existing electrostatic test setups.

I. I NTRODUCTION Measuring the derating of surface mounted devices (SMD) under electrostatic discharge (ESD) stress is becoming inevitable as the SMD package sizes and the components volume become smaller and thereby more vulnerable towards high voltage or high current stresses. Both, the voltage and current stress can be aspects of an ESD. In the eld, however, due to the increased application of new material combinations within all types of apparatus the electrostatic voltages building up under certain conditions are increasing. And with them the potential peak currents in case of a discharge. These two trends, being mainly driven by cost optimisation, lead to the need for a better understanding of component derating behaviour in case of ESD. Although ESD events are not necessarily damaging or destroying the respective component, they still may cause a drift in characteristics leading to secondary effects or can cause a determined breaking point. Later, in the components life an electrical overstress condition occurs and, given the ESD predamaging, triggers a complete failure of the component. Among the mentioned secondary effects can be counted, for example, a changed, i.e. reduced electromagnetic compatibility

Fig. 1. Circuit diagram for the DUT container, a small metal phial with two coaxial connectors interfacing to the different setups. During ESD stress, the phial is plugged into a grounded ange adapting to Pellegrini target dimensions.

(EMC) or a drift in biasing for analog circuitry. However, most times ESD derating is not apparent as such and not at all easy to nd since it usually rst shows up indirectly, e.g. as system or even only software malfunctions. In order to enable development engineers to choose the right component for their application based on objective component parameters rather than on expensive try-and-error experience, a common setup for determining component derating experimentally is proposed within this paper. II. DUT C ONTAINER The object of all measurements conducted is the device under test (DUT). Here, the DUT is a small SMD packaged component having, for example, the size of 1.6 x 0.8 x 0.6 mm (for a relatively big 0603 package). Devices with such tiny physical dimensions are not easy to handle manually without potentially exposing the DUT to human discharges and thereby interfering with a xed and pre-dened ESD stressing scheme.

Fig. 3. Different congurations are enabled by the DUT container design. An ESD stressing step is followed by different types of device characterisations in order to quantise the derating taken place during the stressing. Fig. 2. The picture shows a phial made of brass equipped with two SMAtype coaxial connectors. The squares on the paper have an edge length of 5 mm.

Furthermore, the contacting of the DUT to various xtures of the different stress and measurement equipment involved showed agreeable, yet only limited reproducibility. Then, such SMD components already have a certain stray in parameters due to their manufacturing process. Initial derating effects have a similar parametric range as these part variances, as well as variations in the contacting, which is why it is important not to mistake the one for the other. Apart from that, some xtures need the component to be soldered in before and soldered out after the experiment, effectively causing thermal stress and subsequent derating effects that are unwanted in an ESD-only stress scheme. Other xtures are exible in that they can be used for the whole variety of SMD packages, but they do not feature a low-inductance design and are not easy to shield. Electrical shielding during the ESD stress mainly was added to the specications in order to limit the investigations on conducted impulses to begin with. Last not least, also trivial occasional loss of a DUT, given its tiny size, caused the new development. In summary, the physical dimensions of the DUT, manual handling experience and reproducibility considerations lead to an axially symmetrical design featuring two coaxial ports on each end. The DUT is placed inside the metal phial and remains contacted during the whole procedure (Fig.1). Replacing the DUT to various types of xtures is not necessary any more. Furthermore, soldering the DUT to the xture is not required. The construction prevents the DUT terminals being touched by the handling person, since the centre pin of the coaxial connectors is pulled back with respect to the outer threaded contact dimensions. The cylindrical outline of the DUT container is then adapted to a Pellegrini ange during ESD stress, as it is commonly used to integrate ESD targets for impulse verication within coupling planes in ESD labs. The physical dimensions of the ange are dened in the appendix of [1]. Fig. 2 shows a DUT phial made of brass, featuring two

SMA-type coaxial connectors. With an inner cavity diameter of 7 mm and a length of approximately 25 mm from one coaxial centre pin to the other the design provides enough bandwidth for the impulses applied, enabling realistic worstcase stress conditions for the DUT. III. S ETUP F LEXIBILITY The design provides for a high degree of exibility enabling custom mechanical enhancements and individual test procedures while sticking to standard form factors and ESD design rules. For ESD stressing the DUT phial is integrated into the already mentioned Pellegrini ange. Standard ESD impulses according to the human body model (HBM) are generated by ESD simulators and mimic discharges originating from humans in terms of voltage, current and impulse shape. These discharges are considered responsible for ESD derating during the packaging and handling procedures, such as assembly, repair and maintenance of electronic control units through human or female android personnel. The discharges mentioned are commonly applied as contact or air discharges to the DUT. Here, however, only contact discharges are considered, meaning the ESD simulator is contacted with one of the DUT terminals before the actual discharge event. As an example for the beforementioned customisability an adaptor for the ESD simulator gub tip can be considered. The problem was to provide the sharp cone end of the ESD simulator with a landing area. The solution is a small disc which is used to adapt the coaxial port of the phial to the ESD simulator, as shown in Fig. 4. After ESD stressing, the derating can be measured with different equipment. The coaxial ports of the DUT phial enables any network analyser or impedance measuring device to be used for this purpose. In a manual test procedure the phial therefore has to be taken out of the Pellegrini ange before being connected and measured with a network analyser, for example. Fig. 3 shows the different schematics for stressing and analysis.

Fig. 4. Semi-automatic test setup showing the ESD gun tip in the upper part and the DUT phial integrated into a vertical copper plane. A landing disc for the gun tip is attached to the upper coaxial port. The lower port (not shown) is shorted to ground during the ESD stress.

Fig. 5. Test setup block diagram showing the DUT, ESD gun and an impedance analyser. The whole setup is integrated into a climatic chamber to control the ambient parameters during a sequence. The DUT is moving on a linear unit between ESD stressing and derating measurement during the test sequence.

Within an example test setup the usability of the approach presented could be proved.

IV. E XAMPLE S ETUP A semi-automatic test setup was implemented consisting of the following parts (Fig. 5): DUT phial inserted into a vertical copper plane ESD simulator gun Impedance analyser Climate chamber Linear unit Various control units The DUT is automatically stressed and measured for derating. For actual stressing, the device under test is positioned under the ESD gun (Fig. 6) and contacted by it. Then, an ESD impulse is applied by the ESD simulator gun and the DUT is moved over to the measuring contact. There, the impedance analyser contacts the DUT and measures the electrical characteristics of the device. The process repeats until the ESD stressing procedure is nished. The setup is only semi-automatic, since user intervention is still necessary for replacing the DUT. However, this is minimising effects such as contact variations through terminal staining or similar and leads to better reliability of the measurement results. V. C ONCLUSION This paper proposes a setup for measuring the derating of SMD components under ESD stress. Given the many open questions regarding the derating of standard electrical components such as resistors, capacitors and inductors, a common test setup should be used for conducting experimental investigations. The setup presented features a versatile DUT container with standard ports for connecting both, ESD impulse sources and common analysis equipment, while providing for high reproducibility of the measurements.

Fig. 6. The picture shows the beforementioned phial with the DUT inside (lower right) positioned under the ESD simulator gun (upper right) inside the climate chamber. The ESD simulator gun is attached to the z-axis of the linear unit, whereas the DUT xture is attached to the x-axis.

R EFERENCES
[1] EN 61000-4-2, Electromagnetic compatibility - Part 4-2: Testing and measurement techniques - Electrostatic discharge immunity test, 2001. [2] ISO 10605, Road vehicles - Test methods for electrical disturbances from electrostatic discharge, 2001. [3] D. Pommerenke, Transiente Felder der Elektrostatischen Entladung (ESD), Dissertation, VDI-Verlag, 1995. [4] K. Gl oser, Alternative Methoden des Uberspannungsund ESDSchutzes, Dissertation, TU-Kaiserslautern, 2005.