COMPUTER ORGANIZATION AND ARCHITECTURE UNIT I BASIC STRUCTURE OF COMPUTERS PART-A:

1. Give an example of zero-address, one-address, two-address and three-address instructions. 2. What is the purpose of guard bits in floating point operations? 3. What is a bus? What are the different buses in a CPU? 4. What are the four basic types of operations that need to be supported by an instructor set? 5. Distinguish between CISC and RISC. 6. What is pipelining? 7. Define super scalar execution. 8. Define clock and clock cycle. 9. What are the various commonly used flags? 10. What is the difference between indirect mode and index mode? 11. What is relative addressing mode? When it is used?

PART-B:

1. (i)Explain how the processor is interfaced with the memory with a neat block diagram and explain how they Communicate. (ii)Explain about the various functional units. 2. Explain instruction set and instruction sequencing. 3. (i) Discuss about the ALU design and narrate its operations. (ii) Explain in detail about the single bus structure. 4. Classify addressing modes and explain each type with examples. 5. (i) With necessary diagram explain the concept of indexing and arrays. (ii) Discuss in detail about the performance of a computer. 6. (i)Explain how a processor works with simple instruction sets.(RISC). (ii) How can you improve the performance of a processor with complex instruction sets. (CISC). (8) (10) (6) (16) (6) (10) (16) 8) (8) (8)

UNIT -2 BASIC PROCESSING UNIT PART-A: 1. State the differences between hardwired and micro programmed control unit. 2. What are the operations to be followed to execute an instruction? 3. Draw the block diagram of a control unit organization. 4. What is multiphase clocking? 5. What is hardwired control? 6. How can you determine the control signals in a hardwired control? 7. Define microinstructions. 8. What is the use of wide branch addressing? 9. What are the disadvantages of micro program sequencing? 10. Define micro program and microcode. 11. What are the advantages of nano programming?

PART-B:

1. With neat diagram illustrate the operations involved to execute a given instruction. 2. Explain the single bus and three bus organization of the data path inside a processor with necessary diagrams. 3. Explain the various design methods of hardwired control unit. 4. With neat diagram explain the basic organization of a micro-programmed control unit with a typical set of micro instructions. 5. (i) How can you structure Microinstructions? Explain with the help of an example. (ii) How can you implement branching of micro instructions with the help of Microinstruction sequencing? 6. (i) Explain the objectives and advantages of nanoprogramming. (ii) Narrate the sequence of events for an unconditional branch instruction.

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UNIT3 PIPELINING PART A: 1. What is pipelining and what are the advantages of pipelining? 2. What is data hazard in pipelining? 3. What are the four steps of a pipelined processor? 4. Define instruction hazard. 5. What is structural hazard? 6. What is the function of a dispatch unit? 7. What is delayed branching? 8. Define branch prediction and mention its types. 9. Draw the state machine representation of a 2-state algorithm. 10. Expand the 4 states of a branch instruction. 11. Define instruction throughput. PART-B: 1. (i) How can you solve the memory access problem with the help of Cache memory. (ii)Design a 4-stage pipeline and explain how to improve the performance of a pipeline. 2. What is data hazard? Explain the methods for dealing with data hazards. 3. Highlight the effect and solution of instruction hazards. 4. With the help of state machine representation of branch prediction algorithms, Explain the various hazards introduced by conditional branch instruction with its types. 5. With necessary example and diagram explain different hazards that are handled by pipelining techniques. 6. (i) Highlight the Key features of various addressing modes and the condition code flags for pipelined execution. (ii) Explain the organization of data path for pipelined execution with the help of interstage buffers. (8) (8) (16) (16) (8) (8) (16) (16)

UNIT-4 MEMORY SYSTEM PART-A: 1. What is the function of a TLB? 2. Define locality of reference. What are its types?

3. List the differences between static RAM and dynamic RAM.

4. What is virtual memory? How it is implemented? 5. Define cache memory. 6. How the data is transferred using fast page mode feature? 7. What are the 3 types of packets? Define their functions. 8. What is the concept of write-back protocol? 9. What is a mapping function? State its types. 10. What is the need for memory hierarchy? Draw the memory hierarchy of a computer system. PART-B: 1. (i) Explain in detail about the internal organization of memory chips with the help of Static memories. (ii) Give a detailed account on Memory hierarchy. 2. (i) Discuss in detail about Dynamic RAMs. (ii)Distinguish between static and dynamic memory systems. 3. (i) Discuss in detail about the various ROM technologies with its application areas. (ii) Explain the technique involved in Set associative mapping of cache memory. 4. What is the need for cache memory? Explain the various mapping techniques associated with cache memories. 5. Explain how the virtual address is converted into real address in a paged virtual memory system. 6. Describe the working principle of a typical magnetic disk. (16) (16) (16) (8) (8) (12) (4) (8) (8)

UNIT 5 I/O ORGANIZATION PART A:

1. Why are interrupts provided in any processor? 2. How does bus arbitration typically work? 3. What is DMA operation? State its advantages. 4. What is the necessity of an interface? 5. Why do we need DMA? 6. What is the difference between subroutine and interrupt service routine? 7. List out the sequence of events involved in handling an interrupt request.

8. How the devices are connected in daisy chain? Represent the diagram. 9. What is bus master and slave master? 10. What are the objectives of an USB? 11. List out the various interface standards.

PART B:

1. Explain in detail about interrupt handling. 2. Draw the typical block diagram of a DMA controller and explain how it is used for direct data transfer between memory and peripherals. .

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3. (i) Explain Handshake protocol. Depict clearly how it controls data transfer during an input operation. (ii) Explain the data transfer over a synchronous bus. 4. (i) Explain how a read operation can be performed with data transfer signals in a PCI bus. (ii) Narrate the sequence of events caused by a SCSI controller. 5. Explain in detail about interface standards used in the design of a processor bus. 6. Discuss in detail about the objectives and technical details of USB. 10) (6) (8) (8) (16) (16)