CMOS VLSI IC Design

A decent understanding of all tasks required to design and fabricate a chip takes years of experience

Commonly used keywords

INTEGRATED CIRC IT !IC" #any transistors on one chip $ER% &ARGE 'CA&E INTEGRATI(N !$&'I" )ery #any transistors !* +,,,, gates" on one chip C(-.&E-ENTAR% -ETA& (/IDE 'E-IC(ND CT(R !C-('" TEC0N(&(G% cheap1 high integration density1 lo2 po2er
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Integrated Circuits

The Silicon Wafer

Packaging the Chip

Common Packages

Impact of ICs industry

Integrated Circuits enabled todays way of life +,+3 transistors #anufactured in 4,,5 !+,, #illion for e)ery hu#an on the planet"

Moore's Law

In +675 Gordon -oore predicted that as a result of continuous #iniaturi8ation transistor count 2ould double e)ery +3 #onths 95: co#pound annual gro2th rate o)er ;9 years !No other technology has gro2n so fast so long" Transistors ha)e beco#e< = s#aller = faster = consu#e less po2er = cheaper to #anufacture

Challenges
The greatest challenge in #odern $&'I design is #anaging system complexity 'trategies used to cope 2ith Co#plexity Abstraction 'tructured Design Approach Design >lo2
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Design Abstractions

RTL Abstraction RTL

"ste# Level Register Transfer Level (HDL)

Gate Level Transistor Level 1970 1980

1990

2000+
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Examples of design abstractions (1)

A Module Level 0 1 % Truth Table $

Switch Level MSI Building Block

Gate Level Logic Level

Z = A S' + B S

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Examples of design abstractions (2)

M%S tran#i#tor# Level "egi#ter Tran#$er Level V !L

Structural Level V !L

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Structured Design
Hierarc&"
!ivide and &on'uer (aradig)

'o()larit" ?ell=defined interfaces allo2 #odules to be treated as black boxes Reg)larit" It #akes easier to reuse blocks 'tandard cell libraries are a )ery good exa#ple of #odularity and regularity

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IC Design Hierarchy

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Standard cells

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Simplified IC Design Flows

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Another Simplified IC Design Flow

Implementation: Translation !#erge all design files into a single netlist" De)ice #apping .@R Device Programming: Generation confA file Do2nload confA file into de)ice

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RTL code (Verilog)

assign cout = (a&b) | (a&c) | (b&c);

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Gate level netlist (Verilog)

module carry(input a, b, c, output cout) wire and and and or x, y, z; g1(x, a, g2(y, a, g3(z, b, g4(cout, b); c); c); x, y, z);
a b g. a c g/ b c , +

g* g0 cout

endmodule

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Transistor level netlist (Verilog)

module carry(input wire tranif1 tranif1 tranif1 tranif1 tranif1 tranif0 tranif0 tranif0 tranif0 tranif0 tranif1 tranif0 endmodule a, b, c, output cout) i1, i2, i3, i4, cn; n1(i1, 0, a); n2(i1, 0, b); n3(cn, i1, c); n4(i2, 0, b); n5(cn, i2, a); p1(i3, 1, a); p2(i3, 1, b); p3(cn, i3, c); p4(i4, 1, b); p5(cn, i4, a); n6(cout, 0, cn); p6(cout, 1, cn);

(c c

(. (/ i/

b a a b

(0 i0 (1 n1 i. n0

cn

(2 cout n2

n/ in- b n.

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SPICE netlist
.SUBC ! CARRY A C C!"# $%% &'% ('1 )1 A &'% &'% '(!* +,1" -,0.1." A%,0.3/ A*,0.5/ ('2 )1 &'% &'% '(!* +,1" -,0.1." A%,0.3/ A*,0.5/ ('3 C' C )1 &'% '(!* +,1" -,0.1." A%,0.5/ A*,0.5/ ('4 )2 &'% &'% '(!* +,1" -,0.1." A%,0.15/ A*,0.5/ ('5 C' A )2 &'% '(!* +,1" -,0.1." A%,0.5/ A*,0.15/ (/1 )3 A $%% $%% /(!* +,2" -,0.1." A%,0.6/ A*,1 / (/2 )3 $%% $%% /(!* +,2" -,0.1." A%,0.6/ A*,1/ (/3 C' C )3 $%% /(!* +,2" -,0.1." A%,1/ A*,1/ (/4 )4 $%% $%% /(!* +,2" -,0.1." A%,0.3/ A*,1/ (/5 C' A )4 $%% /(!* +,2" -,0.1." A%,1/ A*,0.3/ ('6 C!"# C' &'% &'% '(!* +,2" -,0.1." A%,1/ A*,1/ (/6 C!"# C' $%% $%% /(!* +,4" -,0.1." A%,2/ A*,2/ C)1 )1 &'% 200 C)3 )3 &'% 300 CA A &'% 400 C &'% 400 CC C &'% 200 CC' C' &'% 400 CC!"# C!"# &'% 200 ."#$S

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Types of ICs
ASS3 ASI& se

4ull5cu#to) Se)i5cu#to)
&ell Ba#ed Gate Arra+#

3rogra))able

&3L! and 43GA

Design 'tyle
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Standard Cells

Rows of standard cells with routing channels between them

Memory array
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Gate Arrays

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Field Programmable Gate Array

C!"#

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Internal Structure of a CLB

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Various on chip structures

Rando# logic Data paths Arrays Analog InputBoutput !IB("

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Example of random Logic

'ynthesi8ed -I.' controller

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Another example of random logic

'ynthesi8ed -I.'

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Example of data path

0and=Crafted -I.' datapath

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Example of Array

S"AM chi(

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Example of Analog structure

&harge 3u)( 3ha#e5Locked Loo(

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Example of I/O

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Bidirectional I/O PAD circuit

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Physical Design
>loorplanning and area esti#ation 'tandard Cell Cased &ayout
.lace and Route .arasitic Extraction .ost &ayout $erification 'lice .lanning .arasitic Extraction .ost &ayout $erification
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Data=path Cased &ayout

Floorplanning
Does the design fit the chip area budgeted D Esti#ates area of #aEor units and defines their relati)e place#ent Esti#ate 2ire lengths Esti#ate 2iring congestion

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Area Estimation
'o#e cell library )endor specify cell layout densities in FgatesB##4

Co#pare to another block you already designed or esti#ate fro# transistor counts Cudget roo# for large 2iring tracks
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Example of Layout

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CAD Tools

Designers rely increasingly on design auto#ation soft2are tools to seek producti)ity gains and to cope 2ith increased co#plexity $ypical Design %low
6 Design *ntr" 6 c&e#atic ca+t)re 6 Har(,are Descri+tion Lang)ages 6 Logic "nt&esis 6 -re la"o)t verification 6 .)nctional si#)lation 6 .or#al #et&o(s 6 Ti#ing Anal"sis 6 .loor+lanning 6 -lace#ent Physical 6 Ro)ting Design 6 */traction 6 -ost la"o)t verification
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!ogic Design

Verification
>abrication is slo2 @ expensi)e -('I' ,A7# #asks< G+,,,1 5 #onths 'tate of art #asks !+5,n#"< G+-1 + #onth Debugging chips is )ery hard &i#ited )isibility into operation .ro)e design is right before buildingH 'yste# si#ulation @ perfor#ance Assess#ent !CBCII" &ogic 'i#ulation B for#al )erification B 'TA Circuit si#ulation &ayout )sA sche#atic co#parison !&$'" Design @ electrical rule checks !DRC1 ERC" $erification is * 9,: of effort on #ost chips H
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Fabrication
Tapeout final layout >or#ats for #ask descriptions< CI> !acade#ia" and GD' II !industry" 71 31 +4J 2afers !bare 2afer costs G+,,,=G9,,," (pti#i8ed for throughput1 not latency !turnaround ti#es up to +, 2eeks H" Cut into indi)idual dice >abless se#iconductor co#panies -anufacturing Co#panies< T'-'1 -C1 IC41

>abrication

>abs cost billions of dollars and beco#e obsolete in a fe2 years

Testing
Test that chip operates as expected
Design errors -anufacturing errors %ields fro# 6,: to K +,: Depends on die si8e1 #aturity of process Test each part before shipping to custo#er

A single dust particle or 2afer defect kills a die

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Summary
Chip Design requires a funda#ental understanding of circuit and physical design This is true e)en if #any chip designers spend #uch of their ti#e specifying circuits 2ith 0D& and seldo# look at the actual transistors The best 2ay to learn $&'I design is by doing it H
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MOS Transistors (POS to be picky)

TRANS-ISTOR (=TRAN'>ER=RE'I'T(R" Four terminals: gate, source, drain, body (= bulk)

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Our first CMOS circuit

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