ALTERA FPGAs

K.Sivasankaran Assistant professor, VLSI Division, School of Electronics Engineering, Engineering VIT University,Vellore.

What is an FPGA?

Field Programmable Gate Array G t A Gate Array

Two-dimensional array of logic gates Traditionally connected with customized metal

Field Programmable Field programmability is achieved through switches (Transistors controlled by memory elements or fuses)

One FPGA can serve every customer

FPGA: re-programmable hardware

WHY FPGA?

FPGA chips handle dense logic and memory elements offering very high logic capacity

Uncommitted logic blocks are replicated in an FPGA with interconnects and I/O blocks

Complete integrated design environment (IDE) Easy to learn and use

CHARACTERISTICS OF AN FPGA

A matrix of p programmable g interconnect surrounds the basic logic g cells. Programmable input/output cells surround the core. Design turnaround is a few hours. hours

ADVANTAGES OF FPGA

A user can program an FPGA design in a few minutes, rather than weeks or months required for the production of mask-programmed parts. FPGAs need no custom mask. A low risk, , saving g thousands of dollars over mask programmed parts. Savings both in money and project delay FPGAs are useful for rapid prototyping and product development.

FPGA Architectures

Symmetrical Array Row-Based Sea of Gates Hierarchical PLD

FPGA - Generic Structure

FPGA building blocks:

Logic block Interconnection switches

I/O

Programmable g logic g blocks Implement combinatorial and sequential logic Programmable g interconnect Wires to connect inputs and outputs to logic blocks Programmable g I/O blocks Special logic blocks at the periphery of device for external connections

I I/O I/O

I I/O

Basic Internals of an FPGA

Logic Element Logic Element Logic Element

Logic Element

Logic Element

Logic Element

Logic g Element

Logic Element

Logic Element

Each logic element is programmed to p the to implement desired function Programmable Connections

EMBEDDING A CIRCUIT IN AN FPGA

All done by CAD system (e.g. Quartus)

Chop up circuit into little pieces of logic Each piece goes in a separate logic element (LE) Hook them together g with the p programmable g routing g
y f z I/O /O Pads ads Desired Circuit x I/O Pad f

x y z

LE

FPGA

FPGA LOGIC ELEMENT

Look-Up Table (LUT) + register + extra

LUT A B 0 Out 0 0 1 A B 0 0 1 SRAM Cell Out

FPGAs typically use 4-input or larger LUTs Cyclone C l f family il (l (low cost): t) 4-inputs 4i t Stratix II: Adaptive Logic Module implements 4 6 p LUTs efficiently y input Virtex 5: 6 inputs
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CONNECTING THE LOGIC

y LE z f I/O Pads x I/O Pad

FPGA

Logic elements implement the pieces of the circuit Now hook them up with the programmable routing

PROGRAMMABLE ROUTING

Programmable switches connect fixed metal wires Choose pattern so any logic element can connect to any other
In2 Logic Block SRAM cell In1 Out

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LOGIC DENSITY

We need a unit to express the logic capability of FPGA Is it possible to define such unit precisely? Traditionally: Xilinx: Altera:

LC Logic Cell LE Logic Element

1 LC = 4 4-input LUT + DD-FF + arithmetic/logic/register circuitry 1 LC = 1 LE

PROGRAMMABLE LOGIC BLOCKS (LC OR LE)

Multiplexer Based LUT based PLD based

MULTIPLEXER BASED
GND A B C D E Y A
00 01 10 11 s1 s2

Y=A*B*C*!D*!E

B C D E

Look-Up Tables (LUT)

Look-up table with N-inputs can be used to implement any combinatorial function of N inputs LUT is programmed with the truth-table
A B C D

LUT

LUT implementation
A B Z C D

Truth-table

Gate implementation

PLD - Sum of Products

Programmable AND array followed by fixed fan-in OR gates
A B C Programmable switch or fuse

f1 = A B C + A B C

f2 = A B + A B C

AND plane

PROGRAMMABLE TECHNOLOGIES

One-time programmable Anti-fuse based A ti f b d Security of config data Non-volatile l l reprogrammable bl Flash/EPROM based Limited reconfiguration cycles Reprogramming slow Volatile reprogrammable SRAM based Unlimited number of reconfigurations possible Microseconds to milliseconds for reprogramming

Poly-diffusion Poly diffusion Anti-fuse Anti fuse

PLICE ( Prog. Low Impedance Ckt. Element)

EPROM

SRAMcell
Employs SRAM (Static RAM) cells to control pass transistors and/or transmission gates SRAM cells control the configuration g of logic block as well Volatile Needs an external storage Needs N d a power-on configuration f mechanism In-circuit re-programmable Lesser configuration time Occupies relatively larger area

PROGRAMMABLE TECHNOLOGIES
p Desired p properties:
Minimum area consumption Low on resistance; High off resistance Low p parasitic capacitance p to the attached wire Reliability in volume production

OTHER FPGA BUILDING BLOCKS

Clock distribution Embedded memory blocks Special purpose blocks: DSP blocks Embedded microprocessors

Commercial FPGA
Company Actel Altera Quick logic Xilinx Architecture Row-Based Hierarchal PLD Symmetrical Array Symmetrical Array Logic Block Type Multiplexer Based PLD Block Multiplexer Based LUT Programming Technology Anti-fuse EPROM Anti-fuse Static RAM

MARKET OVERVIEW

Key players: Xilinx, Altera, Lattice, Actel PLD market estimated at $57 billion and rapidly growing The goal is to expand the market: by lowering per-unit cost to attack the low-end market by increasing speed capabilities to attack the high-end market

PLD market share

lowlow -end FPGA family

Overview
M t recent Most t Alt Altera's ' lowlow l -end d FPGA f family il Introduced in 2004, first shipped in February 2005 1 2V core, 1.2V core 90nm process

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Packaging
Commercial C i l grade d and d industrial i d t i l grade d devices d i are offered. ff d

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FunctionalDescription
T -dimensional TwoTwo di i l row/columnrow/column / l -based b d architecture hit t to t implement i l t custom t logic. l i Column and row interconnects of varying speeds provide signal interconnects between Logic Array Blocks (LABs), embedded memory, and multipliers. Logic array consists of LABs, with 16 logic elements (LEs) in each LAB.

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FunctionalDescription(2)
D Density it f from 4 4,608 608 t to 68 68,416 416 LE LEs. Up to four phasephase-locked locked-loops (PLLs). Global clock network consists of up to 16 global clock lines that drive throughout the entire device.

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FunctionalDescription(3)
M4K memory blocks bl k are true t dual duald l-port t memory bl blocks k with ith 4K bits bit of f memory. Works at up to 260 MHz. These blocks are arranged in columns across the device in between certain LABs. Cyclone II devices offer between 119 to 1,152 Kbits of embedded memory.

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FunctionalDescription(4)
Each E h embedded b dd d multiplier lti li block bl k can implement i l t either ith two t 99-bit multipliers, 9 lti li or one 18 1818-bit multiplier. Embedded multipliers are arranged in columns across the device. Up to 250250-MHz performance.

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FunctionalDescription(5)
E h I/O pin Each i is i fed f d by b an IOE (Input t Output t t Element) l t) located at the periphery of the device. I/O pins support various singlesingle-ended and differential I/O standards. Each IOE contains a bidirectional I/O buffer and three registers for registering input, output, and outputoutput-enable signals.

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LEUnit
4-input LUT acts as a function generator for logic functions with 4 variables variables, Carry logic or a 16-bit register.

Programmable register. Can be configured like D, T, JK or SR flipflop. Used optionally.

Cyclone II LE can operate in 2 modes: normal mode arithmetic mode

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LE NormalMode
Suitable S it bl for f general l logic l i applications li ti and d combinatorial bi t i l functions. f ti

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LE ArithmeticMode
Implements I l t a 22-bit full f ll adder dd and d basic b i carry chain h i

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LABsandInterconnects
LAB - Logic Array Block Local Interconnect. Transfers signals between LEs in the same LAB Column Interconnect. Connects multiple LABs

Row Interconnect. Connects multiple l l LABs

Logic Array Block consists of 16 LEs connected with carry and register chains

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ClockManagement(2)
Th There is i one clock l k control t l block bl k for f each h global l b l clock l k network. t k They are arranged on the device periphery. Clock control blocks are used to select/enable/disable a global clock network network. Multiplexers are used with these clocks to form 6 6-bit buses to feed LABs and IOEs.

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ClockManagement(3)
PLLs are located at the corners:

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ClockManagement(4)
Cyclone II PLLs provide:
Clock skew elimination
Provides zero zero-delay clock signal in every part of FPGA.

Clock multiplication and division

Ranges from x(1/128) up to x32.

Phase shifting
Programmable phase shifts in increments of at least 45 45.

Programmable dutyduty-cycle
Generate clock outputs with a variable duty cycle

Manual clock switchover

Enables you to switch between two reference input clocks for applications that may require support for clocks with two different frequencies frequencies.
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EmbeddedMemory
Consists of columns of M4K memory blocks:

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EmbeddedMemory(2)
Th M4K blocks The bl k support the h following f ll i features: f
4,608 RAM bits (4Kbits + parity bits one for each byte) 250 250-MHz performance True dualdual-port memory
Supports any combination of twotwo-port operations: 2 reads, 2 writes, or 1 read and 1 write at different clock frequencies.

Simple dual dual-port memory

Simultaneous reads and writes are supported.

Single Single-port memory

Simultaneous reads and writes are not allowed.

Shift register

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EmbeddedMemory(3)
Th M4K blocks The bl k support the h following f ll i features: f
FIFO buffer ROM
When configured as RAM or ROM, you can use an initialization file to preload the memory contents.

Byte enable
Allows the input data to be masked so the device can write to specific bytes. The unwritten bytes retain the previous written value.

Address clock enable

Used to hold the previous address value for as long as the signal is enabled. enabled This feature is useful in handling cache misses.

Content Addressable memory (CAM) Associative memory

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EmbeddedMultipliers
Located in columns high as one LAB row:

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EmbeddedMultipliers(2)
M lti li blocks Multiplier bl k are optimized ti i d for f intensive i t i Digital Di it l Signal Si l Processing P i functions, f ti such as:
finite impulse response (FIR) filters, Fast Fourier Transform (FFT),

Embedded multipliers can work in 2 basic Discrete Cosine Transform (DCT) functions, functions etc etc. operational modes: One 18b x 18b multiplier Operate atTwo up to 250 MHz. independent 9b x 9b multipliers

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EmbeddedMultipliers(3)
Th embedded The b dd d multiplier lti li consists i t of f the th following f ll i elements: l t Multiplier block Input p and output p registers g Input and output interfaces These signals control operand representation: signed or unsigned

Output Register (used optionally)

Input Register (used optionally)

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Input/OutputElements
IOE IOEs s (I (Input Output Elements) are located in I/O blocks at the periphery:

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Input/OutputElements(2)
IOEs support many features, including:
Differential Diff ti l and d singlesingle i l -ended d d I/O standards t d d 3-state buffers Programmable input and output delays Programmable pullpull-up resistors during device configuration and in User Mode Bus Bus-hold circuitry Joint Test Action Group (JTAG) boundaryboundary-scan test (BST) support

Input/OutputElements(3)
Programmable Pull-Up resistor Output Enable Register (used optionally) Prevents damage from high voltage Output Register (used optionally)

I/O pin

Bus-hold (keeper) circuit

Programmable delay chain (for input) Input Register (used optionally) ( p y)

Input/OutputElements(4)
IOEs support most conventional and high high-speed I/O protocols: LVTTL (3.3V, ( 2.5V, 1.8V) ) LVCMOS (3.3V, 2.5V, 1.8V, 1.5V) SSTL (classes I, II) and differential HSTL (classes I, II) and differential PCI and PCIPCI-X etc etc.

Input/OutputElements(5)
I/O pins on Cyclone II devices are grouped together into I/O banks. Each h bank b k has h a separate power bus. b To accommodate voltagevoltage-referenced I/O standards, each I/O bank has a VREF bus. u t p e voltagevoltage o tage-referenced e e e ced sta standards da ds ca can be suppo supported ted in a an I/O /O ba bank Multiple as long as they use the same VREF and a compatible VCCIO value. For example:
When VCCIO is 3.3V, a bank can support LVTTL, LVCMOS, and 3.3V PCI for inputs and outputs.

Input/OutputBanks

FPGA Design Flow

Design Specification

Design Entry/RTL Coding

Behavioral or Structural Description of Design

RTL Simulation
Functional Simulation Verify Logic Model & Data Flow (No Timing Delays)

LE
MEM I/O

Synthesis
l t D i i t D i S ifi P i iti T Translate Design into Device Specific Primitives Optimization to Meet Required Area & Performance Constraints

Place & Route

Map Primitives to Specific Locations inside Target Technology with Reference to Area & Performance Constraints Specify Routing Resources to Be Used

FPGA Design Flow

tclk

Timing Analysis
- Verify Performance Specifications Were Met - Static Timing Analysis

Gate Level Simulation

- Timing Simulation - Verify Design Will Work in Target Technology

Program & Test

- Program & Test Device on Board

REFERENCES

www.altera.com www.intel.com www.xilinx.com