Whites, EE 481 Lecture 24 Page 1 of 10

2012 Keith W. Whites

Lecture 24: T-Junction and Resistive
Power Dividers.

The first class of three-port network well consider is the T-
junction power divider. We will look at lossless, nearly lossless,
and lossy dividers in this and the next lecture.

A simple lossless T-junction network is shown in Fig. 7.6:
1
V
+
1
V

3
V
+
3
V

2
V
+
2
V

0
Z
1
Z
2
Z
1
I
2
I
3
I
in
Y

There are two basic constraints we need to incorporate into this
power splitter:
1. The feedline should be matched.
2. The input time average power, P
in
, should be divided
between ports 2 and 3 in a desired ratio.

In the text, this ratio is defined as X:Y where:

( )
/ 100% X X Y + of the incident power is delivered
to one output port, and

( )
/ 100% Y X Y + of the incident power is delivered to
the other.
Whites, EE 481 Lecture 24 Page 2 of 10
For example:
1:1 means 50% of the incident time average power is
delivered to each output port.
2:1 means 67% of the incident time average power is
delivered to one output port and the remaining to the
other.

Referring to the circuit above, in order to enforce the first
constraint on the power splitter requires that

in
1 2 0
1 1 1
Y
Z Z Z
= + = (7.25),(1)
Consequently, to divide the incident power between the two
output ports, we simply need to adjust the characteristic
impedances of the two TLs.

Because port 1 is matched, the input time average power is
simply:

2
0
in
0
1
2
V
P
Z
= (2)
where V
0
is the phasor voltage at the junction.

The output powers can be computed similarly as

2
0
1
1
1
2
V
P
Z
= and
2
0
2
2
1
2
V
P
Z
= (3),(4)
Dividing (3) and (4) by (2) we find
Whites, EE 481 Lecture 24 Page 3 of 10

0 1 1
in 0 1
1/
1/
Z P Z
P Z Z
= = and
0 2 2
in 0 2
1/
1/
Z P Z
P Z Z
= = (5),(6)

Because the network is lossless:

1 2
in in
1
P P
P P
+ =
Substituting (5) and (6) into this expression gives

0 0
1 2
1
Z Z
Z Z
+ = so that
1 2 0
1 1 1
Z Z Z
+ =
Consequently, not only have we split the power between the
output ports, but in light of (1) we have also ensured that the
feedline is matched.

So, once we have specified the desired ratios for the output port
powers, we can use (5) and (6) to compute the required
characteristic impedances of these TLs:

0
1
1 in
Z
Z
P P
= and
0
2
2 in
Z
Z
P P
= (7),(8)
Thats basically it for the design of a simple T-junction power
divider. An example of this design process is given in Example
7.1 of the text, which well cover later.

From a practical standpoint, there are two important points that
arise with T-junction power splitters:

Whites, EE 481 Lecture 24 Page 4 of 10
1. J unction effects. At the junction of the TLs, there is likely
to be an accumulation of excess charge. Take a microstrip
junction for example:
+
+
+
+ +
+
+
+
+ +

These charges attract oppositely-signed charges on the
ground plane:
+ + + +
- - - -
E

This time-varying electric field is a displacement current,
of course. We can model this effect as a lumped capacitor
connected to ground, as shown in Fig. 7.6.

2. Characteristic impedance of the output lines. It is not too
practical to have these Z
1
and Z
2
characteristic impedances
in the system. We generally like to work with just one
system impedance, Z
0
.

To compensate for this, we can use QWTs for matching:
Whites, EE 481 Lecture 24 Page 5 of 10
1
V
+
1
V
3
V
+
3
V

2
V
+
2
V

0
Z
0
Z
0
Z
in
Y
in,1
Z
in,2
Z

Using QWTs makes this power splitter more narrow-
banded, unfortunately.

Here, instead of Z
1
and Z
2
, the impedances of interest in the
power splitter design are Z
in,1
and Z
in,2
. From (1), the match
condition now becomes

in,1 in,2 0
1 1 1
Z Z Z
+ = (9)
and from (5) and (6), the power division constraints
become

0 1
in in,1
Z P
P Z
= and
0 2
in in,2
Z P
P Z
= (10),(11)


Example N24.1 (based on text example 7.1). Design a 1:2, T-
junction power divider in a 50-O system impedance.

Well choose to use the network in Figure 7.6 with B =0:
Whites, EE 481 Lecture 24 Page 6 of 10
1
V
+
1
V

3
V
+
3
V

2
V
+
2
V

0
Z
1
Z
2
Z
Port 1
Port 2
Port 3
1
I
2
I
3
I
in
Z

For a 1:2 split, we want line 1 to carry
in
3 P and line 2 to carry
in
2 3 P .

From (7) and (8):

1
50
150
1/3
Z = = O and
2
50
75
2/3
Z = = O
Thats it for the design of the splitter.

Well carry this example further and first check to make sure the
input port is matched. For a lossless network,
1 in 2 in
1 P P P P + =
which implies that
1 2 0
1 1 1 Z Z Z + = . In this example,

1 1 1
75 150 50
+ =
Therefore,
in
50 Z = O as needed and as expected.

Second, well compute the S parameters for this network. We
know that
11
0 S = since we just computed
in
50 Z = O.

The network is reciprocal, so
| |
S must be symmetric. The
network is also lossless and because its a three-port, we know
Whites, EE 481 Lecture 24 Page 7 of 10
that not all ports will be simultaneously matched. That is, port 2
(port 3) will not be matched when ports 1 and 3 (ports 1 and 2)
are terminated with matched loads.

Based on these facts, we can surmise that the S matrix will have
the form:

| |
21 31
21 22 32
31 32 33
0 S S
S S S S
S S S
(
(
=
(
(

(12)

Lets now compute these S parameters:
S
22
. Terminating port 1 with 50 O and port 3 with 75 O, we
find

1 3
0 2 1
22 2
0
0 2 1
|| 2
|| 3
V V
Z Z Z
S
Z Z Z
+ +
= =

= I = =
+

S
33
. Terminating port 1 with 50 O and port 2 with 150 O, we
find

1 2
0 1 2
33 3
0
0 1 2
|| 1
|| 3
V V
Z Z Z
S
Z Z Z
+ +
= =

= I = =
+

S
21
=S
12
. Terminating port 2 with 150 O and port 3 with 75 O,
then

( )
1 1 2
1 V V
+
+ I =
therefore

1
2 3
2
1
0
1
0
1 1
V V
V
V
+ +

+
I =
= =
= + I =
Whites, EE 481 Lecture 24 Page 8 of 10
One subtlety here is the port 1 and port 2 impedances are
different. Consequently, we need to use generalized S
parameters. From Lecture 17:

0,
0,
0,
k
i j
ij
j i
V k j
V Z
S
V Z
+

+
= =
= (4.62)
so that here

2 3
2 0,1
21
1 0,2
0
50
1 0.577
150
V V
V Z
S
V Z
+ +

+
= =
= = =

S
31
=S
13
. Terminating port 2 with 150 O and port 3 with 75 O,
then

( )
1 1 3
1 V V
+
+ I =
so that

1
2 3
3
1
0
1
0
1 1
V V
V
V
+ +

+
I =
= =
= + I =
Hence,
2 3
3 0,1
31
1 0,3
0
50
1 0.816
75
V V
V Z
S
V Z
+ +

+
= =
= = =

S
32
=S
23
. Terminating port 1 with 50 O and port 3 with 75 O,
then

2 2 3
2/3
1 V V
+
=
| |
+ I =
|
|
\ .

Whites, EE 481 Lecture 24 Page 9 of 10
so that
1 3
3 0,2
32
2 0,3
0
2 150
1 0.471
3
75
V V
V Z
S
V Z
+ +

+
= =
| |
= = =
|
\ .

This relatively large value of S
32
indicates there is little isolation
between the two output ports. This is often undesirable.

Since the network is lossless, implying that
| |
S is unitary, then
from (12):

2 2 2
11 21 31
1 S S S + + =
or
2 2
21 31
1 S S + =
Substituting for S
21
and S
31
, we find that

2 2
21 31
0.333 0.666 0.999 S S + = + =
which serves to partially verify the correctness of our S
parameter calculations.


Resistive Divider Power Splitter

This type of divider is shown in Figure 7.7 and is constructed
from three resistors:

Whites, EE 481 Lecture 24 Page 10 of 10
Since this network is lossy, the resistive power divider can be
simultaneously matched at all three ports. However, the two
output ports will most likely not be isolated.

The S-parameter analysis of this three-port can be performed
using only simple circuit theory since all three ports will be
matched. With no reflections from the port, the total port
voltages are simply the amplitudes of the incoming or outgoing
voltage waves, as appropriate for that port.