Verilog HDL

Practical - 08

 We have seen Multiplexer design using assign statement, logic gates, logic equations and Conditional Operators

Procedural Assignments
Blocking Assignments : Blocking assignment statements are executed
in the order they are specified in a sequential block.

Non blocking Assignments

Non blocking assignments allow scheduling of assignments without blocking execution of the statements that follow in a sequential block. <= operator is used to specify non blocking assignments. Used as a method to model several concurrent data transfers that take place after a common event.

Blocking assignments
reg x,y,z; reg [15:0] reg_a, reg_b; integer count; //All behavioral statements must be inside initial or //always block initial begin x = 0; y = 1;z=1; At time=0 count = 0; reg_a =16b0; reg_b = reg_a; #15 reg_a[2] = 1b1; #10 reg_b[15:13] = {x,y,z}; count = count + 1; end

At time=15 At time=25
At time=25

NonBlocking assignments
reg x,y,z; reg [15:0] reg_a, reg_b; integer count; //All behavioral statements must be inside initial or //always block initial begin x = 0; y = 1;z=1; At time=0 count = 0; reg_a =16b0; reg_b = reg_a; reg_a[2] <= #15 1b1; reg_b[15:13] <= #10 {x,y,z}; count = count + 1; end

At time=15 At time=10
At time=0

Application of non blocking assignments

The final values of reg1, reg2, and reg3 are not dependent on the order in which the assignments are processed.

Non blocking Statements to Eliminate Race Conditions

Did values of a & b swapped??

NO

Yes

Implementing Non blocking Assignments using Blocking Assignments

Event-Based Timing Control

Regular event control The @ symbol is used to specify an event control. Statements can be executed on changes in signal value or at a positive or negative transition of the signal value. The keyword posedge is used for a positive transition

Event OR Control

Note:
always @( reset, clock, d) always @(a or b or c or d or e or f or g) OR always @(*)

always @(posedge clock) begin reg1 <= #1 in1; reg2 <= @(negedge clock) in2 ^ in3; reg3 <= #1 reg1; //The old value of reg1 end

Conditional Statements
If condition ( same as C programming)

Multi way Branching (case statement)

Exercise: 1
Design a 4-to-1 Multiplexer using case statement

Exercise: 2
Design a 2-to-4 decoder using
a. Gates b. Case statement

2-to-4 decoder

Exercise: 3
We have already created 1 bit full adder. Now create a partial 32-bit ALU which can do only addition and subtraction of two 32-bit numbers. Refer ALU in the next slide You can use the example given in slide no: 19 (4-bit Ripple Carry Full Adder)

Combining adder and subtractor Use a multiplexor circuit

binv ai 0 1 + si ci+1 a30 +/s30 ci

binv
a0 +/b0 s0

c1
a1 +/b1 c30 s1

bi

b30
a31 c31 +/s31

b31
18 c32

4-bit Ripple Carry Full Adder

module fulladd(sum, c_out, a, b, c_in); // I/O port declarations output sum, c_out; input a, b, c_in; // Internal nets wire s1, c1, c2; // Instantiate logic gate primitives xor (s1, a, b); and (c1, a, b); xor (sum, s1, c_in); and (c2, s1, c_in); xor (c_out, c2, c1); endmodule

// Define a 4-bit full adder module fulladd4(sum, c_out, a, b, c_in); // I/O port declarations output [3:0] sum; output c_out; input[3:0] a, b; input c_in; // Internal nets wire c1, c2, c3; // Instantiate four 1-bit full adders. fulladd fa0(sum[0], c1, a[0], b[0], c_in); fulladd fa1(sum[1], c2, a[1], b[1], c1); fulladd fa2(sum[2], c3, a[2], b[2], c2); fulladd fa3(sum[3], c_out, a[3], b[3], c3); endmodule