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Product specification
UC3842
DESCRIPTION
The UC3842 is available in an 8-Pin mini-DIP the necessary features to implement off-line, fixed-frequency current-mode control schemes with a minimal external parts count. This technique results in improved line regulation, enhanced load response characteristics, and a simpler, easier to design control loop. Topological advantages include inherent pulse-by-pulse current limiting. Protection circuitry includes built-in undervoltage lock-out and current limiting. Other features include fully-latched operation, a 1% trimmed bandgap reference, and start-up current less than 1mA. These devices feature a totem-pole output designed to source and sink high peak current from a capacitive load, such as the gate of a power MOSFET. Consistent with N-channel power devices, the output is low in the OFF-state.
PIN CONFIGURATIONS
N Package
COMP VFB ISENSE RT/CT 1 2 3 4 TOP VIEW 8 7 6 5 VREF VCC
OUTPUT GROUND
D Package
COMP 1 2 3 4 5 6 7 TOP VIEW 14 VREF 13 NC 12 V CC 11 V C 10 OUTPUT 9 8 GROUND POWER GROUND
FEATURES
Low start-up current (1mA) Automatic feed-forward compensation Pulse-by-pulse current limiting Enhanced load response characteristics Undervoltage lock-out with hysteresis Double pulse suppression High current totem-pole output Internally-trimmed bandgap reference 400kHz operation, guaranteed min
BLOCK DIAGRAM
APPLICATIONS
7(11) (12)7 VCC 34V (9)5 GND 16V 2.5V INTERNAL BIAS 6V UVLO S/R 5V REF V 8(14) REF 5.0V 50mA
(7)4 RT/CT OSC 6(10) OUTPUT ERROR AMP VFB COMP CURRENT SENSE NOTE: Pin numbers in parentheses refer to the D package. (3)2 (1)1 (5)3 + S 2R R R 1V CURRENT SENSE COMPARATOR PWM LATCH
5(8)
1100
853-0614 13721
Product specification
UC3842
ORDERING INFORMATION
DESCRIPTION 8-Pin Plastic Dual In-Line Package (DIP) 14-Pin Plastic Small Outline (SO) Package TEMPERATURE RANGE 0 to +70C 0 to +70C ORDER CODE UC3842N UC3842D DWG # 0404B 0405B
NOTES: 1. All voltages are with respect to Pin 5; all currents are positive into the specified terminal. 2. See section in application note on Power Dissipation Calculation. 3. This parameter is guaranteed, but not 100% tested in production.
1101
Product specification
UC3842
Reference section
VOUT Output voltage Line regulation Load regulation Temp. stability1 Line, load, temp. 10Hzf10kHz, TJ=25C TJ=125C, 1000 Hrs. TJ=25 -55<TJ0C TJ=25C 12VCC25V TMINTJTMAX VPIN 4 peak-to-peak V Pin 1=2.5V 2VO4V Unity gain bandwidth1 TJ=25C TMIN<TJ<TMAX 12VCC25V VPIN 2=2.7V, VPIN 1=1.1V VPIN 2=2.3V, VPIN 1=5V VPIN 2=2.3V, RL=15k to ground VPIN 2=2.7V, RL=15k to Pin 8 2.85 VPIN 1=5V 12VCC25V 0.9 Unity gain bandwidth PSRR ISINK ISOURCE Power supply rejection ratio Output sink current Output source current VOUT High VOUT Low 2.42 -30 -30 4.82 50 5 -100 -100 25 -130 -180 voltage1 Total output variation1 VNOISE Output noise Long-term stability1 Output short-circuit Output short-circuit TJ=25C, IO=1mA 12VIN25V 1IO20mA 4.90 5.00 6 6 0.2 5.10 20 25 0.4 5.18 V mV mV mV/C V V mV mA mA
Oscillator section
Initial accuracy Voltage stability Temp. stability1 47 52 0.2 5 1.7 57 1 kHz % % V
Amplitude
1102
Product specification
UC3842
Output section
VOL VOH tR tF Output Low-Level Output High-Level Rise time Fall time ISINK=20mA ISINK=200mA ISOURCE=20mA ISOURCE=200mA CL=1nF CL=1nF 14.5 8.5 13 12 0.1 1.5 13.5 13.5 50 50 150 150 0.4 2.2 V V ns ns
PWM section
Maximum duty cycle Minimum duty cycle 93 97 100 0 %
UNDERVOLTAGE LOCKOUT
7 VCC ON/OFF COMMAND TO REST OF IC
VON VOFF
ICC
<15mA <1mA VOFF NOTE: During Undervoltage Lock-Out, the output driver is biased to a high impedance state. Pin 6 should be shunted to ground with a bleeder resistor to prevent activating the power switch with output leakage current. VON
VCC
1103
Product specification
UC3842
1 COMP R
3 CURRENT SENSE
RS 5 GND
1104
Product specification
UC3842
0.1F
0.1F
1k 1W OUTPUT
GND CT NOTE: High peak currents associated with capacitive loads necessitate careful grounding techniques. Timing and bypass capacitors should be connected close to Pin 5 in a single point ground. The transistor and 5k potentiometer are used to sample the oscillator waveform and apply an adjustable ramp to Pin 3.
SHUTDOWN TECHNIQUES
4.7k 8
TO CURRENT SENSE RESISTOR NOTE: Shutdown of the UC3842 can be accomplished by two methods; either raise Pin 3 above 1V or pull Pin 1 below a voltage two diode drops above ground. Either method causes the output of the PWM comparator to be high (refer to Block Diagram). The PWM latch is reset dominant so that the output will remain low until the next clock cycle after the shutdown condition at Pins 1 and/or 3 is removed. In the examples shown, an externally-latched shutdown may be accomplished by adding an SCR which will be reset by cycling VCC below the lower UVLO threshold (10V). At this point all internal bias is removed, allowing the SCR to reset.
1105
Product specification
UC3842
1N3613 1N3613
AC INPUT
16V 0.01F UC3842 20k 2 150k VFB 1 COMP 3.6k 100pF 8 VREF 10k 4 RT/CT 0.01F 0.0047F GND 5 3 CUR SEN 470pF 1k 0.85 6 OUT 20k NOTES: T1: Coilcraft E-4140-B Primary 97 turns single AWG24 Secondary 4 turns 4 parallel AWG22 control 9 turns 3 parallel AWG28 27 UFN432 VCC 7 10F 20V 820pF 1N3613 2.5k
ISOLATION BOUNDARY
SPECIFICATIONS
Input line voltage: Input frequency: Switching frequency: Output power: Output voltage: Output current: Line regulation: Load regulation: Efficiency @ 25 W, VIN=90VAC: VIN=130VAC: Output short-circuit current: 70% 65% 2.5A average 90VAC to 130VAC 50 or 60Hz 40kHz10% 25W maximum 5V5% 2 to 5A 0.01%/V 8%/A* NOTE: This circuit uses a low-cost feedback scheme in which the DC voltage developed from the primary-side control winding is sensed by the UC3842 error amplifier. Load regulation is therefore dependent on the coupling between secondary and control windings, and on transformer leakage inductance. For applications requiring better load regulation, a UC1901 Isolated Feedback Generator can be used to directly sense the output voltage.
1106
Product specification
UC3842
4 RA 7 RESET DISCH
RB 2 TRIG 6 THRESH
NE555
OUT
RT/CT 4 UC3842
C NOTES: 1.44 f + (R A ) 2R B) C RB RA ) 2R B
MAX
1107
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