HiPer PX Quick Start Guide

HiPer PX is driven from L-Edit, and requires a space tech setup. The tech setup typically includes layer derivations, device recognition, connectivity descriptions, as well as physical parameters such as resistivity, dielectric constants, layers thickness and edge geometry, etc. The creation of a tech setup is beyond the scope of this document, but the basic required files are: space.def.s human readable tech setup source file space.def.p extract preferences Other files may be required, depending on tech setup details. HiPer PX is found in the L-Edit menus under Tools->Parasitic Extractor.

Finding or Creating the Technology Files The first dialog, Define Technology is used to select which technology setup will be used by this design.

The process path is the name of the folder containing the space technology setup (space.def.s, space.def.p, etc). This field can be an absolute path (ie C:\path\to\tech\setup) or a relative path. If a relative path is specified, it will specify the tech folders relationship to the folder containing the design file. If the tech setup has already been compiled, click Apply to set this designs tech folder path. If you have modified the space.def.s file, or this is the first time you have used this tech setup, you will need to compile it. Clicking on Create will generate the following files in the process folder: space.def.t the compiled form of space.def.s, used by PX to perform extraction maskdata the list of design layers that will be exported to space. Layers included in this file are drawn layers in L-Edit which have a GDS number defined and are mentioned in the space.def.s file. For compatibility with space.def.s, all characters in the layers name except letters and numbers will be replaced with underscore (_). default_lambda the manufacturing grid for this process.

Exporting Layout Data HiPer PX works with a separate database of the layout, optimized for parasitic extraction. L-Edit automatically manages this database, and will update it before each extract run. The Export Database dialog controls the location of this database and L-Edits update behavior.

The path to the database can be absolute, or relative to the design file. Choosing to export All data will cause the database folder to be completely deleted and rebuild before each extract run. This is incompatible with incremental extract and selective resistance extraction (described below). Exporting Modified cells only is recommended. In this mode, L-Edit will check each cell in the PX database, and if it has been changed in the L-Edit design file, it will be overwritten. Pressing OK will create the database path if necessary and export the current cell and its hierarchy to the PX database.

Extracting Layout Once you have set a process folder and database path for the design, you will only need to use the extract dialog for future extractions.

Output file the extracted spice netlist. If a file exists with this name, it will be overwritten. The path can be absolute or relative to the design file. Hierarchy Flat or Hierarchical In Fast (2d) mode, the hierarchical extraction mode is available. In this mode, the design will be extracted based on the layout hierarchy. This mode requires careful design practices, since interactions between hierarchy levels are limited to ports. If a short is created outside of a port, it will extract as an open. Also, parasitic coupling capacitances between layout features of different cells dont fit in a hierarchical circuit description. It is recommended to verify that a design passes LVS using an extract without parasitics before relying on simulations from a hierarchical extract. Within the hierarchical mode, the incremental mode will use existing extractions of sub-cells rather than re-extracting them if the layout has not been modified. This allows mixed mode extract, since a sub-cell can be extracted in Accurate mode and combined with a higher level cell extracted in Fast mode. Capacitance extraction o No extraction no parasitic capacitors will be extracted o Fast uses a 2D interpolated model to extract parasitic capacitors

o Accurate uses a 3D boundary element model to parasitic capacitance o Types of parasitic capacitors extracted Capacitances to substrate only parasitic (area and fringe) capacitance to the substrate will be extracted. Cap(acitance)s to substrate & vertical coupling cap(acitance)s parasitic capacitance to the substrate will be extracted, as will crosstalk capacitance between overlapping interconnect layers. (Fast mode only) Cap(acitance)s to substrate, vertical & lateral coupling cap(acitance)s all parasitic capacitance will be extracted, including capacitance to the substrate and crosstalk capacitance between nearby interconnect nodes. Interconnect Resistance Extraction o No extraction no interconnect resistance will be extracted o Fast uses an efficient finite-element method to extract interconnect resistances o Accurate uses a similar finite-element method, but applies a mesh refinement which increases the accuracy and relevance of the extracted interconnect resistors. See Mesh Refinement Application Note (an0309.pdf) for details of the algorithm. o Limiting resistance extraction by node - If desired, the user may specify nodes for which interconnect resistance is, or is not performed. These nodes are specified by coordinate and layer in a file named sel_con and placed in the database folder (<database_path>\<tdb file name>\sel_con). The format of the file sel_con is as follows. On each line, an x position, an y position and a layername is specified. When an interconnect has the specified layer on the specified layout position, that interconnect is specified in the file. Coordinates are specified in manufacturing grid units. (Ex. 200 150 cpg specifies st4 node in the Oscilx.tdb file. Since the manufacturing grid is 0.05u, the coordinates in micros is x=10u, y=7.5u) Note that, this file should be added to the folder after exporting layout data. Then you should change it Modified cells only, otherwise it will be deleted. Circuit reduction complex RC networks on large designs can be slow on some simulators. HiPer PX provides an algorithm to reduce the complexity of the RC networks without sacrificing accuracy. When extracting resistances together with capacitances, the extractor will add lumped capacitances to the nodes of the initial resistance network to model the distributed capacitive effects. In that case, the node reduction will proceed such that the Elmore time constants between the nodes in the final network are unchanged with respect to their value in the fine RC mesh. This can be done in a frequency independent method, or a more aggressive method which is accurate up to a user-specified frequency.