1.

a.

b. 2. a. b. 3. a. b.

Convert the following i. 101 10112 =______________________6 1 ii. 53147 = _________________________10 1 iii. A19BH = ________________________O 1 iv. Perform the following using 2s Complement Subtraction 2 1000100 - 1100011 Perform the following using 8421 Code 5 1278 + 752 Encode the binary word into a 7 bit even hamming code for 1010. And the 5 received code is 1110010, locate the error and correct it 2 i. Z (Y Z )( X Y Z ) 3 [ A B (C BD ) AB ]C ii.

ABCD BCDE AB BC E reduce using Consensus Theorem Apply DeMorgans Law for the Following

c. 4.

3 A B C D EF Simplify the following using K Map F = M (0,1,2,4,6,8,10,13,15) and represent 5 in SOP function A bank vault has three locks with different key for each lock. Each key is owned by different person. In order to open the door, at least two people must insert their keys into assigned locks. The signal lines A, B, and C are 1 if there is a key inserted into lock 1, 2 or 3 respectively. Design a circuit using only NAND gate, for output Z which is 1 iff the door should open. Design a circuit which can convert BCD code to 84 21 code Design a given function using 4 input digital switch F (A,B,C,D) = m(0,1,4,6,7,10,12,15)+dm(5,8,14). Consider AB as Selection lines and CD as input data line. (A is the MSB). Design a Full adder using active high input and active low output Decoder with suitable external logic gates. 10

5. 6.

a.

10 5

b.

7.

a.

i. ii. iii.

Find the answer for Y from the above diagram. Realize a SR flip flop from D flip flop. Realize a SR flip flop from T flip flop OR

2.5 2.5

b. i. Find the truth table for the outputs F and G of the hierarchical circuit 5 shown below.

8.

ii. Design a D Flip flop using Multiplexer. Analyze the following circuit and draw the state graph.

5 10

9.

a.

Reduce the state table using Implication Chart method. Derive the equations using 10 D FF. Note dont skip any steps.

OR

b.

A sequential Circuit has one input (X) and two outputs (Z1 and Z2). An output Z1 = 1 occurs every time the input sequence 100 is completed provided that the sequence 011 has never occurred. An output Z2 = 1 occurs every time the input 011 is completed. Note that once a Z2 = 1 output has occurred, Z1 = can never occur but not vice versa. Find the Mealy state graph and state table (minimum number of states is 8).
Implement the following Three Boolean functions with PLA F1 (A, B, C) = m (0, 1, 2, 4) F2 (A, B, C) = m (0, 5, 6, 7) F3 (A, B, C) = m (0, 3, 5, 7) Design a 4 input NAND and NOR gate Using CMOS logic

10. a.

b.