EE4375 VLSI Project Report for Fall 2013

Gideon Udo
Department of Electrical and Computer Engineering University of Texas at El Paso El Paso, Texas 79968 gaudo@miners.utep.edu
Abstract In this project, a functional 2 to 4 decoder system in the form of transistors was designed, simulated and prepared to be transformed into a physical layout. For this assignment, the programs that were used are: Cadence Virtuoso ICFB, Analog Design Environment and Virtuoso Layout Editor. The 2 to 4 decoder is a combinational circuit that decodes or converts binary information from 2 input lines to 4 unique output lines.

Fig. 2 NAND with inputs labeled A and B.

B. NAND Gate
1) A NAND gate module was designed, simulated and finalized with the same tools and processes used for the inverter. A total of four transistors (two PMOS and two NMOS) were used. Fig. 2 shows the transistor-level schematic for the NAND gate used in this project.

I.

DISCUSSION OF DESIGN

After the Cadence Virtuoso tutorial was used to become familiar with the full-custom integrated circuit design tools and analog signal features of the software, the schematic for first module to be merged into the final design was created.

C. The 2 to 4 Decoder
1) With the smaller component module designs completed and tested to verify their connections and proper functionality, the decoder was ready to be built and tested in a similar way, using the same features of Virtuoso. 2) Two instances of the inverter module and four instances of the NAND module were combined and simulated together, then compared to a four-to-one decoder truth table to confirm its correct operation. 3) The layout is now finalized into a block as its own module with the potential to be incorporated into the designs of larger circuits. Fig. 3 shows a 2-to-4 decoders schematic and truth table.

A.
1)

Inverter
The inverter was first mapped out by connecting a p-type MOSFET (PMOS) transistor, an n-type MOSFET (NMOS) transistor, a power supply voltage (vdd) and a ground line (gnd), with input and output pins (as shown in Fig. 1) using the Schematics L tool. With the wiring complete, the inverter schematic was ready to be simulated by connecting voltage pulses to the input and a 1fF capacitor to the output. The simulation was successful in showing that the input voltage was inverted from low to high and from high to low. The Layout XL tool was used to specify the placement of the PTAP/NTAP substrate contacts, the width of metal/poly paths, and to verify and finalize the module for its use in the final layout.

2)

3)

Fig.1Transistor-Level Inverter.

Fig. 3 The Decoder. **A reverse-logic approach was used (NAND gates instead of AND) in my project as the simulation data reflect. The outputs (D values) in the truth table are inverted.