Spyglass CDC improves SOC design quality control

XU TONG Project Director, Loongson Technology

Email: xutong@ict.ac.cn
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Outline
About loongson CDC origin: Metastability CDC brings challenge to design quality management Our design case with SG-CDC

Summary

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About Loongson Technology ltd.

Established in 2008 by ICT Industrialization origin of Loongson technology

Loongson Architecture, chip, system etc. Developer of the first 32-bit general-purpose CPU of China

Team of original Loongson CPU

Licensor of the high-performance 64-bit CPU architecture to ST micro

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Loongson Technology : new Turn-key solution provider

Proprietary IP license ---silicon proven

Loongson CPU IP LS132, LS232, LS464 System fabric IP AXI generator, AHB, APB, bridge, memory controller, etc. Peripheral IP CAN,AC97, LCD display controller , PCI, I2C, SPI, serial port etc. Network IP
High-performance level-2 ethernet switch, etc.

SOC design service--- experience from 180um to 65nm,up to GHz design

Physical design service SOC design service Tool-chain and driver development design consultation High-speed board design BSP-level and OS-level software development

System design service

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Multiple clock domain becomes more and more

popular in SOC design
More peripherals : HDMI,USB, SATA, PCI, LCD, AC97, CAN, SPI, RS232, MAC Core frequency and bus frequency mismatch Asynchronous signals requirement

Direct frequency division relationship rarely meet

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CDC problems origin: single-bit meta-stability

DFF internal schematic Meta-stability

Different CLKs make things worse

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CDC problem challenge SOC design quality management

more and more 3rd party IPs integrated

Grey box: Trust or not?

Internal coding by engineers from different group and with different level

Does he or she really understand the design or CDC

techniques?

Pre-simulation and post-simulation can not find meta-stability if not intentionally and specially considered

How to verify design is CDC BUG free?

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Spyglass CDC substitution for man-power check

Spyglass CDC: A formal check methodology of CDC

SG SG

Managing Multi-clock Designs

RTL

IPs
SG

Systematic approach towards CDC problems

Design Creation
Verification

check and report any unsynchronized signals Clocks and Reset

Synthesis

Backend

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Case study
A SOC design with 12 clock domain, 900Kgates and 25 Macro.

1x 3rd-party IP 5x designs from other group 1x design by novice with preliminary training and

design guideline

CDC issue planned for manual check before running Spyglass

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CDC issue 1 : basic check

clock_sync08a: Misusing double sampling on data signals

Ordinary fault by green hand

Clock_sync01: 1 signal missing double sample in the 3rd-party IP

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CDC issue 2 : Functional check Ac_cdc01a: Data hold in multi-flop synchronized fastto-slow crossing

Report data loss with clocks with different periods

Bugs found in codes by another group

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CDC issue 3 : intensive structural check

Clock_sync03b: convergence of two signals originating from different domains

1 bus signal missing found in synchronizers FIFO design refinement

Also Clock_sync03b

1 fake bug: fail to identify our handshaking protocol

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CDC Data for Running Spyglass

Tool introduction to adoption: 2 week CDC runtime when design fixed: 28 min CDC output

bugs untouched before CDC 2 real CDC bugs found in 3rd-party soft IP 4 real CDC bugs found in codes by other group 1 real CDC bug found in codes by green-hand 1 CDC potential of reset in SOC integration

All CDC problems fixed in 1 week Chip run successfully at the first tape-out, in volume production now
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SG CDC: Not perfect, but really good enough

To be enhanced:

Sometimes output is mass

Misreports for system-level synchronization

Sometimes long runtime

Unpredictable time variation dependence on design style

Designers Solution

Strict design guidelines for engineer to follow Run spyglass CDC check with your own template and waiver Check reports carefully Communication with excellent local support staff

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SG-CDC value in our SOC design management

Classified potential CDC problems list

Good metric for quality control regardless of code source Controllable time for design re-spins

Excellent visual schematic and waveform to debug

Simple to setup

Minimum flow adjustment time for tool introduction Good training book for novice

Detailed databook

Overall increase of design efficiency

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Thanks!

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