CONTENTS S. No. 1 2 3 4 5 6 & + Title Syllabus Lesson Plan Course / Subject Objectives Program / Learning Outcomes Prerequisites o!

ics covere" 6#1 Core o!ics 6#2 o!ics Covere" beyon" t$e syllabus e't boo(s an" )e*erences ,ction - ,ssessment !lan .to im!rove t$e course !lan to meet t$e objectives/ +#1 ,ctions +#1#1 +#1#2 +#1#3 +#1#4 +#1#5 +#1#6 +#1#& 4 15 11 ,ssignments 0ini !roject 1or( s$o!/Seminar Pa!er !resentation Case Stu"y Sli! est / 2ui3 0i" erm 2uestion Pa!er & 4 4 Page No. 2 3 4 5 5 5%6 6 6

+#2 ,ssessment !lan *or ,ctions )elation o* course to !rogramme outcomes Course Objectives / Programme Outcomes 0atri' Lecture 6otes .7nit%8ise/ UNIT-1

1#1 1#2 1#3 1#4 1#5 1#6 1#& 1#+

9ntro"uction to :LS9 ec$nology O!eration o* 0OS; P0OS; 60OS <abrication o* 60OS - P0OS <abrication o* C0OS O'i"ation; Lit$ogra!$y; =i**usion 9on im!lantation; 0etallisation; >nca!sulation Probe testing 9ntegrate" )esistors an" Ca!acitors Total classes to complete UNIT-I UNIT-II

2#1 2#1

=rain to source current vs voltage relations$i!s o* 0OS 0OS transistor $res$ol" voltage an" <igure o* merit

2#3 2#4 2#5 2#6 2.7

Pass transistor; 60OS 9nverter =etermination o* Pull%u! to Pull%"o8n ratio C0OS 9nverter analysis an" "esign ?i%C0OS 9nverters Total classes to complete UNIT-II UNIT-III

3#1 3#2 3#3 3#4 3#5 3#6 3.7

:LS9 =esign <lo8; 0OS Layers Stic( =iagrams =esign )ules an" Layout; C0OS =esign rules *or 8ires Contact cuts; Layout =iagrams *or 60OS an" C0OS 9nverters an" @ates Scaling o* 0OS circuits Limitations o* Scaling Total classes to complete UNIT-III UNIT-IV

4#1 4#2 4#3 4#4 4#5 4#6 4#& 4.8

Logic @ates an" ot$er com!le' gates S8itc$ Logic; ,lternate gate circuits; ?asic circuit conce!ts S$eet )esistance )S an" its conce!t to 0OS ,rea Ca!acitance o* Layers Calculation o* =elays =riving Large Ca!acitive Loa"s; <an%in an" <an%out 1iring Ca!acitances; C$oice o* Layers Total classes to complete UNIT-IV UNIT-V

5#1 5#2 5#3 5#4 5#5 5#6 5.7

Subsystem =esign; S$i*ters; ,""ers ,L7s 0ulti!liers Parity generators; Com!arators Aero/One =etectors; Counters Big$ =ensity 0emory >lements Total classes to complete UNIT-V UNIT-VI

6#1 6#2 6#3 6#4 6#5 6#6

=esign o* PL,s =esign o* <P@,s =esign o* CPL=s Stan"ar" Cells =esign o* P,Ls >'ercise !roblems Total classes to complete UNIT-VI UNIT-VII

&#1 &#2 &#3 &#4 &#5 &#6 7.7 +#1 +#2 +#3 +#4 +#5 8. 8.7

:B=L Synt$esis Circuit =esign <lo8; Circuit Synt$esis Simulation; Layout =esign ca!ture tools =esign veri*ication tools est Princi!les Total classes to complete UNIT-VII UNIT-VIII C0OS esting; 6ee" *or testing est Princi!les; =esign Strategies *or test C$i!level est ec$niques System Level est ec$niques Layout =esign *or im!rove" estability Total classes to complete UNIT-VIII TOT!" NO O# C"!SSES 144 1&2

1. S$""!%US V"SI &ESI'N UNIT I INT(O&UCTION ) 9ntro"uction to 9C ec$nology C 0OS; P0OS; 60OS; C0OS ?iC0OS tec$nologies% O'i"ation; Lit$ogra!$y; =i**usion; 9on im!lantation; 0etallisation; >nca!sulation; Probe testing; 9ntegrate" )esistors an" Ca!acitors# UNIT II %!SIC E"ECT(IC!" P(OPE(TIES ) ?asic >lectrical Pro!erties o* 0OS an" ?iC0OS CircuitsD 9"s%:"s relations$i!s; 0OS transistor t$res$ol" :oltage; gm; g"s; *igure o* merit oE Pass transistor; 60OS 9nverter; :arious !ull u!s; C0OS 9nverter analysis an" "esign; ?i%C0OS 9nverters#

UNIT III V"SI CI(CUIT &ESI'N P(OCESSES) :LS9 =esign <lo8; 0OS Layers; Stic( =iagrams; =esign )ules an" Layout; 2 m C0OS =esign rules *or 8ires; Contacts an" ransistors Layout =iagrams *or 60OS an" C0OS 9nverters an" @ates; Scaling o* 0OS circuits; Limitations o* Scaling# UNIT IV '!TE "EVE" &ESI'N ) Logic @ates an" Ot$er com!le' gates; S8itc$ logic; ,lternate gate circuits; ?asic circuit conce!ts; S$eet )esistance )S an" its conce!t to 0OS; ,rea Ca!acitance 7nits; Calculations % F% =elays; =riving large Ca!acitive Loa"s; 1iring Ca!acitances; <an%in an" *an%out; C$oice o* layers UNIT V SU%S$STE* &ESI'N ) Subsystem =esign; S$i*ters; ,""ers; ,L7s; 0ulti!liers; Parity generators; Com!arators; Aero/One =etectors; Counters; Big$ =ensity 0emory >lements# UNIT VI SE*ICON&UCTO( INTE'(!TE& CI(CUIT &ESI'N ) PL,s; <P@,s; CPL=s; Stan"ar" Cells; Programmable ,rray Logic; =esign ,!!roac$# UNIT VII V+&" S$NT+ESIS ) :B=L Synt$esis; Circuit =esign <lo8; Circuit Synt$esis; Simulation; Layout; =esign ca!ture tools; =esign :eri*ication ools; est Princi!les# UNIT VIII C*OS TESTIN' ) C0OS esting; 6ee" *or testing; est Princi!les; =esign Strategies *or test; C$i!level est ec$niques; System%level est ec$niques; Layout =esign *or im!rove" estability# TE,T%OO-S D 1# >ssentials o* :LS9 circuits an" systems C Gamran >s$rag$ian; >s$rag$ian =ougles an" ,#Puc(nell; PB9; 2555 >"ition 2# Princi!les o* C0OS :LS9 =esign C 1este an" >s$rag$ain; Pearson >"ucation; 1444 r" 3# 0o"ern :LS9 =esign C 1ayne 1ol*; Pearson >"ucation; 3 >"ition; 144& 4#:B=L%Programming by e'am!le%=ouglas !erry $ir" >"ition (E#E(ENCES ) 1# C$i! =esign *or Submicron :LS9D C0OS Layout - Simulation; % Ho$n P# 7yemura; $omson Learning# 2# 9ntro"uction to :LS9 Circuits an" Systems % Ho$n #P# 7yemura; Ho$n1iley; 2553# 3# =igital 9ntegrate" Circuits % Ho$n 0# )abaey; PB9; >>>; 144&# 5# :LS9 ec$nology C S#0# SA>; 2n" >"ition; 0B; 2553#

2. "ESSON P"!N

S.No

Name o. t/e Topic

No o. Te0t Classes %oo1s

1 2 3 4 5 6 & + 4 15 11 12 13 14

UNIT-I 9ntro"uction to :LS9 ec$nology O!eration o* 0OS; P0OS; 60OS <abrication o* 60OS - P0OS <abrication o* C0OS O'i"ation; Lit$ogra!$y; =i**usion 9on im!lantation; 0etallisation; >nca!sulation Probe testing 9ntegrate" )esistors an" Ca!acitors Total classes to complete UNIT-I UNIT-II =rain to source current vs voltage relations$i!s o* 0OS 0OS transistor $res$ol" voltage an" <igure o* merit Pass transistor; 60OS 9nverter =etermination o* Pull%u! to Pull%"o8n ratio C0OS 9nverter analysis an" "esign ?i%C0OS 9nverters Total classes to complete UNIT-II

1 1 1 1 1 1 1 1 8 2 1 1 2 1 1 8

2 2 1 1 1 1 1 2 1 1 1 1 1 1

15 16 1& 1+ 14 25 21 22 23 24 25 26 2& 2+ 24 35 31 32 33

UNIT-III :LS9 =esign <lo8; 0OS Layers Stic( =iagrams =esign )ules an" Layout; C0OS =esign rules *or 8ires Contact cuts; Layout =iagrams *or 60OS an" C0OS 9nverters an" @ates Scaling o* 0OS circuits Limitations o* Scaling Total classes to complete UNIT-III UNIT-IV Logic @ates an" ot$er com!le' gates S8itc$ Logic; ,lternate gate circuits; ?asic circuit conce!ts S$eet )esistance )S an" its conce!t to 0OS ,rea Ca!acitance o* Layers Calculation o* =elays =riving Large Ca!acitive Loa"s; <an%in an" <an%out 1iring Ca!acitances; C$oice o* Layers Total classes to complete UNIT-IV UNIT-V Subsystem =esign; S$i*ters; ,""ers ,L7s 0ulti!liers Parity generators; Com!arators Aero/One =etectors; Counters Big$ =ensity 0emory >lements Total classes to complete UNIT-V UNIT-VI

1 2 2 3 1 1 12 1 2 1 1 1 1 1 8 1 2 1 1 2 1 8

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

34 35 36 3& 3+ 34 45 41 42 43 44 45 46 4& 4+ 44 55

=esign o* PL,s =esign o* <P@,s =esign o* CPL=s Stan"ar" Cells =esign o* P,Ls >'ercise !roblems Total classes to complete UNIT-VI UNIT-VII :B=L Synt$esis Circuit =esign <lo8; Circuit Synt$esis Simulation; Layout =esign ca!ture tools =esign veri*ication tools est Princi!les Total classes to complete UNIT-VII UNIT-VIII C0OS esting; 6ee" *or testing est Princi!les; =esign Strategies *or test C$i!level est ec$niques System Level est ec$niques Layout =esign *or im!rove" estability Total classes to complete UNIT-VIII TOT!" NO O# C"!SSES

2 1 1 1 1 1 7 1 2 1 1 1 2 8 1 2 2 1 2 8 5

1 1 1 1 1 1 4 4 4 4 4 4 2 2 2 2 2 2

3. COU(CE3 SU%4ECT O%4ECTIVES) 1# 7n"erstan" t$e gro8t$ o* 9C ec$nology by con"ucting a qui3/seminar# 2# 7n"erstan" t$e im!act o* t$e !$ysical an" c$emical !rocesses o* integrate" circuit *abrication tec$nology on t$e "esign o* integrate" circuits# 3# 7n"erstan" !$ysics o* t$e Crystal gro8t$; 8a*er *abrication an" basic electrical !ro!erties o* silicon 8a*ers# 4# Learn $o8 to "esign 0OS circuits using stic( "iagrams an" layouts%,ssignments 5# 7n"erstan" t$e "esign o* logic gates an" subsystems using 0OS transistors# 6# Learn "i**erent testing strategies o* C0OS circuits# &# =evelo!ing a mini!roject /!a!er !resentation on 4. P(E(E5UISITES %$ TOPIC) 1# $e *un"amental o!eration o* semicon"uctor "evices an" t$eir circuit a!!lications# 2# $e !$ysical !rinci!les o* semicon"uctors; em!$asi3ing silicon tec$nologyE o!erating !rinci!les an" "evice equations *or P6 "io"es; biasing; an" elementary circuit a!!lications o* "io"es# 3# ?asic o!erating !rinci!les an" "evice equations *or 0OS ca!acitors an" transistors; an" bi!olar junction transistors# 4# $e basics o* transistor am!li*ier an" logic circuit "esign using 0OS transistors 5. P6og6am E78catio9 O8tcomes

a/ @ra"uates 8ill "emonstrate (no8le"ge o* "i**erential equations; vector calculus; com!le' variables; matri' t$eory; !robability t$eory; !$ysics; semicon"uctor an" electronic "evices# b/ @ra"uates 8ill "emonstrate an ability to i"enti*y; *ormulate an" solve electronics an" communication engineering !roblems# c/ @ra"uate 8ill "emonstrate an ability to "esign analog an" "igital circuits; con"uct e'!eriments on electronics an" communication systems; analy3e an" inter!ret "ata# "/ @ra"uates 8ill "emonstrate an ability to analy3e; "esign an analog an" "igital system; com!onent or !rocess as !er nee"s an" s!eci*ications# e/ @ra"uates 8ill "emonstrate an ability to visuali3e an" 8or( on >C> laboratory an" multi"isci!linary tas(s# */ @ra"uate 8ill "emonstrate s(ills to use mo"ern electronics an" communication engineering tools; so*t 8ares an" equi!ment to analy3e !roblems# g/ @ra"uates 8ill "emonstrate (no8le"ge o* !ro*essional an" et$ical res!onsibilities# $/ @ra"uate 8ill be able to communicate e**ectively in bot$ verbal an" 8ritten *orm# i/ @ra"uate 8ill s$o8 t$e un"erstan"ing o* im!act o* electronics an" communications engineering solutions on t$e society an" also 8ill be a8are o* contem!orary issues# j/ @ra"uate 8ill "evelo! con*i"ence *or sel* e"ucation an" ability *or li*e%long learning# (/ @ra"uate 8$o can !artici!ate an" succee" in com!etitive e'aminations li(e @, >; @)>; 9>S; B,L etc# . Topics to :e co;e6e7 .1) Topics co;e6e7 <abrication an" electrical !ro!erties o* 0OS transistors :LS9 circuit "esign !rocesses an" layout "iagrams @ate level an" subsystem "esign using 0OS transistors Semicon"uctor integrate" circuit "esign a!!roac$ :B=L synt$esis an" C0OS testing .2) Topics to :e co;e6e7 :e<o97 t/e s<lla:8s 6on i"eal 9%: e**ects o* c$aracteristics o* 0OS transistor ransmission @ates

7. Te0t :oo1s a97 (e.e6e9ces TE,T%OO-S D 1# >ssentials o* :LS9 circuits an" systems C Gamran >s$rag$ian; >s$rag$ian =ougles an" ,#Puc(nell; PB9; 2555 >"ition

2# Princi!les o* C0OS :LS9 =esign C 1este an" >s$rag$ain; Pearson >"ucation; 1444 3# 0o"ern :LS9 =esign C 1ayne 1ol*; Pearson >"ucation; 3r" >"ition; 144& 4#:B=L%Programming by e'am!le%=ouglas !erry $ir" >"ition (E#E(ENCES ) 1# C$i! =esign *or Submicron :LS9D C0OS Layout - Simulation; % Ho$n P# 7yemura; $omson Learning# 2# 9ntro"uction to :LS9 Circuits an" Systems % Ho$n #P# 7yemura; Ho$n1iley; 2553# 3# =igital 9ntegrate" Circuits % Ho$n 0# )abaey; PB9; >>>; 144&# 5# :LS9 ec$nology C S#0# SA>; 2n" >"ition; 0B; 2553# 8. !ctio9 = !ssessme9t pla9 >to imp6o;e t/e co86se pla9 to meet t/e o:?ecti;es@ +# Stu"ents s$oul" atten" t$e "aily lecture classes an" maintain t$e lecture notes *or every subject# $ere are ot$er requirements ot$er t$an atten"ing t$e classes# 8.1@ !ctio9s) 8.1.1@ !ssig9me9ts) I9st68ctio9s) ,ll t$e assignments s$oul" be in eit$er !rinte" 0S 1or" or 1ritten "ocuments 8it$ t$e *ollo8ing requirements# 1/ Cover !age 8it$ name; course name an" course section# 2/ , !age 8it$ assignments tas(s# 3/ Solutions/>'!lanations# 8o assignments are given to t$e stu"ents "uring t$e course# !ssig9me9t1 )> #6om 1-4 89its@ 1# =escribe t$e t8o commonly use" met$o"s *or obtaining integrate" ca!acitor# 2# 1it$ neat s(etc$es; e'!lain in "etail; all t$e ste!s involve" in electron lit$ogra!$y !rocess# 3# 1$at is 0ooreIs la8J >'!lain its relevance 8it$ res!ect to evolution o* 9C ec$nology# 4# 1it$ neat s(etc$es e'!lain t$e *abrication o* C0OS inverter using !%8ell !rocess# 5# >'!lain in "etail about 60OS en$ancement mo"e o* o!eration# 6# >'!lain various regions o* C0OS inverter trans*er c$aracteristics# &# <or a C0OS inverter; calculate t$e s$i*t in t$e trans*er c$aracteristic curve 1$en n/p ratio is varie" *rom 1/1 to 15/1# +# >'!lain n0OS inverter an" latc$ u! in C0OS circuitsJ 4# =erive an equation *or IDS o* an n%c$annel >n$ancement 0OS<> o!erating in Saturation region# 15# ,n n0OS transistor is o!erating in saturation region 8it$ t$e *ollo8ing !arameters# VGS K 5V; Vtn K 1.2V E W/L K 115E nCox K 115 A/V 2#

<in" ranscon"uctance o* t$e "evice# 11# 1$at are "esign rulesJ 1$y is metal% metal s!acing larger t$an !oly C!oly s!acing# 12# =ra8 t$e stic( "iagram an" mas( layout *or a C0OS t8o in!ut 6O) gate an" Stic( "iagram o* t8o in!ut 6,6= gate# 13# =ra8 t$e stic( "iagram an" a translate" mas( layout *or n0OS inverter circuit# 14# >'!lain t$e *ollo8ing .a/ =ouble metal 0OS !rocess rules# .b/ =esign rules *or P% 8ell C0OS !rocess 15# =escribe t$ree sources o* 8iring ca!acitances# >'!lain t$e e**ect o* 8iring ca!acitance on t$e !er*ormance o* a :LS9 circuit# 16# =e*ine an" e'!lain t$e *ollo8ingD i# S$eet resistance conce!t a!!lie" to 0OS transistors an" inverters# ii# Stan"ar" unit o* ca!acitance# 1&# >'!lain t$e requirement an" *unctioning o* a "elay unit# 1+# 8o n0OS inverters are casca"e" to "rive a ca!acitive loa" CLK14Cg as s$o8n in <igure# Calculate t$e !air "elay :in to :out in terms o* *or t$e given "ata# 9nverter %, LP.UK 12 ; 1P.U K 4 ; LP.d K 1 ; 1P.d K 1 9nverter %? LP.UK 4 ; 1P.U K 4 ; LP.d K 2 ; 1P.d K +

!ssig9me9t2 )> #6om 5-8 89its@ 8.1.2@ Slip Tests) Sli! tests are con"ucte" in t$e class rooms# 4 sli! tests are con"ucte" !er semester !er course# 2 questions are given *or eac$ sli! test# I9st68ctio9s) Sli! test s$oul" be in 8ritten "ocuments 8it$ t$e *ollo8ing requirements# 1/ Cover !age 8it$ name; roll number; course name an" course section# 2/ , !age 8it$ questions# 3/ Solutions/>'!lanations# Slip Test1 )> #6om 89it 1a97 2@ Slip Test2 )> #6om 89it 3a97 4@ Slip Test3 )> #6om 89it 5a97 @ Slip Test4 )> #6om 89it 7a97 8@

8.2@ !ssessme9t pla9 .o6 !ctio9s) !ssessme9t pla9 .o6 !ssig9me9ts) Co9te9t P6o:lem 7esc6iptio9 Impleme9tatio9 (es8lt !ssessme9t pla9 .o6 Slip Test) Co9te9t !9al<Di9g o. p6o:lem A6iti9g (es8lt Aeig/t age 12B 82B 12B P6og6am o8tcomes aC : aC :C /C ? cC 7C ? Aeig/t age 22B 72B 12B P6og6am o8tcomes aC : aC :C /C ? cC 7C ?

E. (elatio9 o. co86se to p6og6amme o8tcomes a/ @ra"uates 8ill "emonstrate (no8le"ge o* "i**erential equations; vector calculus; com!le' variables; matri' t$eory; !robability t$eory; !$ysics; semicon"uctor an" electronic "evices# b/ @ra"uates 8ill "emonstrate an ability to i"enti*y; *ormulate an" solve electronics an" communication engineering !roblems; c/ @ra"uate 8ill "emonstrate an ability to "esign micro8ave transmission lines .8avegui"es an" micro stri! lines/ con"uct e'!eriments on ra"io communication systems; analy3e an" inter!ret "ata# "/ @ra"uates 8ill "emonstrate an ability to analy3e; "esign micro8ave "evices; !rocess as !er nee"s an" s!eci*ications# e/ @ra"uates 8ill "emonstrate an ability to visuali3e an" 8or( on >C> laboratory an" multi"isci!linary tas(s# */ @ra"uate 8ill "emonstrate s(ills to use mo"ern electronics an" communication engineering tools; so*t 8ares an" equi!ment to analy3e !roblems# g/ @ra"uates 8ill "emonstrate (no8le"ge o* !ro*essional an" et$ical res!onsibilities# $/ @ra"uate 8ill be able to communicate e**ectively in bot$ verbal an" 8ritten *orm# i/ @ra"uate 8ill s$o8 t$e un"erstan"ing o* im!act o* electronics an" communications engineering solutions on t$e society an" also 8ill be a8are o* contem!orary issues# j/ @ra"uate 8ill "evelo! con*i"ence *or sel* e"ucation an" ability *or li*e%long learning# (/ @ra"uate 8$o can !artici!ate an" succee" in com!etitive e'aminations li(e @, >; @)>; 9>S; B,L etc# 12. Co86se O:?ecti;es 3 P6og6amme O8tcomes *at6i0

O%4ECTIVES a b c

P6og6am E78catio9 O8tcomes " e * g $ i

1 L 2 L 3 L 4 L 5 6 & L 11. "ect86e Notes >U9it-Fise@ 11.1 U9it-1

L L L L L L L L L L L L L L

L L

L L

L L

L L

1.1@

I9t6o78ctio9 to V"SI Tec/9olog<)

1.2@ope6atio9 o. *OSCP*OSCN*OS t6a9sisto6s

1.3@#a:6icatio9 o. C*OS i9;e6te6 %asic C*OS Tec/9olog< 9n early "ays o* tec$nology; t$e control gate o* t$e 0OS transistor 8as ma"e 8it$ aluminum instea" o* !olycrystalline silicon# 9t 8as "i**icult to align t$e metal over t$e c$annel !reciselyE an o**set in one "irection or ot$er 8oul" create a non%*unctioning o* t$e transistor# o overcome t$ese !roblems; t$e !oly%silicon gate 8as intro"uce"# $is !olysilicon 8oul" be "e!osite" be*ore source/"rain "i**usion# =uring t$e "i**usion; source an" "rain regions are sel*%aligne" 8it$ res!ect to t$e gate# $is sel*%alignment structure re"uces t$e "evice si3e# 9n a""ition; it eliminates t$e large overla! ca!acitance bet8een gate an" "rain; 8$ile maintaining a continuous inversion layer bet8een source an" "rain# 9n t$e case o* metal gate !rocess; ,l "e!osition $as to be carrie" out almost at t$e en" o* *abrication because *urt$er $ig$ tem!erature !rocessing 8oul" melt ,l# 9n case o* sel*% aligne" !oly silicon gate tec$nology; t$ese restrictions are also circumvente"# %asic 9-Fell C*OS p6ocess 9n a stan"ar" n%8ell !rocess; one o* t$e *irst t$ings ma"e is t$e n%8ell in a ! ty!e substrate# Once t$e n%8ell is create"; t$e active areas can be "e*ine"# $e 0OS<> is buil" 8it$in t$is active area# , very t$in layer o* silicon "io'i"e is gro8n on t$e sur*ace# $is 8ill be use" to insulate t$e gate *rom t$e sur*ace# $e t$in layer o* SiO 2 is gro8n an" covere" 8it$ Si364# $is 8ill act as a mas( "uring t$e subsequent c$annel sto! im!lant an" *iel" o'i"e gro8t$# $e c$annel sto! im!lant is to !revent con"uction bet8een unrelate" transistor source/"rains# , t$ic( a""itional layer o'i"e gro8s in bot$ "irections vertically 8$ere Si364 is absent# Layer o* silicon "io'i"e un"er t$e !olysilicon gate .8$ic$ 8ill be create" later/ is (no8n as gate o'i"e an" t$at is not "irectly un"er t$e gate o* a transistor is (no8n as *iel" o'i"e# $e *iel" o'i"e !rovi"es isolation bet8een transistors# , t$res$ol" a"justment im!lant 8oul" be t$e ne't !rocess ste!# $is is carrie" out to balance o** t$e t$res$ol" voltage "i**erences# $e P%0OS results in a $ig$er t$res$ol" voltage level t$an n0OS 8it$ normal "o!ing concentrations# 1it$ a""itional negative c$arges burie" insi"e t$e c$annel; : *or !0OS coul" be controlle"# .a/

#o6matio9 o. 9-Fell >:@

'ate o0i7e co;e6e7 Fit/ silico9 9it6i7e i9 t/e acti;e a6eas Polysilicon "e!osition is carrie" out an" gate "e*inition is t$en com!lete" using t$e mas( s$o8n in *ig .c/# 6ote t$at t$e connection bet8een t8o gate in!uts in a C0OS inverter is ac$ieve" using t$e !oly silicon# $e source an" "rain "i**usions *or !0OS is carrie" out using !%ty!e "i**usion# ?oron is t$e most !o!ular element use" *or t$is ste!# Similarly; source an" "rain "i**usions *or n0OS is carrie" out using n%ty!e "i**usion# P$os!$orous an" ,rsenic can bot$ be use" *or t$is ste!# ,""itional o'i"e is create"; an" t$en t$e contact $oles are cut in t$e o'i"e "o8n to t$e "i**usions an" !olysilicon# $ese contacts can be *ille" by metal !ermitte" to *lo8 into t$e $oles# $e "rains o* !0OS an" n0OS transistors are connecte" by a metal line in or"er to ta(e t$e out!ut *rom t$e C0OS inverter#

Top ;ieF o. Pol< silico9 mas1 ."/

Pol< silico9 gate 7e.i9itio9 is complete7 >e@

T6a9sisto6 so86ce376ai9 7i..8sio9 is complete7

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C6oss sectio9 o. a C*OS i9;e6te6 i9 a9 9-Fell p6ocess P-Fell p6ocess Prior to t$e n%8ell !rocess !%8ell !rocess 8as !o!ular# P%8ell !rocess is !re*erre" in circumstances 8$ere balance" c$aracteristics o* t$e n0OS an" !0OS are nee"e"# 9t $as been observe" t$at t$e transistors in t$e native substrate ten" to $ave better c$aracteristics t$an t$at 8as ma"e in a 8ell# ?ecause ! "evices in$erently $ave lo8er gain t$an "evices; n 8ell !rocess am!li*ies t$is "i**erence 8$ile a !%8ell !rocess mo"erates t$e "i**erence# $e stan"ar" !%8ell !rocess ste!s are is similar to n%8ell !rocess; e'ce!t t$at a !%8ell is im!lante" instea" o* an n%8ell as a *irst ste!# Once t$e !%8ell is create"; t$e active areas an" subsequently !oly gates can be "e*ine"# Later "i**usions can be carrie" out to create source an" "rain regions# <inally; metal is "e!osite" an" !atterne" *or contacts# TFi9-T8: p6ocess 9t is also !ossible to create bot$ a !%8ell an" an n%8ell *or t$e n%0OS<> Ns an" !% 0OS<> res!ectively in t$e t8in 8ell or t8in tub tec$nology# Suc$ a c$oice means t$at t$e !rocess is in"e!en"ent o* t$e "o!ant ty!e o* t$e starting substrate .!rovi"e" it is only lig$tly "o!e"/#

! simpli.ie7 s1etc/ o. tFi9-Fell C*OS p6ocess c6oss sectio9

9n lit$ogra!$y *or micromac$ining; t$e !$otosensitive material use" is ty!ically a !$otoresist .also calle" resist; ot$er !$otosensitive !olymers are also use"/# 1$en resist is e'!ose" to a ra"iation source o* a s!eci*ic a 8avelengt$; t$e c$emical resistance o* t$e resist to "evelo!er solution c$anges# 9* t$e resist is !lace" in a "evelo!er solution a*ter selective e'!osure to a lig$t source; it 8ill etc$ a8ay one o* t$e t8o regions .e'!ose" or une'!ose"/# 9* t$e e'!ose" material is etc$e" a8ay by t$e "evelo!er an" t$e une'!ose" region is resilient; t$e material is consi"ere" to be a !ositive resist .s$o8n in *igure 2a/# 9* t$e e'!ose" material is resilient to t$e "evelo!er an" t$e une'!ose" region is etc$e" a8ay; it is consi"ere" to be a negative resist .s$o8n in *igure 2b/#

#ig86e 2) a/ Pattern definition in positive resist; b/ Pattern definition in negative resist

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12. U9it Fise 58estio9 %a91 >S8:?ecti;e = O:?ecti;e@ 12.1 7nit%1 769 %1 1# =escribe t$e t8o commonly use" met$o"s *or obtaining integrate" ca!acitor# 2# 1it$ neat s(etc$es; e'!lain in "etail; all t$e ste!s involve" in electron lit$ogra!$y !rocess# 3# 1$at is 0ooreIs la8J >'!lain its relevance 8it$ res!ect to evolution o* 9C ec$nology# 4# 1$at is t$e si3e o* silicon 8a*er use" *or manu*acturing state%o*%t$e art :LS9 9CsJ 5# 1$at is t$e minimum *eature si3e o* current commercial :LS9 "evicesJ 6# >'!lain t$e *ollo8ingD .a/ $ermal o'i"ation tec$nique .b/ Ginetics o* t$ermal o'i"ation# &# 1it$ neat s(etc$es e'!lain $o8 6P6 transistor is *abricate" in bi!olar !rocess# +# 1it$ neat s(etc$es e'!lain $o8 =io"es an" )esistors are *abricate" in n0OS Process# 4# 1it$ neat s(etc$es e'!lain C0OS *abrication using n%8ell !rocess# 15# 1it$ neat s(etc$es e'!lain t$e *abrication o* C0OS inverter using !%8ell !rocess#

11# >'!lain in "etail about 60OS en$ancement mo"e o* o!eration# 12# >'!lain in "etail t$e o!eration o* 60OS "e!letion mo"e transistor# 13# >'!lain t$e !rocess o* ion%im!lantation#

769 %2 1# >'!lain various regions o* C0OS inverter trans*er c$aracteristics# 2# <or a C0OS inverter; calculate t$e s$i*t in t$e trans*er c$aracteristic curve 1$en On/O! ratio is varie" *rom 1/1 to 15/1# 3# >'!lain n0OS inverter an" latc$ u! in C0OS circuitsJ 4# =ra8 t$e n0OS transistor circuit mo"el an" e'!lain various com!onents o* $e mo"el# 5# Com!are t$e relative merits o* t$ree "i**erent *orms o* !ull u! *or an inverter Circuits# 1$at is t$e best c$oice *or reali3ation in .a/ 60OS tec$nology .b/ C0OS tec$nology 6# >'!lain t$e o!eration o* ?iC0OS inverterJ Clearly s!eci*y its c$aracteristics# &# >'!lain $o8 t$e ?iC0OS inverter !er*ormance can be im!rove"# +# =e*ine t$res$ol" voltage o* a 0OS "evice an" e'!lain its signi*icance# 4# >'!lain t$e e**ect o* t$res$ol" voltage on 0OS<> current >quations# 15 1it$ neat s(etc$es e'!lain t$e *ormation o* t$e inversion layer in n%c$annel >n$ancement 0OS<> # 11# , P0OS ransistor is o!erate" in t$e trio"e region 8it$ t$e *ollo8ing !ara meters# :@S K P4#5:E :t! K P1: E :=S K P2#2: E 1/L K 45E QnCo' K45 Q,/: 2 <in" its "rain current an" "rain source resistance# 12# Clearly e'!lain t$e sub%t$res$ol" con"uction o* t$e 0OS<> # 13# S$o8 t$at s8itc$ing s!ee" o* an en$ancement 0OS<> various inversely as $e square o* c$annel lengt$# 14# =erive an equation *or 9=S o* an n%c$annel >n$ancement 0OS<> o!erating in Saturation region# 15# ,n n0OS transistor is o!erating in saturation region 8it$ t$e *ollo8ing !arameters# :@S K 5:E :tn K 1#2: E 1/L K 115E QnCo' K 115 Q,/: 2# <in" ranscon"uctance o* t$e "evice# 769 %3 1# 1$at is a stic( "iagramJ =ra8 t$e stic( "iagram an" layout *or a C0OS 9nverter# 2# 1$at are t$e e**ects o* scaling on :tJ

3# 1$at are "esign rulesJ 1$y is metal% metal s!acing larger t$an !oly C!oly s!acing# 4# =ra8 t$e stic( "iagram an" mas( layout *or a C0OS t8o in!ut 6O) gate an" Stic( "iagram o* t8o in!ut 6,6= gate# 5# =ra8 t$e stic( "iagram an" a translate" mas( layout *or n0OS inverter circuit# 6# >'!lain t$e *ollo8ing .a/ =ouble metal 0OS !rocess rules# .b/ =esign rules *or P% 8ell C0OS !rocess &# =esign a stic( "iagram *or t8o in!ut n%0OS 6,6= an" 6O) gates# +# =esign a stic( "iagram *or t$e 60OS logic s$o8n belo8 R K ., S ? S C/I # 4# =esign a stic( "iagram *or n%0OS >'%6O) gate# 15# =esign a stic( "iagram *or t$e P0OS logic s$o8n belo8 R K .., S ?/#C/I# 11# =esign a layout "iagram *or t$e P0OS logic s$o8n belo8 R K .,?/I S .C=/I# 12# =esign a layout "iagram *or n0OS inverter 13# >'!lain about t$e *ollo8ing .a/ Lamb"a % base" "esign rules .b/ =ouble metal !rocess rules# 769 %4 1# Calculate t$e rise time an" *all time o* t$e C0OS inverter .1/L/nK 6 an" .1/L/!K+; GTn K155Q ,/: 2; :tn K5#&:; GT!K 62 Q ,/: 2; :t!K%5#+5:; :== K3#3:# otal out%!ut ca!acitance K155 *<# 2# >'!lain t$e conce!t o* s$eet resistance an" a!!ly it to com!ute t$e O6 resis tance .:== to @6=/ o* an 60OS inverter $aving !ull u! to !ull "o8n ratio O* 4D1; 9* n c$annel resistance is )sn K 154 !er square# 3# Calculate t$e gate ca!acitance value o* 5Qm tec$nology minimum si3e transistor 1it$ gate to c$annel ca!acitance value is 4 U 15 %4!</Qm2# 4# =escribe t$ree sources o* 8iring ca!acitances# >'!lain t$e e**ect o* 8iring ca!acitance on t$e !er*ormance o* a :LS9 circuit# 5# =e*ine an" e'!lain t$e *ollo8ingD i# S$eet resistance conce!t a!!lie" to 0OS transistors an" inverters# ii# Stan"ar" unit o* ca!acitance# 6# >'!lain t$e requirement an" *unctioning o* a "elay unit# &# 8o n0OS inverters are casca"e" to "rive a ca!acitive loa" CLK14Cg as s$o8n in <igure# Calculate t$e !air "elay :in to :out in terms o* V *or t$e given "ata# 9nverter %, LP#7K 12W ; 1P#7 K 4 W ; LP#" K 1 W ; 1P#" K 1 W 9nverter %?

LP#7K 4W ; 1P#7 K 4 W ; LP#" K 2 W ; 1P#" K + W

+# Calculate on resistance o* t$e circuit s$o8n in <igure 1 *rom :== to @6=# 9* n% C$annel s$eet resistance )sn K 15 4 !er square an" !%c$annel s$eet resistance )s! K 2#5 U 154 !er square#

4# Calculate t$e gate ca!acitance value o* 2Qm tec$nology minimum si3e transistor 8it$ gate to c$annel ca!acitance value is + U 15P4!</Qm2# 15# >'!lain clearly about "i**erent !arasitic ca!acitances o* an n0OS transistor# 769 %5 1# >'!lain t$e C0OS system "esign base" on t$e "ata !at$ o!erators 8it$ a suitable e'am!le# 2# =ra8 an" e'!lain t$e basic 0emory% c$i! arc$itecture# 3# >'!lain t$e C0OS system "esign base" on t$e "ata !at$ o!erators 8it$ a suitable e'am!le# 4# =ra8 an" e'!lain t$e basic 0emory% c$i! arc$itecture# 5# Com!are t$e "i**erent ty!es o* C0OS subsystem 0ulti!liers# 6# =esign a sc$ematic *or an +%8or" U 2%bit 6,6= )O0 t$at serves a loo(u! table to im!lement a *ull a""er# &# =ra8 t$e sc$ematic *or tiny XO) gate an" e'!lain its o!eration# +# =ra8 t$e circuit "iagram *or 4%by%4 barrel s$i*ter using com!lementary trans% mission gates an" e'!lain its s$i*ting o!eration# 4# >'!lain about t$e *ollo8ing gate array base" ,S9CS .a/ C$annel gate arrays .b/ C$annel less gate arrays .c/ Structure" gate arrays 769 %6 1# >'!lain t$e *unction o* 4D1 0u' in P,L C0OS "evice 8it$ t$e $el! o* 9/O structure# 2# >'!lain $o8 t$e !ass transistors are use" to connect 8ire segments *or t$e !ur!ose o* <P@, !rogramming#

3# >'!lain t$e met$o"s o* !rogramming o* P,L C0OS "evice# 4# =ra8 an" e'!lain t$e arc$itecture o* an <P@,# 5# 1$at are t$e c$aracteristics o* 22:15 P,L C0OS "evice an" "ra8 its 9/O structure# 6# >'!lain any one c$i! arc$itecture t$at use" t$e anti*use an" give its a"vantages# &# =ra8 t$e ty!ical stan"ar"%cell structure s$o8ing lo8%!o8er cell an" e'!lain it# +# S(etc$ a "iagram *or t8o in!ut XO) using PL, an" e'!lain its o!eration 8it$ t$e $el! o* trut$ table# 4# 7sing PL, 9m!lement HG <li! *lo! circuit 15#1it$ neat s(etc$es e'!lain t$e arc$itecture o* P,L 769 %& 1# 1rite a :B=L Program *or a "ivi"e%by%3 counter 8it$ suitable state "iagram# 2# Com!are all available "esign veri*ication tools# 3# 1$at are t$e "i**erent ty!es o* o!erators use" in :B=LJ @ive some e'am!les using t$is# 4# Com!are t$e Circuit%level; Logic%level; s8itc$%level an" iming simulations# 5# 1$at are t$e "i**erent "ata ty!es available in :B=L an" $o8 t$ey are in"icate"J 6# 1rite a :B=L !rogram *or a 4%bit Counter 8it$ ,sync$ronous reset# &# 1$at are t$e a"vantages o* Bar"8are =escri!tion Languages an" give some e'am!lesJ +# >'!lain t$e "i**erent ty!es o* simulators use" to !re"ict an" veri*y t$e !er*ormance o* given circuit# 4# 1$at are t$e in!uts t$at are !rovi"e" to t$e synt$esis toolJ ,n" e'!lain com!letely about synt$esis !rocess in t$e ,S9C "esign# 15# >'!lain t$e *ollo8ing !rocesses in t$e ,S9C "esign *lo8# .a/ Post % layout timing simulation# .b/ Post synt$esis simulation# 11# 1it$ res!ect to synt$esis !rocess e'!lain t$e *ollo8ing terms# ,/ <lattening ?/ <actoring C/ 0a!!ing

769 %+ 1# =ra8 t$e basic structure o* !arallel scan an" e'!lain $o8 it re"uces t$e long scan c$ains# 2# =ra8 t$e state "iagram o* ,P Controller an" e'!lain $o8 it !rovi"es t$e control signals *or test "ata an" instruction register# 3# =ra8 t$e basic structure o* !arallel scan an" e'!lain $o8 it re"uces t$e long scan c$ains# 4# =ra8 t$e state "iagram o* ,P Controller an" e'!lain $o8 it !rovi"es t$e

control signals *or test "ata an" instruction register# 5# Com!are *unctionality test an" manu*acturing test# 6# 1$at ty!e o* testing tec$niques are suitable *or t$e *ollo8ingD i# 0emories ii# )an"om logic iii# =ata !at$# &# Bo8 9==2 testing is use" to test t$e bri"ge *aultsJ +# >'!lain $o8 an im!rove" layout can be re"uce" *aults in C0OS circuits# 4# >'!lain $o8 a !seu"o ran"om sequence generator may be use" to test a 16%bit"ata !at$# Bo8 8oul" t$e out!uts be collecte" an" c$ec(e"# 15# >'!lain about t$e *ollo8ing !ac(aging "esign consi"erations# .a/ :LS9 "esign rules# .b/ $ermal "esign consi"eration# UNIT-1 O?H>C 9:> 27>S 9O6S 1 0OS 0eans .a/ 0etal o'i"e silicon tec$nology .b/ 0etal o'i"e semicon"uctor tec$nology .c/ ,ny o* .a/ an" .b/ ."/ 6one 2 n 0OS "evices are *orme" in aYYYYYYYYYYYYYsubstrate o* mo"erate "o!ing level# .a/ P % ty!e .c/ >it$er a an" b 3 .a/ n % ty!e .b/ ! % ty!e .c/ >it$er a .or/ b ."/ 6one 4 $e connections to t$e source an" "rain are ma"e by a "e!osite"YYYYYYYYYYlayer .a/ P "i**usion .b/ n "i**usion .c/ >!itanial ."/ 0etal 5 ,Y gate is "e!osite" on a layer o* insulation over t$e region bet8een source an" "rain in a en$acement mo"e "evice .b/ n % ty!e ."/ 6one

$e source an" "rain in a n 0OS "evice are *orme" by "i**usingYYYYYYYYYYYim!urities#

.a/ O'i"e .c/ 0etal an" "rain .c/ .a/ 6on con"ucting layer .c/ Con"ucting Layer &

.b/ Polysilicon ."/ 6one#

6 9* t$e gate is connecte" to a suitable !ositive voltage t$en a is *orme" bet8een source .b/ e!ita'ial Layer ."/ 6one voltage to t$e gate .b/ Positive ."/ 6one#

$e source an" "rain are connecte" by a con"ucting c$annel but t$e c$annel may no8

be cleare" by a!!lying a suitable .a/ 6egative .c/ Aero

+ 9n a Pmos "evice t$e substrate is o*YYYYYYYYYYty!e material .a/ n % ty!e .c/ >it$er a or b 4 $e source an" "rain material are ty!e in a !0OS "evice .a/ ! ty!e .c/ >it$er a or b .a/ n % 8ell !rocess .c/ ?ot$ a an" b tec$nology .a/ C0OS .b/ L .c/ ?i % C0OS ."/ 6one 12 $e ?i C0OS n!n transistor consists o* .a/ PSbase region .b/ nS collector area .c/ ?urie" subcollector ."/ ,ll t$e above 13 Process simulation can be "one *or t$e *ollo8ing !rocess in 9C *abrication .a/ Lit$ogra!$y .b/ im!lantation .c/ >tc$ing ."/ ,ll t$e above 14 O'i"ation in 9C *abrication re*ers to t$e c$emical !rocess o* reaction o* OY8it$YYYYYYY .a/ Si 8it$ O 2 .b/ Si 8it$ 6 2 .c/ Si 8it$ B 2 ."/ 6one .b/ n ty!e ."/ none# .b/ ! % 8ell !rocess ."/ 6one .b/ !%ty!e

15 $e *abrication o* C0OS is "one by

11 $e Limite" "eive ca!ability o* 0OS transistors can be overcome byYYYYYYYYYYYYYYY

15 $e *ollo8ing is a ty!e o* o'i"ation .a/ $ermal o'i"ation .b/Big$ !ressure o'i"ation .c/ Plasma o'i"ation ."/ ,ll t$e above 16 $ermal o'ia"ation is "one in .a/ )esistance $eate" o'i"ation *urnace .b/ 9on im!lantation *urnace .c/ >it$er a or b ."/ 6one# 1& $e o'i"i3ing s!ecies are trans!orte" *rom t$e bar( o* t$e gas !$ase to gas o'i"e intergace 8it$ *le' .a/ < .b/ < 2 .c/ < 3 ."/ 6one# 1+ $e *lu' < is given by < K $ @ (CG - Cs) 8$ere $ @ is .a/ @as !$ase 0aes trans*er coe**icient .b/ Liqui" !$ase 0aes trans*er coe**icient .c/ Soli" !$ase 0aes trans*er coe**icient ."/ 6one# 14 $e rate o* o'i"ation "e!en"s on .a/ Su!!ly o* o'i"ant to inter*ace .b/ $e reaction rate constant )S an" Ci .c/ ?ot$ a an" b ."/ 6one# 25 $e $ig$ % !ressure o'i"ation !rocess is a!!lie" to t$e o'i"e isolation o*YYYYYYYYYYYY LS9 8it$ *ully ion im!lante" s$allo8 junctions an" multi level metalli3or# .a/ Big$ s!ee" bi!olar .b/ Lo8 s!ee" bi!olar .c/ Big$ s!ee" C0OS

."/ Lo8 s!ee" C0OS UNIT-2

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13.UNIVE(SIT$ 5UESTION P!PE(S)

III %.Tec/ II Semeste6 (eg8la6 E0ami9atio9sC !p63*a< 222E V"SI &ESI'N Co"e 6oD )55325452 Set 6o# 1 1# 1it$ neat s(etc$es e'!lain t$e 9on %lit$ogra!$y !rocess# Z16[ 2# .a/ >'!lain "i**erent *orms o* !ull u!s use" as loa"; in C0OS an" in en$ancement - "e!letion mo"es o* 60OS# .b/ =etermine t$e !ull u! to !ull "o8n ratio o* an n0OS inverter "riven by anot$er n0OS transistor# Z+S+[ 3# =esign a stic( "iagram an" layout *or t8o in!ut C0OS 6,6= gate in"icating all t$e regions - layers Z16[ 4# =escribe t$e *ollo8ing brie*ly .a/Casca"e" inverters as "rivers# .b/ Su!er bu**ers# .c/ ?iC0OS "rivers# Z+S4S4[ 5# >'!lain brie*ly t$e C0OS system "esign base" on t$e "ata !at$ o!erators; memory elements; control structures an" 9/O cells 8it$ suitable e'am!les# Z16[ 6# .a/ =ra8 an" e'!lain t$e <P@, c$i! arc$itecture# .b/ =ra8 an" e'!lain t$e ,6=/6O) re!resentation o* PL,# Z+S+[ &# .a/ 1rite a :B=L !rogram *or &%sengment "is!lay "eco"er# .b/ 1$at are t$e basic sources o* errors in C0OS circuits an" $o8 t$ese are teste"J @ive name o* suc$ a simulator# Z+S+[ +# .a/ >'!lain t$e gate level an" *unction level o* testing# .b/ , sequential circuit 8it$ inJ in!uts an" \mI storage "evices# o test t$is circuit $o8 many test vectors are require"# .c/ 1$at is sequential *ault gra"ingJ >'!lain $o8 it is analy3e"# Z6S4S6[ Co"e 6oD )55325452 Set 6o# 2 1# 1rite in "etail about integrate" !assive com!onents# Z16[ 2# .a/ >'!lain t$e o!eration o* ?iC0OS inverterJ Clearly s!eci*y its c$aracteristics# .b/ >'!lain $o8 t$e ?iC0OS inverter !er*ormance can be im!rove"# Z+S+[ 3# .a/ 8$at is a stic( "iagramJ =ra8 t$e stic( "iagram an" layout *or a C0OS inverter# .b/ 1$at are t$e e**ects o* scaling on :tJ .c/ 1$at are "esign rulesJ 1$y is metal% metal s!acing larger t$an !oly %!oly s!acing# Z+S4S4[

4# .a/ =etermine an equation *or t$e !ro!agation "elay *rom in!ut to out!ut o* t$e !ass transistor c$ain s$o8n in *igure 4a 8it$ t$e $el! o* its equivalent circuit#

<igure 4a .b/ 1$at are su!er ?u**ersJ Z12S4[ 5# .a/ >'!lain $o8 a ?oot$ reco"e" multi!lier re"uces t$e number o* a""ers# .b/ =ra8 circuit "iagram o* a one transistor 8it$ transistor ca!acitor "ynamic ),0 an" also "ra8 its layout# Z+S+[ 6# .a/ =ra8 t$e ty!ical arc$itecture o* P,L an" e'!lain t$e o!eration o* it# .b/ 1$at is CPL=J =ra8 its basic structure an" give its a!!lications# Z+S+[ &# .a/ 1$at is meant by enumeration ty!e o* "ata an" give some e'am!le *or itJ .b/ 1$at are t$e "i**erent Libraries use" in :B=LJ 1rite t$e synta' to loa" it# .c/ >'!lain $o8 t$e "elay o* a statement is relate" to simulation an" synt$esis# Z6S6S4[ +# .a/ 1$at is , P@J >'!lain a met$o" o* generation o* test vector# .b/ >'!lain t$e terms controllability; observability an" *ault coverage# Z+S+[ Co"e 6oD )55325452 Set 6o# 3 1# >'!lain t$e 0OS ransistor o!eration 8it$ t$e $el! o* neat s(etc$es in t$e *ollo8ing mo"es .a/ >n$ancement mo"e .b/ =e!letion mo"e# Z+S+[ 2# .a/ =ra8 an n0OS transistor mo"el in"icating all t$e com!onents# .b/ >'!lain latc$ u! !roblem in C0OS circuits# Z+S+[ 3# .a/ 1$at is 0ooreIs la8J >'!lain its relevance 8it$ res!ect to evolution o* tec$ nology# .b/ 1$at are "i**erent :LS9 tec$nologies available com!are t$eir s!ee"/!o8er !er*ormance# .c/ 1$y is :LS9 "esign !rocess !resente" in 60OS onlyJ ."/ =iscuss t$e micro electronics evolution# Z6S4S2S4[ 4# .a/ >'!lain cloc(e" C0OS logic; "omino logic an" n%! C0OS logic# .b/ 9n gate logic; com!are t$e geometry as!ects bet8een t8o %in!ut 60OS 6,6= an" C0OS 6,6= gates# Z+S+[

5# .a/ =esign a magnitu"e com!arator base" on t$e "ata !at$ o!erators# .b/ =ra8 t$e Sc$ematic an" mas( layout o* array a""er use" in ?oot$ 0ulti!lier an" e'!lain t$e !rinci!le o* multi!lication in ?oot$ 0ulti!lier# Z6S15[ 6# .a/ 1$at are t$e c$aracteristics o* 22:15 P,L C0OS "evice an" "ra8 its 9/O structure# .b/ >'!lain any one c$i! arc$itecture t$at use" t$e anti*use an" give its a"vantages# Z+S+[ &# .a/ 1$at are t$e a"vantages o* Bar"8are =escri!tion Languages an" So*t8are LanguagesJ .b/ 1$at are "i**erent "esign veri*ication tools an" e'!lain t$em in brie*J Z+S+[ +# .a/ =ra8 t$e basic structure o* !arallel scan an" e'!lain $o8 it re"uces t$e long scan c$ains# .b/ =ra8 t$e state "iagram o* ,P Controller an" e'!lain $o8 it !rovi"es t$e control signals *or test "ata an" instruction register# Z+S+[ Co"e 6oD )55325452 Set 6o# 4 1# .a/ 1it$ neat s(etc$es e'!lain t$e 60OS *abrication !roce"ure# .b/ =ra8 t$e cross sectional vie8 o* C0OS P % 1ell inverter# Z+S+[ 2# .a/ =erive an equation *or ranscon"uctance o* an n c$annel en$ancement 0OS<> o!erating in active region# .b/ , P0OS transistor is o!erate" in trio"e region 8it$ t$e *ollo8ing !arameters# :@SK% 4#5:; :t!K %1:E :=SK%2#2 :; .1/L/ K45; QnCo' K45Q,/: 2# <in" its "rain current an" "rain source resistance# Z+S+[ 3# .a/ =iscuss "esign rule *or 8ires .orbit 2Qm C0OS/# .b/ =iscuss t$e transistor relate" "esign rule .orbit 2Qm C0OS/# Z+S+[ 4# 8o 60OS inverters are casca"e" to "rive a ca!acity loa" CLK 14Cg as s$o8n in *igure 4#

Calculate t$e !air "elay :in to :out in terms o* V *or t$e given "ata inverter%,# Z16[

L!uK12W; 1!uK4W; L!"K1W; 1!"K+W 9nverter%? L!uK4W; 1!uK4W; L!"K2W; 1!"K+W <igure 4 5# .a/ =esign a magnitu"e com!arator base" on t$e "ata !at$ o!erators# .b/ =ra8 t$e Sc$ematic an" mas( layout o* array a""er use" in ?oot$ 0ulti!lier an" e'!lain t$e !rinci!le o* multi!lication in ?oot$ 0ulti!lier# Z6S15[ 6# 1rite brie*ly aboutD .a/ C$annelle" gate arrays .b/ C$annelless gate arrays 8it$ neat s(etc$es# Z+S+[ &# .a/ Bo8 to re!resent a tristate in :B=L an" e'!lain it 8it$ suitable !rogram# .b/ 1$at is ratIs%nest 8iring "iagramJ >'!lain its signi*icance in system "esign# Z+S+[ +# .a/ =ra8 t$e basic structure o* !arallel scan an" e'!lain $o8 it re"uces t$e long scan c$ains# .b/ =ra8 t$e state "iagram o* ,P Controller an" e'!lain $o8 it !rovi"es t$e control signals *or test "ata an" instruction register# Z+S+[ III %.Tec/ S8pplime9ta6< E0ami9atio9sC !8g3Sep 2228 V"SI &ESI'N Co"e 6oD )55325452 Set 6o# 1 1# 1it$ neat s(etc$es e'!lain ?9C0OS *abrication !rocess in an 6 8ell# Z16[ 2# .a/ 1it$ neat s(etc$es; e'!lain t$e trans*er c$aracteristic o* a C0OS inverter# .b/ =erive an equation *or 9"s o* an n%c$annel en$ancement 0OS<> o!erating in saturation region# Z+S+[ 3# =esign a stic( "iagram an" layout *or t$e 60OS logic s$o8n belo8 R K .., S ?/C/1 Z16[ 4# .a/ >'!lain cloc(e" C0OS logic; "omino logic an" n%! C0OS logic# .b/ 9n gate logic; com!are t$e geometry as!ects bet8een t8o %in!ut 60OS 6,6= an" C0OS 6,6= gates# Z+S+[ 5# .a/ =ra8 t$e to! level sc$ematic an" a *loor !lan *or 16 U 16 ?oot$ reco"e" multi!lier an" e'!lain its o!eration# .b/ >'!lain t$e tra"eo**s bet8een o!en; close"; an" t8iste" bit lines in a "ynamic ),0 array# Z+S+[ 6# .a/ =ra8 an" e'!lain t$e ,nti*use Structure *or !rogramming t$e P,L "evice# .b/ >'!lain $o8 t$e 9/O !a" is !rogramme" in <P@,# Z+S+[ &# .a/ 1rite a arc$itecture *or a 4% bit Counter in bot$ be$avioral an" structural

styles# .b/ >'!lain 8it$ e'am!le $o8 mi'e" mo"e simulator are more *or C0OS circuits testing# Z+S+[ +# .a/ 1$at are t$e reasons o* mal*unctioning o* c$i!J 1$at are t$e "i**erent levels o* testingJ .b/ >'!lain $o8 a !arallel scan is use" *or "ata !at$ test# .c/ 1$at is mean by level sensitive o* logic systemJ Z6S6S4[ Co"e 6oD )55325452 Set 6o# 2 1# 1rite in "etail about integrate" !assive com!onents# Z16[ 2# .a/ >'!lain various regions o* C0OS inverter trans*er c$aracteristics# .b/ <or a C0OS inverter; calculate t$e s$i*t in t$e trans*er c$aracteristic curve 8$en On/O! ratio is varie" *rom 1/1 to 15/1# Z+S+[ 3# .a/ 1rite t$e scaling *actors *or "i**erent ty!es o* "evice !arameters# .b/ =iscuss t$e limits "ue to sub t$res$ol" currents# Z+S+[ 4# =escribe t$ree sources o* 8iring ca!acitances# >'!lain t$e e**ect o* 8iring ca!acitance on t$e !er*ormance o* a :LS9 circuit# Z16[ 5# .a/ =ra8 t$e sc$ematic *or tiny XO) gate an" e'!lain its o!eration# .b/ =ra8 t$e circuit "iagram *or 4%by%4 barrel s$i*ter using com!lementary trans% mission gates an" e'!lain its s$i*ting o!eration# Z+S+[ 6# .a/ =ra8 an" e'!lain t$e ,nti*use Structure *or !rogramming t$e P,L "evice# .b/ >'!lain $o8 t$e 9/O !a" is !rogramme" in <P@,# Z+S+[ &# .a/ Com!are t$e Bar"8are an" So*t8are Languages# .b/ =ra8 t$e basic "esign *lo8 t$roug$ ty!ical C0OS :LS9 tools an" give some names o* corres!on"ing tools# Z+S+[ +# .a/ 1$at ty!e o* "e*ects are teste" in manu*acturing testing met$o"sJ .b/ 1$at is t$e =esign *or ,utonomous est an" 8$at is t$e basic "evice use" in t$isJ .c/ 1$at ty!e o* tests are use" to c$ec( t$e noise margin *or C0OS gatesJZ4S6S6[ Co"e 6oD )55325452 Set 6o# 3 1# 1it$ neat s(etc$es necessary; e'!lain t$e o'i"ation !rocess in t$e 9C *abrication !rocess# Z16[ 2# .a/ =ra8 an n0OS transistor mo"el in"icating all t$e com!onents# .b/ >'!lain latc$ u! !roblem in C0OS circuits# Z+S+[ 3# .a/ =iscuss in "etial t$e 60OS "esign style# .b/ =iscuss C0OS "esign style# Com!are 8it$ 60OS "esign style# Z+S+[

4# =escribe t$ree sources o* 8iring ca!acitances# >'!lain t$e e**ect o* 8iring ca!acitance on t$e !er*ormance o* a :LS9 circuit# Z16[ 5# .a/ >'!lain $o8 a ?oot$ reco"e" multi!lier re"uces t$e number o* a""ers# .b/ =ra8 circuit "iagram o* a one transistor 8it$ transistor ca!acitor "ynamic ),0 an" also "ra8 its layout# Z+S+[ 6# .a/ =ra8 t$e ty!ical stan"ar"%cell structure s$o8ing regular%!o8er cell an" e'% !lain it# .b/ =ra8 an" e'!lain t$e !seu"o%n0OS PL, sc$ematic *or *ull a""er an" 8$at are t$e a"vantages an" "isa"vantages o* it# Z+S+[ &# .a/ >'!lain $o8 :B=L is "evelo!e" an" 8$ere it 8as use" initially# .b/ 1$at are t$e "i**erent "esign ca!ture toolsJ >'!lain t$em brie*ly# Z+S+[ +# .a/ >'!lain $o8 *unction o* system can be teste"# .b/ >'!lain any one o* t$e met$o" o* testing bri"ge *aults# .c/ 1$at ty!e o* *aults can be re"uce" by im!roving layout "esignJ Z6S5S5[ Co"e 6oD )55325452 Set 6o# 4 1# 1it$ neat s(etc$es; e'!lain in "etail; all t$e ste!s involve" in electron lit$ogra!$y !rocess# Z16[ 2# .a/ =erive an equation *or r"s o* an n c$annel en$ancement 0OS<> in linear region# .b/ Plot t$e trans*er c$aracteristic o* an n0OS inverter as a *unction o* :"s#Z+S+[ 3# .a/ =iscuss in "etial t$e 60OS "esign style# .b/ =iscuss C0OS "esign style# Com!are 8it$ 60OS "esign style# Z+S+[ 4# .a/ >'!lain t$e requirement an" o!eration o* !ass transistors an" transmission gates# .b/ Com!are !seu"o%n 0OS logic an" cloc(e" C0OS logic# Z+S+[ 5# .a/ Bo8 can t$e com!onents o* C0OS system "esign be categori3e" into t$e grou!s# .b/ 1$y is t$e static 6 transistor cell use" *or average C0OS system "esignJ .c/ Com!are t$e !er*ormance o* C0OS O** c$i! an" On c$i! memory "esigns# Z4S6S6[ 6# .a/ =ra8 a sel* time" "ynamic PL, an" 8$at are t$e a"vantages o* it com!are" to *oote" "ynamic PL,# .b/ >'!lain t$e tra"eo**s bet8een using a transmission gate or a tristate bu**er to im!lement an <P@, routing bloc(# Z+S+[

&# .a/ 1$at are t$e "i**erent ty!es o* o!erators use" in :B=LJ @ive some e'am!les using t$is# .b/ Com!are t$e Circuit%level; Logic%level; s8itc$%level an" iming simulations# Z+S+[ +# .a/ >'!lain t$e gate level an" *unction level o* testing# .b/ , sequential circuit 8it$ JnJ in!uts an" \mI storage "evices# o test t$is circuit $o8 many test vectors are require"# .c/ 1$at is sequential *ault gra"ingJ >'!lain $o8 it is analy3e"# Z6S4S6[

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