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Version 2.02

PowerPC Operating Environment Architecture

Book III

Version 2.02

January 28, 2005

Manager:

Joe Wetzel/Poughkeepsie/IBM

Technical Content:

Ed Silha/Austin/IBM

Cathy May/Watson/IBM

Brad Frey/Austin/IBM

Junichi Furukawa/Austin/IBM

Giles Frazier/Austin/IBM

Version 2.02

The following paragraph does not apply to the United Kingdom or any country or state where such provisions are inconsistent with local law.

The specifications in this manual are subject to change without notice. This manual is provided “AS IS”. Inter- national Business Machines Corp. makes no warranty of any kind, either expressed or implied, including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose.

International Business Machines Corp. does not war- rant that the contents of this publication or the accom- panying source code examples, whether individually or as one or more groups, will meet your requirements or that the publication or the accompanying source code examples are error-free.

This publication could include technical inaccuracies or typographical errors. Changes are periodically made to the information herein; these changes will be incorpo- rated in new editions of the publication.

Address comments to IBM Corporation, Internal Zip 9630, 11400 Burnett Road, Austin, Texas 78758-3493. IBM may use or distribute whatever information you supply in any way it believes appropriate without incur- ring any obligation to you.

The following terms are trademarks of the International Business Machines Corporation in the United States and/or other countries:

IBM

POWER2

PowerPC

RISC/System 6000

POWER4+

POWER

POWER4

IBM System/370

Notice to U.S. Government Users&mdash.Documenta- tion Related to Restricted Rights&mdash.Use, duplica- tion or disclosure is subject to restrictions set fourth in GSA ADP Schedule Contract with IBM Corporation.

© Copyright International Business Machines Corpora- tion, 1994, 2003. All rights reserved.

Version 2.02

Preface

This document defines the additional instructions and facilities, beyond those of the PowerPC User Instruc- tion Set Architecture and PowerPC Virtual Environment Architecture, that are provided by the PowerPC Operat- ing Environment Architecture. It covers instructions and facilities not available to the application program- mer, affecting storage control, interrupts, and timing facilities.

Other related documents define the PowerPCUser Instruction Set Architecture, the PowerPC Virtual Envi- ronment Architecture, and PowerPC Implementation Features. Book I, PowerPC User Instruction Set Archi- tecture defines the base instruction set and related facilities available to the application programmer. Book II, PowerPC Virtual Environment Architecture defines the storage model and related instructions and facilities available to the application programmer, and the Time Base as seen by the application programmer. Book IV, PowerPC Implementation Features defines the imple- mentation-dependent aspects of a particular implemen- tation.

As used in this document, the term PowerPC Architec- turerefers to the instructions and facilities described in Books I, II, and III. The description of the instantiation of the PowerPC Architecture in a given implementation includes also the material in Book IV for that implemen- tation.

Note: Change bars indicate changes relative to Version

2.01.

Version 2.02

Version 2.02

Table of Contents

Chapter 1.

Introduction

 

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1.1 .

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1.2 Compatibility with the POWER Archi-

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1.3

Document Conventions

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1

1.3.1

Definitions and

 

1

1.3.2

Reserved

2

1.4

General Systems Overview

 

3

1.5

Exceptions

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3

1.6

Synchronization

 

4

1.6.1

Context Synchronization

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4

1.6.2

Execution Synchronization

 

4

1.7

Logical Partitioning

 

5

1.7.1

Logical Partitioning Control Register

(LPCR)

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1.7.2

Real Mode Offset Register (RMOR)6

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1.7.3

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Hypervisor Real Mode Offset Regis- .

1.7.4

Logical Partition

 

Identification Register (LPIDR)

 

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1.7.5 Other Hypervisor Resources

 

7

1.7.6 Sharing Hypervisor Resources

 

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Chapter 2.

 

Branch Processor

 

9

2.1

Branch Processor Overview

 

9

2.2

Branch Processor

 

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2.2.1

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Machine Status Save/Restore Regis- .

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2.2.2

Hypervisor Machine Status Save/

 

Restore Registers

 

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2.2.3

Machine State Register

 

10

2.3

Branch Processor Instructions

 

12

2.3.1

System Linkage Instructions

12

Chapter 3.

Fixed-Point Processor 15

3.1

Fixed-Point Processor Overview

 

15

3.2

Special Purpose Registers

 

15

3.3

Fixed-Point Processor Registers

 

15

3.3.1

Data Address

 

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3.3.2

Data Storage Interrupt

 

Status Register

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3.3.3 Software-use SPRs

 

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3.3.4 Control

 

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3.3.5 Processor Version Register

 

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3.3.6 Processor Identification Register. 17

3.4

Fixed-Point Processor Instructions . 18

3.4.1

OR Instruction

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3.4.2

Move To/From System Register

Instructions

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Chapter 4.

Storage Control

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4.1

Storage

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4.2

Storage Model

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4.2.1

Storage Exceptions

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4.2.2

Instruction Fetch

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4.2.3

Data Access .

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4.2.4

Performing Operations

Out-of-Order

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4.2.5

4.2.6

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32-Bit Mode

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29

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4.2.7

Uses

Address Ranges Having Defined .

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4.2.8

Invalid Real Address

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4.3

Address Translation Overview

32

4.4

Virtual Address Generation

33

4.4.1

Segment Lookaside Buffer (SLB). 33

4.4.2

SLB Search

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4.5

Virtual to Real Translation

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4.5.1

Page Table

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4.5.2

Storage Description

Register 1

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4.5.3

Page Table

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4.6

Data Address

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4.7

Data Address Breakpoint

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4.8

Storage Control Bits

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4.8.1

Storage Control Bit Restrictions

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4.8.2

Altering the Storage Control Bits . 42

4.9

Reference and Change Recording . 43

4.10

Storage

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4.10.1

Storage Protection, Address Trans-

lation Enabled

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4.10.2 Storage Protection, Address Trans-

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4.11

Storage Control Instructions

 

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4.11.1

Cache Management Instructions 47

4.11.2

Synchronize Instruction

 

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4.11.3

Lookaside Buffer

 

Management

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4.12

Page Table Update

 

Synchronization Requirements

 

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4.12.1

Page Table

 

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Version 2.02

Chapter 5.

Interrupts

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61

5.1

Overview

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5.2

Interrupt Synchronization

 

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5.3

Interrupt Classes

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5.3.1

Precise Interrupt

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5.3.2

Imprecise Interrupt

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5.4

Interrupt

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5.4.1

Hypervisor

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5.5

Interrupt Definitions

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5.5.1

System Reset Interrupt

 

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5.5.2

Machine Check

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5.5.3

Data Storage

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5.5.4

Data Segment

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5.5.5

Instruction Storage Interrupt

 

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5.5.6

Instruction Segment

Interrupt

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5.5.7 External

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5.5.8 Alignment Interrupt

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5.5.9 Program Interrupt

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5.5.10 Floating-Point Unavailable .

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5.5.11 Decrementer Interrupt

 

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5.5.12 Hypervisor Decrementer .

Interrupt

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5.5.13 System Call

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5.5.14 Trace

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5.5.15 Performance Monitor

 

Interrupt (Optional)

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5.6

Partially Executed

Instructions

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5.7

Exception Ordering

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5.7.1

Unordered

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5.7.2

Ordered Exceptions

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5.8

Interrupt

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Chapter 6.

Timer

79

6.1

Overview

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6.2

Time Base

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6.2.1

Writing the Time

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6.3

6.3.1

Decrementer

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menter

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6.4 Hypervisor Decrementer

 

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6.5 Processor Utilization of Resources

 

Register

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Chapter 7.

Synchronization

Requirements for Context Alterations

85

Chapter 8.

Optional Facilities and

Instructions

89

8.1

External Control

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8.1.1

External Access Register

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8.1.2

External Access Instructions

 

90

8.2

Real Mode Storage Control

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8.3

Move to Machine State Register

 

Instruction .

8.4

tions

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Chapter 9.

Optional Facilities and

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92

Instructions that are being Phased

Out

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9.1

Bridge to SLB Architecture

 

93

9.1.1

Segment Register

 

Manipulation Instructions

 

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93

Appendix A.

 

Assembler Extended

Mnemonics

97

A.1

Move To/From Special Purpose Regis-

98

ter Mnemonics

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Appendix B.

Cross-Reference for

Changed POWER

 

101

Appendix C.

New and Newly

 

Optional Instructions

 

103

Appendix D.

Interpretation of the

DSISR as Set by an Alignment .

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105

Appendix E.

Example Performance

Monitor (Optional)

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107

E.1

PMM Bit of the Machine State Register

108

E.2

Special Purpose Registers

 

109

E.2.1

Performance Monitor Counter Regis-

ters

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109

E.2.2

Monitor Mode Control Register 1 112

E.2.3

 

Monitor Mode Control Register A113

E.2.4

Sampled Instruction Address Regis-

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113

E.2.5

Sampled Data Address Register 114

114

E.3

Performance Monitor

E.4

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Appendix F.

Example Trace

Extensions (Optional)

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Appendix G.

PowerPC Operating

Environment Instruction Set

.119

Version 2.02

Figures

1. Logical view of the PowerPC processor architecture

 

3

42. GPR contents for mtsr, mtsrin, mfsr, and .

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93

2. Logical Partitioning Control

 

5

43. Performance Monitor SPR encodings for

 

3. Real Mode Offset Register

6

mtspr and mfspr

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109

4. Hypervisor Real Mode Offset Register

 

6

44. Performance Monitor Counter

 

109

5. Logical Partition Identification Register

7

45. Monitor Mode Control Register 0

 

110

6. Save/Restore Registers

 

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9

46. Monitor Mode Control Register 1

112

7. Hypervisor Save/Restore Registers

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47. Monitor Mode Control Register

 

113

8. Machine State

 

10

48. Sampled Instruction Address

 

113

9. Data Address Register

 

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49. Sampled Data Address Register

 

114

10. Data Storage Interrupt Status Register

 

16

11. SPRs for use by privileged non-hypervisor pro-

grams .

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12. SPRs for use by hypervisor

 

16

13. Control Register

 

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14. Processor Version

 

17

15. Processor Identification

 

17

16. Priority hint levels for or

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17. SPR encodings for mtspr

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18. SPR encodings for mfspr

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19. Address translation overview

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20. Translation of 64-bit effective address to 80-bit virtual address

 

33

21. SLB Entry

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22. Translation of 80-bit virtual address to 62-bit real

address

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23. Page Table

 

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24. .

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25. Address Compare Control Register

 

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26. Data Address Breakpoint Register

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27. Data Address Breakpoint Register Extension .

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28. Storage control bits .

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29. Setting the Reference and Change bits

 

44

30. PP bit protection states, address translation

 

45

31. Protection states, address translation

 

disabled

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32. GPR contents for slbmte

 

51

33. GPR contents for slbmfev

 

52

34. GPR contents for slbmfee

52

35. MSR setting due to interrupt

 

65

36. Effective address of interrupt vector by

 

interrupt type

 

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37. Time

Base

 

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38. Decrementer

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80

39. Hypervisor Decrementer

 

81

40. Processor Utilization of Resources

 

82

41. External Access Register

 

89

Version 2.02

Version 2.02

Chapter 1. Introduction

1.1 .

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1

1.7

Logical Partitioning (LPAR)

 

5

1.2 Compatibility with the POWER Archi-

1.7.1

Logical Partitioning Control Register

tecture

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5

1.3

Document Conventions

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1.7.2 Real Mode Offset Register (RMOR)6

1.3.1

Definitions and

 

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1.7.3 Hypervisor Real Mode Offset Regis-

1.3.2

Reserved

 

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ter (HRMOR)

 

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1.4

General Systems Overview

 

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1.7.4

Logical Partition

 

1.5

Exceptions

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Identification Register (LPIDR)

 

7

1.6

Synchronization

 

4

1.7.5 Other Hypervisor Resources

 

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1.6.1

Context Synchronization

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1.7.6 Sharing Hypervisor Resources

 

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1.6.2

Execution Synchronization

 

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1.1 Overview

Chapter 1 of Book I, PowerPC User Instruction Set Architecture describes computation modes, compatibil- ity with the POWER Architecture, document conven- tions, a general systems overview, instruction formats, and storage addressing. This chapter augments that description as necessary for the PowerPC Operating Environment Architecture.

1.2 Compatibility with the

POWER Architecture

The PowerPC Architecture provides binary compatibil- ity for POWER application programs, except as described in the appendix entitled Incompatibilities with the POWER Architecturein Book I, PowerPC User Instruction Set Architecture. Binary compatibility is not necessarily provided for privileged POWER instructions.

1.3 Document Conventions

The notation and terminology used in Book I apply to this Book also, with the following substitutions.

For system alignment error handlersubstitute Alignment interrupt.

For system data storage error handlersubstitute Data Storage interrupt, Data Segment interrupt,

or Data Storage or Data Segment interrupt, as appropriate.

For system floating-point enabled exception error handlersubstitute Floating-Point Enabled Excep- tion type Program interrupt.

For system error handlersubstitute interrupt.

For system illegal instruction error handlersubsti- tute Illegal Instruction type Program Interrupt.

For system instruction storage error handlersub- stitute Instruction Storage interrupt, Instruction Segment interrupt, or Instruction Storage or Instruction Segment interrupt, as appropriate.

For system privileged instruction error handlersubstitute Privileged Instruction type Program interrupt.

For system service programsubstitute System Call interrupt, as appropriate.

For system trap handlersubstitute Trap type Program interrupt.

1.3.1 Definitions and Notation

The definitions and notation given in Book I, PowerPC User Instruction Set Architecture are augmented by the following.

A real page is a 4 KB unit of real storage that is aligned at a 4 KB boundary.

Version 2.02

The context of a program is the environment (e.g., privilege and relocation) in which the program exe- cutes. That context is controlled by the contents of certain System Registers, such as the MSR and SDR1, of certain lookaside buffers, such as the SLB and TLB, and of the Page Table.

An exception is an error, unusual condition, or external signal, that may set a status bit and may or may not cause an interrupt, depending upon whether the corresponding interrupt is enabled.

An interrupt is the act of changing the machine state in response to an exception, as described in Chapter 5. Interruptson page 61.

A trap interrupt is an interrupt that results from exe- cution of a Trap instruction.

Additional exceptions to the rule that the processor obeys the sequential execution model, beyond those described in the section entitled Instruction Fetchingin Book I, are the following.

- A System Reset or Machine Check interrupt may occur. The determination of whether an instruction is required by the sequential exe- cution model is not affected by the potential occurrence of a System Reset or Machine Check interrupt. (The determination is affected by the potential occurrence of any other kind of interrupt.)

- A context-altering instruction is executed (Chapter 7. Synchronization Requirements for Context Alterationson page 85). The context alteration need not take effect until the required subsequent synchronizing operation has occurred.

- A Reference and Change bit is updated by the processor. The update need not be per- formed with respect to that processor until the required subsequent synchronizing operation has occurred.

Hardware means any combination of hard-wired implementation, emulation assist, or interrupt for software assistance. In the last case, the interrupt may be to an architected location or to an imple- mentation-dependent location. Any use of emula- tion assists or interrupts to implement the architecture is described in Book IV, PowerPC Implementation Features.

instruction, in a register, or in an architected stor- age table.

/, //, ///,

denotes a field that is reserved in an

1.3.2 Reserved Fields

Some fields of certain architected storage tables may be written to automatically by the processor, e.g., Ref- erence and Change bits in the Page Table. When the

processor writes to such a table, the following rules are obeyed.

Unless otherwise stated, no defined field other than the one(s) the processor is specifically updat- ing are modified.

Contents of reserved fields are either preserved by the processor or written as zero.

The handling of reserved bits in System Registers described in Book I applies here as well. The reader should be aware that reading and writing of some of these registers (e.g., the MSR) can occur as a side effect of processing an interrupt and of returning from an interrupt, as well as when requested explicitly by the appropriate instruction (e.g., mtmsrd).

Programming Note

Software should set reserved fields in architected storage tables (e.g., the Page Table) to zero, because these fields may be assigned a meaning in some future version of the architecture.

Version 2.02

1.4 General Systems Overview

The processor or processor unit contains the sequenc- ing and processing controls for instruction fetch, instruction execution, and interrupt action. Instructions that the processing unit can execute fall into three classes: