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2 Marks ( )
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Institute of Engineering Studies (IES,Bangalore)
Leading Institute for GATE/IES/JTO/PSUs in (Branches @ Jayanagar &Malleshwaram) Bangalore.
Contact: (+91) 99003 99699 E-Mail: onlineies.com@gmail.com Site: www.onlineies.com
Branch :--EC/EE/IN Subject: Analog Electronics Topic: Op Amp
Total Questions :120 Practice Questions for Classroom & Postal Series Students
Common Data for Q1 and Q2 is given below
Consider op-amp ideal
1)Find input resistance
[A] 2 K [B] 3 K
[C]6.47 K [D]1 K
2)Find the ratio
[A] 3 [B] 2.66
[C]1.66 [D]2.5
3)For an amplifier having a slew rate of 60 v/sec, what is the highest frequency at which a 20 (peak to
peak) sine wave can be produced at the output ?
[A] 47.74 kHz [B] 1 MHz
[C]20 kHz [D]95.5 kHz
4)Find the value of R to get _ = 9.8 mA and _ = 0.7V
[A] 1.02 k [B] 640.3
[C]949 [D]378
5)For a type 741 op- amp ( = 9.5 A and = 30 PF) then the slew rate is
[A] 0.92 V/ sec [B] 0.63 V/ sec
[C]0.56 V/ sec [D]0.72 V/ sec
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. [QAnaA052] .. 2 Marks ( )
. [QAnaA055] .. 2 Marks ( )
6)The circuit in figure is
[A] LPF [B] Notch Filter
[C]HPF [D]All pass filter
7)TheSchmitt trigger is shown in figure. The hysteresis is
[A] [B]
[C] [D]
8)Assertion (a) : An Op-Amp can perform mathematical operations like scaling, addition, integration,
differentiation etc. Such building blocks can be suitably connected to obtain an analog computer
Reason (r) : A differentiator is not used in analog computer because it amplifier noise and other unwanted
signals as its inputs.
[A] Both (a) and (r) are true and (r) is the correct
reason for (a)
[B] Both (a) and (r) are true and (r) is not the correct
reason for (a)
[C]Both (a) and (r) are false [D](a) is true but (r) is false
9)Thecommon mode rejection ratio of a diff amp with parameters = 10V, = - 10V,JQ = 0.8 mA and
= 12 k .The transistor parameters are = 100, = .Assume the output resistance looking into the
constant current source is = 25 K .Use a one sided output at . TheCMRR in dBs
[A] 42.3 dB [B] 51.8 dB
[C]72.3 dB [D]82.1 dB
10)Consider the Schmitt trigger in figure with parameters = 10 K and = 90 k . Let = 10V and =
- 10V . Determine the hysteresis
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. [QAnaA057] .. 2 Marks ( )
. [QAnaA059] .. 2 Marks ( )
. [QAnaA060] .. 2 Marks ( )
. [QAnaA061] .. 2 Marks ( )
[A] 5 V [B] 4 V
[C]3 V [D]2 V
11)For the RC phase shift oscillator in figure , the parameters are R = 10 K and C = 100 PF . The required
value of at = 65 KHz
[A] 320 K [B] 570 K
[C]290 K [D]720 K
12)For the circuit shown in figure equals to
[A] [B]
[C] [D]
13)For the correct shown in figure
[A] [B]
[C] [D]
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. [QAnaA081] .. 1 Marks ( )
. [QAnaA089] .. 2 Marks ( )
. [QAnaA090] .. 2 Marks ( )
14)
Consider the deferential amplifier shown in the figure. Let 10 and = 11. Determine CMRR
(dB)
[A] 52.1 dB [B] 22.4 dB
[C]62.1 dB [D]41.6 dB
15)For the amplifier circuit shown in figure , is
[A] 100 V [B] 22 V
[C]11 V [D]None
16)The expression for the output voltage in terms of the input voltage and in the circuit shown in the
figure , assuming the operational amplifier to be ideal is :
The values of and would be respectively
[A] 9 and - 10 [B] 9.9 and -10
[C]- 9 and 10 [D]- 9.9 and 10
17)The circuit connection of op-amp given in figure (i) and figure (ii) represent
[A] logarithmic amplifiers for both figures (i) and (ii) [B] detectors for both figures (i) and (ii)
[C]detector for figure (i) and logarithmic amplifier for
figure (ii)
[D]logarithmic amplifier for figure (i) and detector for
figure (ii)
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. [QAnaA092] .. 2 Marks ( )
. [QAnaA093] .. 2 Marks ( )
. [QAnaA096] .. 2 Marks ( )
. [QAnaA099] .. 1 Marks ( )
18)In the op-amp circuit shown below , >0 and . The output voltage will be proportional to
[A] [B]
[C] [D]
19)In the given circuit , if the voltage inputs and are to be amplified the same amplification factor , the
value of 'R' should be
[A] r = 33 k [B] r = 12 k
[C]r = 58 k [D]r = 22 k
20)Calculate output voltage ¤t for the circuit
[A] = 5 V , = 1 mA [B] = 5 V , = 1.5 mA
[C] = 5 V , = 0.5 mA [D]None
21)Assume that the operational amplifier in figure is ideal . The current ' I' through the 1k ohm resistor is
[A] - 4 mA [B] - 2 mA
[C]2 mA [D]4 mA
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. [QAnaA105] .. 1 Marks ( )
. [QAnaA107] .. 2 Marks ( )
. [QAnaA109] .. 2 Marks ( )
22)For the op-amp, BJT circuit shown assume = 4 for BJT , and op-amp to be ideal. Which is the correct
statement , assume BJT be in active region and power supply will be 10 V
[A] terminal A is inverting and = 1V [B] terminal A is non - inverting and = 1V
[C]terminal A is inverting and = 1.25 V [D]terminal A is non - inverting and = 1.25 V
23)In the figure shown, what is the value of
[A] 10 V [B] 8 V
[C]6 V [D]2 V
24)For the circuit shown assume op-amp to be ideal and are identical and have
. What is the value of
[A] 4.2 V [B] 3 V
[C]4 V
[D]can not be determined as op-amp is in positive
feedback
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. [QAnaA110] .. 2 Marks ( )
. [QAnaA124] .. 2 Marks ( )
. [QAnaA127] .. 2 Marks ( )
. [QAnaA137] .. 2 Marks ( )
. [QAnaA141] .. 2 Marks ( )
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. [QAnaA147] .. 2 Marks ( )
25)Input the op-amp circuit is sine wave of peak value of 10V. What is the duty cycle of output
[A] 0.55 [B] 0.45
[C]0.5 [D]1
26)
Assertion(A): Op-Amps with FET input stages have less gain than those with BJT
Reason(R) : BJT has higher transconductance than FET
[A] Both A and R are true and R is the correct
explanation of A
[B] Both A and R are true but R is NOT the correct
explanation of A
[C]A is true but R is false [D]A is false but R is true
27)In single stage differential amplifier , the output offset voltage is basically dependent on the mismatch of
[A] , and [B] and
[C] and [D] and
28)
Assertion(A) : In an op-amp circuit when one input terminal of the op-amp is grounded, the other terminal
becomes a virtual ground
Reason(R) : Input impedance of the op-amp is high
[A] both A and R are true and R is the correct
explanation of A
[B] both A and R are true but R is NOT the correct
explanation of A
[C]A is true but R is false [D]A is false but R is true
29)
In a 741 op-amp, there is 20 dB/decade fall-off starting at a relatively low frequency . This is due to the
[A] applied load [B] internal compensation
[C]impedance of the source [D]power dissipation in the chip
30)
The input differential stage of op-Amp 741 is biased at about 10 A current .Such a low current of the input
stage gives
1.high CMRR 2. high differential gain
3. low differential gain 4. high input impedance
Which of these are correct ?
[A] 1 and 2 [B] 1,2 and 4
[C]3 and 4 [D]1,2,3 and 4
31)
Assertion(A) : Operational amplifiers should have a high slew rate for good transient response
Reason(R): Slew rate is the maximum rate of change of the output voltage of the operational amplifier
when a large amplitude step is applied to its input
[A] both A and R are true and R is the correct
explanation of A
[B] both A and R are true but R is NOT the correct
explanation of A
[C]A is true but R is false [D]A is false but R is true
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. [QAnaA148] .. 2 Marks ( )
. [QAnaA150] .. 2 Marks ( )
. [QAnaA162] .. 2 Marks ( )
. [QAnaA167] .. 2 Marks ( )
. [QAnaA185] .. 2 Marks ( )
32)
Assertion(A) : An operational amplifier can amplify very low frequency including d.c signals
Reason(R) : op-amp uses very large coupling capacitor for cascading the various stages
[A] both A and R are true and R is the correct
explanation of A
[B] Both A and R are true but R is NOT the correct
explanation of A
[C]A is true but R is false [D]A is false but R is true
33)
An operational amplifier possesses
[A] very large input resistance and very large output
resistance
[B] very small input resistance and very small output
resistance
[C]very large input resistance and very small output
resistance
[D]very small input resistance and very large output
34)consider the following circuit :
What is the function of diode D2 in the above circuit ?
[A] To avoid saturation of the op-Amp
[B] To provide negative feedback when the input is
negative
[C]To reduce reverse breakdown voltage of D1 [D]As a buffer
35)Cosider the following circuit :
How does the above circuit work
[A] As a logarithmic amplifier [B] As a negative clipper
[C]As a positive clipper [D]As a half-wave rectifier
36)
Consider the following statements :
Dominant pole frequency compensation in an OP-AMP
1.increases the slow-rate of the OP-AMP
2. Increases the stability of the OP-AMP
3. Reduces the bandwidth of the OP-AMP
4.reduces the CMRR of the OP-AMP
Which of the statements given above are correct ?
[A] 1 and 3 only [B] 1,2 and 4
[C]1 and 2 only [D]2 and 3 only
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. [QAnaA189] .. 2 Marks ( )
. [QAnaA190] .. 2 Marks ( )
. [QAnaA191] .. 2 Marks ( )
. [QAnaA199] .. 2 Marks ( )
37)What is the output voltage of the below circuit ?
[A] -1.1 V [B] 1.1 V
[C]1.0 V [D]10 V
38)What is the output voltage of the below circuit ?
[A] -11 V [B] 6 V
[C]11 V [D]-6 V
39)For the circuit of figure with an ideal operational amplifier, the maximum phase shift of the output with
reference to the input is
[A] [B]
[C] [D]
40)Assuming the operational amplifier to be ideal the gain for the circuit shown in figure is
[A] - 1 [B] - 20
[C]- 100 [D]- 120
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. [QAnaA215] .. 2 Marks ( )
. [QAnaA216] .. 2 Marks ( )
. [QAnaA235] .. 2 Marks ( )
. [QAnaA239] .. 2 Marks ( )
. [QAnaA240] .. 1 Marks ( )
. [QAnaA241] .. 2 Marks ( )
41)
Consider the following statements :
1. stray capacitance at the input terminal of an op-amp effectively introduces an additional phase lag
network in feedback loop
2.stray capacitance depends upon the value of resistor used in feedback
3.Low value of resistances has higher effects on stray capacitance
4.High value of resistances has higher effects on stray capacitance.
Which of the statements given above are correct ?
[A] 1,2 and 3 [B] 2,3 and 4
[C]1,3 and 4 [D]1,2 and 4
42)
A differential amplifier has inputs , = 1050 V and = 950 V with CMRR = 1000. What is the error in the
differential output ?
[A] 10% [B] 1%
[C]0.1% [D]0.01%
43)Inthe circuit shown above , what is the value of transfer function ?
[A] [B]
[C] [D]
44)
For a given op-amp, CMRR = and differential gain = . What is the common mode gain of the op-amp
?
[A] [B] 2 x
[C] [D]1
45)The voltage comparator shown in figure can be used in the analog to-digital conversion as
[A] a 1-bit quantizer [B] a 2- bit quantizer
[C]a 4- bit quantizer [D]a 8- bit quantizer
46)For the circuit given below , what is equal to ?
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. [QAnaA254] .. 2 Marks ( )
. [QAnaA255] .. 2 Marks ( )
. [QAnaA267] .. 2 Marks ( )
[A] V/ [B] V/R
[C]V /( R+ ) [D]V /( 2R+ )
47)In the active filter circuits shown in figure, if Q= 1, a pair of poles will be realized with equal to
[A] 1000 rad/s [B] 100 rad/s
[C]10 rad/s [D]1 rad/s
48)The input resistance of the circuit in figure is
[A] + 100 k [B] - 100 k
[C]+ 1 M [D]- 1 M
49)
What is the load current I
L
in the circuit below ?
[A]
-5 mA
[B] -10 mA
[C]+25 mA [D]+50 mA
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. [QAnaA268] .. 2 Marks ( )
. [QAnaA269] .. 2 Marks ( )
. [QAnaA271] .. 2 Marks ( )
50)Consider the inverting amplifier using an ideal operational amplifier shown in the figure. The designer
wishes to realize the input resistance seen by the small-signal source to be as large as possible, while
keeping the voltage gain between 10 and 25. the upper limit on is 1 M . The value of should be
[A] Infinity [B] 1 M
[C]100 k [D]40 k
51)
Consider the following circuit :
What is the value of in the above circuit, if the voltage and are to be amplified by the same
amplification factor ?
[A] 7 k [B] 22 k
[C]33 k [D]35 k
52)Consider the following Op-Amp circuit:
What is the output voltage in the above Op-amp circuit ?
[A] 10 V [B] -10 V
[C]11 V [D]-11 V
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. [QAnaA272] .. 2 Marks ( )
. [QAnaA273] .. 2 Marks ( )
. [QAnaA281] .. 2 Marks ( )
53)
Consider the following circuit :
Which one of the following expressions for is correct ?
[A]
[B]
[C] [D]
54)In the given figure, if the input is a sinusoidal signal, the output will appear as shown in
[A]
[B]
[C]
[D]
55)
In the op-amp circuit shown above (assuming ideal op-amp)
The output voltage is
[A]
= -5 V
[B] = + 5 V
[C] = 0 [D] = - 2V
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. [QAnaA282] .. 2 Marks ( )
. [QAnaA283] .. 2 Marks ( )
. [QAnaA295] .. 2 Marks ( )
. [QAnaA298] .. 2 Marks ( )
56)The current through the resistor R in the below circuit is
[A]
1 mA
[B] 4 mA
[C]8 mA [D]10 mA
57)
The stage marked X in the shown below architecture of a two-stage op-amp is
[A] Direct coupled amplifier 1. [B] buffer amplifier
[C]Level shifter [D]Blocking oscillator
58)
A non inverting op-amp is shown below (assume ideal op-amp)
The output voltage for an input = [ 2+ sin(100 t)] V
[A] 3/2 sin (100 t) [B] 3 sin (100t)
[C]2 sin(100 t) [D]3 sin (100 t) +1/2
59)
An op-amp circuit is shown in the figure
The output will be (assume ideal op-amp)
[A] equal to zero because the input is zero
[B] dependent on element values hence nothing can
be predicted without a knowledge of element
values
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. [QAnaA303] .. 1 Marks ( )
[C]a square wave varying between + and - [D]a sinusoidal wave of amplifier
60)For a given sinusoidal input voltage, the voltage waveform at point P of the clamper circuit shown in figure
will be
[A]
[B]
[C]
[D]
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. [QAnaA306] .. 2 Marks ( )
. [QAnaA309] .. 2 Marks ( )
. [QAnaA316] .. 2 Marks ( )
61)An op-amp circuit is shown in the figure given below. Different inputs and output are given under List-I and
List-II . Match List-I(inputs) with List-II(Outputs) and select the correct answer using the codes given below
the lists :
Codes: A B C D
[A] 2 4 1 3 [B] 1 3 2 4
[C]2 3 1 4 [D]1 4 2 3
62)
In a circuit , if the open loop gain is and output voltage is 10 volt, the differential voltage should be
[A] 10 V [B] 0.1 V
[C]100 V [D]1 V
63)In the circuit shown in the given figure, is given by
[A]
Sin(t /4)
[B] sin(t+ /4)
[C]sin t [D]cos t
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. [QAnaA320] .. 2 Marks ( )
. [QAnaA324] .. 2 Marks ( )
. [QAnaA327] .. 2 Marks ( )
. [QAnaA331] .. 2 Marks ( )
64)In the circuit shown in the given figure, the current flowing through resistance of 100 would be
[A]
8 mA
[B] 10 mA
[C]20 mA [D]100 mA
65)The op-amp circuit shown in the given figure is
[A]
a high pass circuit
[B] a low-pass circuit
[C]a band-pass circuit [D]an all-pass circuit
66)
Consider the following statements :
A totem pole configuration used in the output stage of an op-amp has the advantage of using
1.only n-p-n BJTs
2.complementary symmetrical pair of transistors
3.only one transistor
Which of these statements is/are correct ?
[A] 1 alone [B] 2 alone
[C]3 alone [D]1 and 3
67)The of the Op-Amp circuit shown in the given figure is
[A]
11
[B] 10
[C] [D]Zero
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Class room coaching | Postal series | Online tests | Forums | Counselling & Guidance for GATE/IES/JTO/PSU
. [QAnaA332] .. 2 Marks ( )
. [QAnaA333] .. 2 Marks ( )
. [QAnaA334] .. 2 Marks ( )
68)The voltage gain versus frequency curve of an Op-Amp is shown in the given figure
The gain-bandwidth product of the Op-Amp is