MDLOGIC SOLUTIONS - #4 Arcot Road, Kodambakkam, Chenna !4 "!

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A-STRACT The Combinational circuit which we designed was NAND-based digitally controlled delay-lines (DCDL) present a glitching problem which may limit their employ in many applications. This paper presents a glitch-free NAND-based DCDL which o ercame this limitation by opening the employ of NAND-based DCDLs in a wide range of applications. The proposed NAND-based DCDL maintains the same resolution and minimum delay of pre iously proposed NAND-based DCDL. The theoretical demonstration of the glitch-free operation of proposed DCDL is also deri ed in the paper. !ollowing this analysis" three dri ing circuits for the delay control-bits are also proposed. #roposed DCDLs ha e been designed in a $%-nm C&'( technology and compared" in this technology" to the state-of-the-art. (imulation results show that no el circuits result in the lowest resolution" with a little worsening of the minimum delay with respect to the pre iously proposed DCDL with the lowest delay. (imulations also confirm the correctness of de eloped glitching model and si)ing strategy. As e*ample application" proposed DCDL is used to reali)e an All-digital spread-spectrum cloc+ generator (((C,). The employ of proposed DCDL in this circuit allows to reduce the pea+-to-pea+ absolute output -itter of more than the .%/ with respect to a ((C, using three-state in erter based DCDLs. /0ISTING S1ST/M 0n the e*isting design DCDLs ha e been designed in a $%-nm C&'( technology" to the state-of-the-art. (imulation results show that no el circuits result in the lowest resolution" with a little worsening of the minimum delay with respect to the pre iously proposed DCDL with the lowest delay. 1e erify the logic in (imulations itself which tells the correctness of de eloped glitching model and si)ing strategy. As e*ample application" e*isting DCDL is used to reali)e an All-digital spreadspectrum cloc+ generator (((C,). The employ of e*isting DCDL in this circuit allows

MDLOGIC SOLUTIONS - #4 Arcot Road, Kodambakkam, Chenna !4 "!##$##"4# % #4444##"4# md&o' c(o&)t on(*'ma &+com
to reduce the pea+-to-pea+ absolute output -itter of more than the .%/ with respect to a ((C, using three-state in erter based DCDLs. 2RO2OS/D S1ST/M 0n the proposed system to a oid glitches and -itters occur during the fast switching operation we introduce strobe controlled DCDL logic where each gate is under the control of single strobe. 1hich reduces the error more than 2%/ comparing with the pre ious method SO,T3AR/ R/4UIR/M/NT Design 3n ironment4 50L0N5 0(3 Language4 67DL (imulation4 &'D3L(0& 8 50L0N5 0(3 (imulator 5ARD3AR/ R/4UIR/M/NT 50L0N5 (#A9TAN De elopment :oard De ice4 5C;(2%%3