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Placement and Power Optimization

Learning Objectives
During this lab, you will perform design exploration then perform placement and optimization (timing, area and power). After completing this lab, you should be able to: Apply placement constraints Apply routing blockages erify design setup !erform standard cell placement and optimization "ecognize and resol#e congestion issues !erform incremental optimization

Lab Duration: 90 minutes

Placement and Power Optimization


Synopsys 20-I-071-SLG-007

Lab 2-1

Lab 2

Introduction
$n this lab, you are pro#ided with complete %"&A'(%! design data (netlist, timing constraints and floorplan) in a )ilkyway database. *ou will apply placement constraints then perform standard cell placement *ou will also perform power analysis and optimization after the placement has been completed.

Answers / Solutions
(here is an ANSWERS / SOLUTIONS section at the back of each lab. *ou are encouraged to refer often to this section to #erify your answers, or to obtain help with the execution of some steps.

elevant !iles and "irectories


All files for this lab are located in the lab2_placement directory under your home directory.
lab2_placement/ orca_lib.mw/CEL ORCA_TOP (he synthesized and floorplanned design sa#ed in +ynopsys )ilkyway format.

scripts/ physical_constraints.tcl A script used to add other physical constraints. inputs_toggle_rate.tcl A script used to set statistical toggle rates for the input ports.

Lab 2-2

Placement and Power Optimization


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Lab 2

Instructions
#as$ 1%
1.

&'ec$ing Logical "esign Setup

+tart $& &ompiler from the lab2_placement directory.


UNIX$ cd lab _place!ent UNIX$ icc_shell

2.

%pen the design library, and then make a copy for a working design cell. %pen the copied design cell to perform the placement exploration.
open_!"_lib orca_lib.!" copy_!"_cel #$ro! ORCA_TOP #to e%plore open_!"_cel e%plore Note:

)aking a copy of a cell is optional. ,owe#er, it is a good practice to work on a copy of a design cell to a#oid accidentally o#erwriting the starting design cell.

3.

erify that the clock definitions are complete:


report_cloc& report_cloc& 's&e" report_port '( )cl& Question 1.

$s the clock port specification complete...................................................................................................

Question 2.

.hat type of a port is +D'DD"'&/0 defined on...................................................................................................

Placement and Power Optimization


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Lab 2-(

Lab 2
4. !erform a timing sanity check using zero1interconnect delay mode:
set_*ero_interconnect_delay_!ode true report_ti!ing Note:

*ou can bring up the timing report in a separate window using 2#iew report'timing3 or 2# rt3. Does the design meet setup timing- +hould you worry...................................................................................................

Question 3.

5. 6.

"e#iew the answer to 4uestion 5 in the Answers section. (urn off timing for the scan enable net, since it will be handled later by place'opt:
set_ideal_net"or& +get_ports scan_en,

7. 8.

"erun the timing report. *ou should not see any #iolations now. &heck all constraint #iolations:
report_constraint 'all -or better. ( rc/

*ou should find that there are a number of hold #iolations, which we don6t care about now. Also, there are max transition and max capacitance #iolations on the reset networks, which high fanout synthesis will take care of during place'opt. 9. Don6t forget to turn off 7$&:
set_*ero_interconnect_delay_!ode $alse

Lab 2-)

Placement and Power Optimization


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Lab 2 #as$ 2%
1.

Placement *+ploration

%pen the graphical user interface (89$).


gui Note:

2gui3 is a function created for this workshop. $t calls start'gui and end'gui to open and close the 89$ depending on the current state.

2.

&heck for potential floorplan issues:


chec&_physical_design #$or_place!ent chec&_physical_constraints Question 4.

,ow many soft placement blockages exist in this design...................................................................................................

Question 5.

Does the floorplan contain narrow placement areas...................................................................................................

Question 6.

.hat is the design utilization reported after the 2:arrow !lacement Area3 messages...................................................................................................

3.

+o how is it possible that utilization is so high e#en before starting- 9se the following command to get a 4uick picture of what is going on:
create_place!ent '0uic&

4.

,a#e a look at the layout.


Question 7.

.hat may be the cause of the high utilization...................................................................................................

5.

$f you ha#e an answer to the 4uestion, #alidate your idea by executing a command to sol#e the problem. $f you don6t know, check the answer section for this 4uestion, and execute the commands gi#en there.

Placement and Power Optimization


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Lab 2-,

Lab 2
"un chec&_physical_constraints one more time. (he utilization should be less than ;<= now. >ut there are still some narrow channels reported, for which the macros are responsible.
Question 8.

.hat is the easiest solution to pre#ent congestion in the narrow channels for this floorplan................................................................................................... ...................................................................................................

6.

Apply soft and hard keepouts to the floorplan as learned in lecture:


set physopt_hard_&eepout_distance 1 set physopt_so$t_&eepout_distance 21 Note:

%f course, you may perform a placement first to confirm that the settings abo#e actually impro#e congestion, or you can take our word for it.

7.

!erform placement, so you can see how the settings applied so far affect the design:
create_place!ent legali*e_place!ent

8.

8enerate and Analyze a placement congestion map.

+elect the "eload button, confirm with %0, you should then see the congestion patterns in the layout #iew. +o far so good. (he congestion is relati#ely distributed. (here is what you could call a small congestion hot spot around the middle of the design, and between some of the "A) blocks. (he bottom areas of the design seem to be a little more congested. 9. ,a#e a look at a cell density map, to see whether the cell distribution may be problematic. +elect 2!in Density3 from the already open dialog that is used to display the congestion, or choose !lacement!in Density )ap. +et the 8rid Dimension to ? std cell heights and apply.
Lab 2-Placement and Power Optimization
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Lab 2
*ou should see that the pin distribution is pretty e#en, mostly in the 51?? range, but you also see that there is higher density in the bottom areas of the design. &lose the density map. 10. "un placement with congestion options to see if congestion in the bottom areas of the design impro#es:
create_place!ent 'congestion legali*e_place!ent

Did &ongestion impro#e$t seems that the hotspot in the middle of the design has gotten better. Also, hardly #isible, congestion in the bottom did impro#e e#ery so slightly. @ollow up with a high effort congestion placement:
create_place!ent 'congestion 'congestion_e$$ort high legali*e_place!ent

)any of the hot edges ha#e disappeared, but the hotspot in the middle is still there, although lighter o#erall. 11. @ollow up with a global route congestion map. &ompare this with the results seen in the placement congestion map. *ou should see that congestion is better in the 8" map. (hat is due to the nature of the 8" that it can route around congested areas.

#as$ (%

#iming

$t seems that congestion is more or less under control, although e#ery crossing with the power grid shows congested edges. $t is difficult to Audge right now whether this is going to cause unsol#able problems at the routing stage. *ou ha#e to consider that place'opt uses e#en more efficient congestion algorithms, and the timing optimization and buffering can change things a bit. 1. >efore going any further, analyze the timing of the placed design.
Question 9.

.hat do you conclude from the reports................................................................................................... ...................................................................................................

Placement and Power Optimization


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Lab 2-.

Lab 2
2. (o see whether the timing can be impro#ed by better placement, run the following command. (his will enable the timing1dri#en placement:
create_place!ent 'ti!ing_dri(en 'congestion 3 'congestion_e$$ort high legali*e_place!ent

3.

8enerate another timing report.


Question 10.

Did the situation impro#e...................................................................................................

(here are a number of things that you could still do to impro#e congestion, but for now, we will turn the design o#er to placement, and see how good the algorithms really perform.

#as$ )%
1.

Per/orm Placement and Optimization

&lose and discard the current 2explore3 cell:


close_!"_cel

2.

&opy and open a working design cell to perform the placement and optimization.
copy_!"_cel #$ro! ORCA_TOP #to place_opt open_!"_cel place_opt

3.

Apply the pro#ided script to add the physical design constraints you found during the pre#ious tasks:
source 'e '( scripts4physical_constraints.tcl

4.

>efore running place'opt, you need to make sure that scan information has been annotated on the design. Bxecute the following command:
report_scan_chain

$f you don6t see anything, this means that no scan chain information was loaded.

Lab 2-0

Placement and Power Optimization


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Lab 2
5. /oad the +&A:DB@ file:
read_de$ ..4re$4design_data4ORCA_TOP.scande$ ( report_scan_chain

*ou should see scan chains nowC (his information will be used during place'opt to optimize the scan chain wiring. 6. "eport the settings for high fanout synthesis:
report_ah$s_options

7.

>ased on the abo#e, and knowing the defaults (see man1page) ha#e a look at which nets are candidates for high fanout synthesis:
all_high_$anout #nets #threshold 255

As you can see, all the reset nets (D) and the scan'en net will be buffered. (he clock nets will not be buffered by place'opt. 8. >ased on your obser#ations earlier, perform a placement and optimization run while optimizing :
place_opt #opti!i*e_d$t #congestion

You may observe the output of place_opt to get an idea of the optimizations that occur, or you may take a 5-10 minute break 9. +a#e the current design as 2placed3.
sa(e_!"_cel #as placed

Placement and Power Optimization


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Lab 2-1

Lab 2
Question 11.

.hat is the standard cell utilization as reported by the chip summary in the log...................................................................................................

Question 12.

$s there a congestion hot spot that would make it difficult for the final routing...................................................................................................

Question 13.

,as the design met setup timing...................................................................................................

10.

"un the following command to ha#e a look at your high fanout nets:
report_bu$$er_tree_0or #$ro! +all_high_$anout #nets 3 #threshold 255 #through_bu$_in(,

*ou can see that the reset nets and scan'en ha#e been buffered. 11. !erform an incremental area reco#ery:
set_!a%_area 5 set physopt_area_critical_range 5.2 psynopt #area_reco(ery Note:

Any area reco#ery will lower the utilization of the standard cells and may help lower the congestion. .hat is the design utilization after the area reco#ery run...................................................................................................

Question 14.

Lab 2-12

Placement and Power Optimization


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Lab 2 #as$ ,% Incremental "3namic Power Optimization

(he goal of this task is to show the flow and the user interface of the integrated !ower &ompiler. $nstead of using the recommended flow where +A$@ is re4uired, you are pro#ided with statistical inputs for the design. 1. Bnable dynamic power optimization (disabled by default):
report_po"er_options set_po"er_options #dyna!ic true report_po"er_options

2.

+et the toggle rates for the design:


source scripts4inputs_toggle_rate.tcl Note:

:ot using +A$@ pre#ents !ower &ompiler from achie#ing a realistic power reduction.

3.

"eport and record the current dynamic power dissipation:


report_po"er

&ell $nternal !ower :et +witching !ower (otal Dynamic !ower *ou can also see the power using 2report'constraint3. 4. !erform incremental power optimization and generate a power report for comparison:
psynopt #po"er report_po"er

(he power reduction is #ery small since this is an incremental optimization and is not based on +A$@ data. Bnabling power optimization during placement and optimization (place'opt) would show a bigger reduction. !ower optimization during placement was skipped due to lab time.

Placement and Power Optimization


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Lab 2-11

Lab 2
$f you wish though, you can start a power optimization using the full place'opt flow, and look at the results in the morningC +tart with a clean design, and make sure you set the following options:
set_po"er_options 'dyna!ic true 3 #lo"_po"er_place!ent true place_opt 'congestion 'opti!i*e_d$t #po"er

5.

Bxit $& &ompiler.

Congratulations! *ou ha#e completed the placement and power optimization lab.

Lab 2-12

Placement and Power Optimization


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Answers / Solutions

Lab 2

Answers / Solutions
Question 1.

$s the clock port specification complete(he clock ports ha#e a defined dri#ing cell, and a capaciti#e loading is attached as well. (he maximum transition on the clock seems a little high (? ns), but this may be the way it was intended.

Question 2.

.hat type of a port is +D'DD"'&/0 defined on+D'DD"'&/0 is a generated clock, defined on the output port sd'&0. +d'&0 is listed in the report'clock report, with :report'port E# sd'&03 you can find out about the direction of the port.

Question 3.

Does the design meet setup timing- +hould you worry@or the normal paths, yes. (here is a path starting at scan'en that has a #ery large #iolation though. Although this path will be taken care of by ,igh @anout +ynthesis during place'opt, a big #iolation like this will throw off any timing1dri#en placement. >est to hide the #iolation during the exploration phase.

Question 4.

,ow many soft placement blockages exist in this design(here are no soft placement blockages reported by the chec&_physical_constraints command.

Question 5.

Does the floorplan contain narrow placement areas*es, many, scattered all o#er the design.

Question 6.

.hat is the design utilization reported after the 2:arrow !lacement Area3 messages&lose to 5D<=CC !lacement will not be possible with utilization that high.

Question 7.

.hat may be the cause of the high utilization(he high utilization is caused by the fact that placement is not occurring under the power straps. "un the command report_pnet_options and you will see that no placement was allowed under )B(A/?, )B(A/D and )B(A/F. $t will not be possible to place the design this way. A complete power net keepout is only recommended if you ha#e a lot of room in your floorplan. (his is not the case

Placement and Power Optimization


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Lab 2-1(

Lab 2

Answers / Solutions
here. $ssue the following commands to allow cells to 2slide3 in under the power nets if no shorts are caused:
set_pnet_options #none 678TA9 report_pnet_options Question 8. 78TA9: 78TA9;< 78TA9: 78TA9;<

set_pnet_options #partial 678TA9

.hat is the easiest solution to pre#ent congestion in the narrow channels for this floorplan*ou can control the congestion in the narrow channels by using placement keepouts. (he easiest way is to use placement blockage #ariables to define soft and hard keepouts near the macros.

Question 9.

.hat do you conclude from the reports(he timing #iolations are pretty se#ere in some cases, about 5G1?<= of the o#erall path delay. .e paid much attention to congestion, but not much to timing.

Question 10.

Did the situation impro#e(he situation impro#ed somewhat. (he timing is now better, but the congestion has degraded again slightly.

Question 11.

.hat is the standard cell utilization as reported by the chip summary in the logAround ;D=.

Question 12.

$s there a congestion hot spot that would make it difficult for the final routing:ot really, there are similar congestion patterns as found earlier though (make sure you are looking at a global route congestion map).

Question 13.

,as the design met setup timing(here should be no #iolations at all.

Question 14.

.hat is the design utilization after the area reco#ery runAround ;?=. A reduction of almost 5=C

Lab 2-1)

Placement and Power Optimization


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