Digital Electronics

Logic gates
Electronic or electrical circuits which implement Boolean operations are called logic gates. Logic gate performs logical functions. Logic gates are the basic elements that makeup a digital system. A logic gate is an electronic or electrical logic circuit with one output and one or more inputs providing a logic high output only for certain combinations of input signals. A truth table is a table that shows the output logic levels for all the input possibilities of a logic circuit. In digital circuits, normally there are TWO possible states of the input. i,e., ON and OFF. A logic HIGH state corresponding to binary 1 and a logic LOW state corresponding to binary O is called positive logic. If in a system high level is designated as O and LOW as 1, then such a logic is called as a negative logic. Basic Logic gates: The three basic logic gates are OR, AND and NOT gates. OR-gate: An OR gate is a logic circuit with two or more input points and a single output such that the output is HIGH when any or all the inputs are high. The output is LOW if all the inputs are LOW. If A and B are the inputs of a two input OR gate, the output Y is HIGH if either A or B or both are HIGH. Therefore, the gate is called as OR gate. OR gate realises the Boolean OR operator. The Boolean equation for an OR gate is given by Y = A+B (output Y is equal to input A OR input B). Truth table of two input OR gate A B Y=A + B 0 0 0 A 0 1 1 B 1 0 1 1 1 1 where A and B are the inputs and Y is the output Logic symbol of two input OR-gate:
Y=A+B

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Digital Electronics Schematic symbol and truth table of a three input OR-gate: Inputs Output A B C Y=A+B+C A Y = A + B+C 0 0 0 0 B 0 0 1 1 C 0 1 0 1 0 1 1 1 1 0 0 1 [Note: Y = A + B + C should be read as Y equals A or B or C] 1 0 1 1 1 1 0 1 1 1 1 1 NOT gate or INVERTER gate: Not gate or an inverter has one input and one output terminals, the output is HIGH for LOW input and the output is LOW for HIGH input. Truth table of NOT gate and Logic symbol of NOT gate are shown in the figure. NOT gate using Transistor: Fig. shows the circuit of a NOT gate using transistor. When the input is 0V, the E/B junction of the transistor is not forward biased and hence the transistor will be in CutOFF condition. The output is equal to 5V. If the input is 5V, the transistor is driven into saturation and the output is
+ 5V RC A Y= A

Input A 0 1

Output

Y=A
1 0

Y =

RB A

Y=A

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Digital Electronics nearly equal to 0V. The symbol of NOT gate is shown in fig. The bubble at the output indicates the inversion.
Operating conditions:

A 0V 5V

Condition of transistor OFF ON

Output Y 5V 0V

AND gate: AND gate performs the Boolean AND operation. The Boolean equation for a two input AND gate is given by Y = AB (output Y is equal to A AND B). AND gate is a logic circuit with two or more inputs and a single output such that the output is HIGH only when all the inputs are held HIGH, otherwise the output is LOW. If A and B are the inputs of a two input AND gate, the output Y is HIGH if both A and B are HIGH. Therefore, the gate is called as AND gate. Truth table
A 0 0 1 1 B 0 1 0 1 Y=A B 0 0 0 1
Logic symbol of a two input AND-gate

A B

Y=AB

Truth Table Inputs Output A B C Y=A.B.C 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 0 1 0 0 0 1 0 1 0 1 1 0 0 1 1 1 1

A B C

Y=A. B.C

[Note: Y = A .B . C should be read as Y equals A AND B AND C]

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Digital Electronics NAND gate: NAND gate is an equivalent logic gate of AND gate followed by a NOT gate. In this gate, the output is low when all the inputs are high. The Boolean equation for the output of NAND gate is Y= A B . NAND gate is an AND gate followed by a NOT gate as shown below.
A B

A Y= A B B

AB

Logic symbol of NAND gate Truth table and symbol of 2 and 3 input NAND gates
Tr uth table

A 0 0 1 1

B 0 1 0 1

Y= A B 1 1 1 0

A B

AB

Inputs A B 0 0 0 0 0 1 0 1 1 0 1 0 1 1 1 1 NAND gate

Output C Y= A B C A 0 1 B 1 1 C 0 1 1 1 0 1 1 1 0 1 1 0 using diodes and transistor

+ 5V

Y= A B C

D1
A

RC

RC
X T

Y = A.B

D2

Fig. shows a two input NAND gate using diodes and transistor. Page 4 of 42

Digital Electronics Working: Case1: When both the inputs A and B are 0V, the diodes D1 and D2 are forward biased due to 5V VCC. Potential at Node X becomes zero resulting in the cutoff of transistor T and hence the output will be nearly 5V. Case2: When A = 0V and B = 5V, diode D2 turns OFF and diode D1 is ON. The voltage at node X is nearly zero and the transistor T reaches cut OFF state. Therefore output voltage is nearly 5V. Case3: When A=5V and B=0V, diode D1 turns OFF and diode D2 is ON. The voltage at node X is nearly zero and the transistor T remains in cut OFF state. Therefore output voltage is nearly 5V. Case4: When both A and B are given 5V, both the diodes D1 and D2 turn OFF making node X voltage nearly 5V. Therefore, the transistor T is driven into saturation resulting in nearly 0V output. Operating conditions indicated in the table summarises the Boolean NAND operation of the above circuit Operating conditions of diode transistor NAND gate Condition of B Voltage at Condition of Output Y diodes node X Transistor D2 D1 0V ON ON 0V OFF 5V 5V ON OFF 0V OFF 5V 0V OFF ON 0V OFF 5V 5V OFF OFF 5V ON 0V

A 0V 0V 5V 5V

NOR gate: NOR Gate has one output and 2 or more inputs. The Gate can be considered as an OR Gate followed by an inverter. The output of NOR Gate is LOW if any one or all the inputs are HIGH. The Boolean equation for the output of 2 input NOR gate is. Y = A + B NOR gate is an OR gate followed by NOT gate as shown below.
A B

Y=A+B

A B

Y=A+B

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Digital Electronics Logic symbol and truth table of 2 and 3 input NOR gates
Tr uth table
A

Y=A+B
B

A 0 0 1 1

B 0 1 0 1

Y= A + B 1 0 0 0

A B C

Y = A+ B+C

Inputs A B 0 0 0 0 0 1 0 1 1 0 1 0 1 1 1 1
+ 5V

C 0 1 0 1 0 1 0 1

Output Y= A + B + C 1 0 0 0 0 0 0 0

NOR gate using diodes and transistor:

D1 RC
A T

Y=A+B
X

D2

Fig. shows a two input NOR gate using diodes and transistor. Case1: When both the inputs A and B are 0V, the diodes D1 and D2 are not biased and therefore both the diodes turn OFF. Potential at Node X becomes zero resulting in the cutoff of transistor T and hence the output will be nearly 5V. Page 6 of 42

Digital Electronics Case2: When A = 0V and B = 5V, diode D1 is OFF and diode D2 turns ON. The voltage at node X is nearly 5V and the transistor T reaches saturation state. Therefore output voltage Y 0V. Case3: When A=5V and B=0V, diode D1 is ON and diode D2 turns OFF. The voltage at node X is nearly 5V and the transistor T reaches saturation state. Therefore, the output voltage Y 0V. Case4: When both A and B are given 5V, both the diodes D1 and D2 turn ON making node X voltage nearly 0V. Therefore, the transistor T is driven into saturation resulting in nearly 0V output. Operating conditions indicated in the table show that the circuit realises Boolean NOR operation. Operating conditions of diode transistor NOR gate: Condition of A B Voltage at Condition of Output Y diodes node X Transistor D2 D1 0V 0V OFF OFF 0V OFF 5V 0V 5V OFF ON 5V ON 0V 5V 0V ON OFF 5V ON 0V 5V 5V ON ON 5V ON 0V Exclusive-OR gate: This gate realises the Boolean Exclusive-OR operation. The X-OR operator is represented by sign. It is a combinational logic gate with two or more inputs and one output. The output of X-OR gate is HIGH when odd number of inputs are in HIGH state. For a two input X-OR gate, the output is HIGH when the inputs are different. The Boolean equation for a two input X-OR gate is Y=A B. i.e., Y = A B+ B A. When there are more than two inputs, the Boolean equation can be written as Y= ABC. Truth table Inputs Output Y = AB + BA A B 0 0 0 0 1 1 1 0 1 1 1 0
Logic symbol of 2 input X-OR gate.

A B

Y= A B + B A

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Digital Electronics Inputs A B 0 0 0 0 0 1 0 1 1 0 1 0 1 1 1 1 Output Y= A B C 0 1 1 0 1 0 0 1

Logic symbol of 3 input X-OR gate.

A B C

Y=A B C

X-OR gate using basic gates:

A
A

C 0 1 0 1 0 1 0 1

AB

Y= A B+ B A

B
B

BA

XNOR gate: It is an X-OR gate followed by a NOT gate. It gives logic HIGH output whenever the even number of inputs are held HIGH. i.e., X-NOR gate produces LOW output when odd number of inputs are in HIGH state. The Boolean expression for a two input X-NOR gate is given by Y = AB + BA = A B Logic symbol of X-NOR gate:
A B

Truth table

Inputs A 0 0 1 1 B 0 1 0 1

Output Y 1 0 0 1

Y = AB

Two input X-NOR gate is useful for bit comparison and it recognises when the two inputs are identical. Hence this gate is also called as the comparator or coincidence circuit. It is also used as an even parity generator. Universal logic gates: By using different combinations of NAND gates or NOR gate, all other logic gates can be realised. Therefore, NAND gate and NOR gates are called as universal logic gates. Page 8 of 42

Digital Electronics Universal property of NAND gate: 1. NAND gate as NOT gate:
A Y= A

2. AND gate using NAND gates:

A B
AB

Y=

A B

3. OR gate using NAND gates:

A

Y = A B= A + B
B
B

4. NOR gate using NAND gates:

A A Y= A+B B
A+B

5. XOR gate using NAND gates:

A
A AB

AB

B AB

Y = A AB B AB Y = A B + A B = A AB + B AB = A AB + B AB = AB(A + B)
= (A + B)(A + B) = A B + AB

6. XNOR gate using NAND gates:

A

Y = A AB B AB
= A B + AB

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Digital Electronics Universal property of NOR gates: 1. NOR gate as NOT gate:
A Y= A

2. OR gate using NOR gates:

A A+B Y=A+B=A+B

3. AND gate using NOR gates:

A
A

Y = A + B = A B = AB

B
B

4. NAND gate using NOR gates: A

A
A.B

Y=AB

B
A

5. X-OR gate using NOR gates:

A
A+B

A+A+B

(A + A + B) + (B + A + B)
Y

B+A+B

Y= ( A + A + B) + (B + A + B)

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Digital Electronics The Boolean equation of the output of the above circuit can be simplified as follows. Y = ( A + A + B) + ( B + A + B) = A (A + B) + B(A + B) = A B + A B = A B 6.
A
AB
A+B

X-NOR gate using NOR gates:

A+A+B

Y= (A + A + B) + (B + A + B) B
B+A+B

Output Equation can be simplified as follows: Y = (A + A + B) + (B + A + B) = A B + AB = A B Half adder: = A (A + B) + B(A + B)

Half adder is a basic building block of arithmetic circuits. It adds two binary digits without taking carry in to account. It has two inputs and two outputs. If A and B are the inputs, the outputs SUM and CARRY are given by the Boolean equations A B + A B and A.B respectively. Half adder is generally used in the LSB column of binary adder circuits. Half Adder cannot accept a carry from other column and hence the terminology Half Adder is in practice. Half adder can be constructed by using an Exclusive OR-gate and an AND gate as shown the figure.
A Carry=AB A
B

Carry = AB

Half Adder
B

Sum = AB + A B

Sum= A B + A B

Working: A) When A = 0 ,B = 0: CARRY = 0 and SUM = 0

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Digital Electronics B) When A = 0, B = 1 :the output of AND gates will be zero but XOR gate gives the HIGH output. This confirms the addition 0 + 1 as SUM=1 &CARRY = 0 C) When A = 1, B = 0: XOR gate gives HIGH output and AND gate gives 0 output. This confirms the binary addition 1 + 0 as SUM=1 &CARRY = 0 D) When both inputs A and B are HIGH the output of XOR gate is zero and that of AND gate is HIGH which confirms the binary addition 1 + 1 as SUM =0 CARRY=1 i.e.,1+1= 10. Thus a Half adder performs two bit binary addition. The truth table of the Half adder is given in the following table. Truth table of half adder A 0 0 1 1 Full Adder : A full adder is a binary adder capable of adding two bits of the binary along with the carry generated because of previous addition at a time resulting in two outputs SUM and a CARRYOUT. Full adder hence has 3inputs and 2 outputs.
A B C

B 0 1 0 1

Carry AB 0 0 0 1

Sum
A B + AB

0 1 1 0

C 1 = A .B
Half adder 1 S1 = A B + A B

C O =(A B) +A B C

C 2 =(A B) C Half adder 2

CARRY

SUM = A B C

A Full adder can be constructed using two half adders as shown in the fig . A and B are the bits corresponding to a column in binary addition whereas the input C is generally the CARRY from other column. The following truth table explains its action. Page 12 of 42

Digital Electronics
Truth Table of full adder

A 0 0 0 0 1 1 1 1

B 0 0 1 1 0 0 1 1

Cin 0 1 0 1 0 1 0 1

COUT 0 0 0 1 0 1 1 1

SUM 0 1 1 0 1 0 0 1

From the truth table it is clear that when any two bits are high we get CARRY as logic HIGH. The SUM 1 gives the binary addition for the inputs A and B which in turn gets added on to the input C which is generally the CARRY obtained from other columns during the binary addition. The final CARRY Co is given by CO=(AB) +ABC and the final SUM is given by So = ABC. Simplifying the final CARRY equation, we get, CO=AB+BC +CA. A full adder can be realised in the following way also.
A B C AB

BC

CARRY =AB+BC+CA

AC

SUM = A B C

Timing Diagrams : Timing diagrams are the representations of input and output conditions of a digital circuit with reference to time. Normally these are voltage time representations.
A Y B

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Digital Electronics Consider the following input and output waveforms for the above gate.
Input A

o
Input B

o
Output

Fundamental Products: In digital systems, signals are available in either complimented form or uncomplemented form. Consider a two input AND gate as in figure. To obtain a high output for the first entry of the truth table (TT). The A & B must be inputs.
Truth Table A 0 0 1 B 0 1 0 Y 0 0 0

From the timing diagrams it is clear that the output of AND gate exists only when both the inputs are high (AND gate function). Therefore, the output waveform contains only two pulses for the given input pulse according to the fig. In digital circuits timing diagrams play an important role in representing the response of a circuit. ( Karnaugh Map ) K-Map

Similarly to obtain high output for 2nd entry A B are the inputs and for the third AB are the inputs. The four logic products i.e., Page 14 of 42

Digital Electronics
A B , A B, AB, AB

are called fundamental products, because they

represent the basic ways to combine the signals with an AND gate for high output. Similarly for a three the input signal

A B C , A B C , A B C , A B C , A B C , A B C , A B C , A B C are

fundamental

products. Sum of Products (SOP) Truth Table B A 0 0 1 1 0 1 0 1 Y 0 0 1 1

Suppose the truth table is given as this, the Boolean expression for the output can be written with the help of AND-OR gates as follows. The fundamental products for the truth table are A B and A B . The Boolean expression is the OR of the fundamental products i.e.,
Y = AB + AB (logic sum of the fundamental products). This is the sum-

of-product expression for the given Truth Table. Plotting of K-Map (2-variable) Truth Table A B Y 0 0 1 1 0 1 0 1 0 0 1 1

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Digital Electronics
B A
A B

Suppose this is the given truth table, the K-map for this table is drawn as follows. The vertical

column has A followed by A and the horizontal row has B followed by B as shown in Figure (1).
B A
A B

From the truth table, first high output is

1 (2) (3)
B
B

obtained for an input AB = 10. The fundamental product for this is AB . Enter 1 on the K-Map as shown in (2). This 1 represents the fundamental product
AB .

Similarly

enter

for

the

fundamental product AB as in (3). Final step in the construction of K-map is to enter 0s in the remaining spaces. (4) shows the complete K-map for the given truth table.

B
A
A

0 1
(4)

0 1

Three Variable K-Map For a 3 variable K-Map the vertical column is labeled as
A B , A B, AB, AB .

This order is not a binary progression, rather it

follows the gray code process or progression of 00, 01, 11, 10. The reason for this is only one variable will change from complemented to uncomplemented form (or vice versa). The fundamental products for the truth table are A BC , ABC and
ABC . Draw the empty K-map and then enter 1 for the fundamental

Page 16 of 42

Digital Electronics products. Finally enter 0s in

CD AB CD CD CD

AB AB
AB

0 0 0 0
C

1 0 0 0 C

0 1 0 0

0 1 1 0

the remaining spaces.

The

final K-map looks as shown in (2)

C
AB

C 0 0 1 0

AB

0 1 1 0

AB
AB
AB

1 1 1

AB

AB
AB

Table (1) Table (2) Four Variable K-Map: The vertical column is labeled A B , A B, AB, AB and horizontal column is labeled as C D , C D, CD & CD which is also a gray code progression. Final products are A B C D, A BCD , A BCD & ABCD Pairs, Quads and Octates Map shown in (1) contains a pair of 1s that are horizontally adjacent. The first represent the products AB and the second AB. Only one variable changes from complemented to uncomplemented form ( B to B). Whenever this happens we can eliminate the variable that changes.
B

B
0 1

(1) Algebraic Proof Sum of product equation corresponding is = A ( B + B) Y = AB + AB (Q B + B = 1) Y=A Pair means two 1s that are horizontally or vertically adjacent. Pair eliminates one variable in the equation. Page 17 of 42

0 1

Digital Electronics Quad A quad is a group of four 1s that are horizontally or vertically adjacent. The 1s may be end to end as shown in (1) or in the form of a square as in (2). Quad mean two variables and their complements drop out of the equation.
CD
AB

CD

CD

CD

CD
AB

CD

CD

CD

0 0 1 0

0 0 1 0

0 0 1 0

0 0 1 0

0 0 0 0

0 0 0 0

0 0 1 1

0 0 1 1

AB
AB AB

AB
AB AB

(1)
= AB (C + C ) = AB

(2)

The quad shown in (1) can be written as a group of 2 pairs.

Y = ABC + ABC

Quad shown in (2) can be written as a group of 2 pairs as

Y = ABC + AB C = AC (B + B ) = AC

Octet is a group of eight 1s which are adjacent. It eliminates three variables and their complements. (1) shows the octet. This octet can be written as a group of two quads.

CD AB

CD

CD

CD

AB
AB AB

0 1 1 0

0 1 1 0
Y = BC + BC

0 1 1 0 (1)

0 1 1 0

= B( C + C ) = B

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Digital Electronics Karnaugh Simplifications: Encircle the octates first, quads second, pairs next and the isolated ones last. Overlapping Groups It is allowed to use the same 1 more than once in the map for simplifications (1) shows this. The 1 representing the final product
A BC is a part of the pair and a part of the quad.

The simplified

equation for the overlapping groups is

C 1
1 1 Fig 1 C 1 1
Y = A + BC

AB AB AB

---

(1)

It is also valid to encircle the 1s as shown in (2), the isolated 1 results in the more complicated equation.

AB

C
AB AB

C 1 1
Y = A + ABC

1 1 1

---

(2)

AB AB

This will require a more complicated logic circuit for equation (2). So always overlapping of groups results in more simplified equations.

Rolling the Map From (1) the pairs resulting in the equation Y = BC D + BCD . Assume that the map is rolled such that left side touches the eight side then the two pairs actually looks like a quad. To indicate this draw half circles around each pair as shown in figure 2. From this the quad equation is Y = BD . The explanation for this is as follows. Page 19 of 42

Digital Electronics
CD AB AB CD CD CD CD AB AB CD CD CD

0 1 1 0

0 0 0 0 Figure 1

0 0 0 0

0 1 1 0

0 1 1 0

0 0 0 0 Figure 2

0 0 0 0

0 1 1 0

Deleted: <sp>

AB
AB

AB
AB

Y = BC D + BCD = BD (C + C )

Y = BD

This is nothing but a rolled map equation.

Therefore, 1s on the

edges of a Map can be grouped to get simplified equations. Elimination of Redundant groups If in a group all 1s are completely overlapped by other groups, then that group is to be eliminated in order to obtain simplified equation. For equation the map shown in (1) results in the equation
Y = BD + A BC + A CD + ABC + AC D

CD
AB

CD

CD

CD

0 1 0 0

0 1 1 1 Fig (1)

1 1 1 0

0 0 1 0

CD
AB

CD

CD

CD

0 1 0 0

0 1 1 1 Fig (2)

1 1 1 0

0 0 1 0

AB AB
AB

AB AB AB

Eliminating the quad in (2), the equation is --- (2) Y = A BC + A CD + ABC + AC D Equation (2) will contain one less product than equation (1). Therefore, (2) will be the correct way to group 1s.

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Digital Electronics The summary of the K-map method for simplifying Boolean equation. 1. Enter a 1 on the map for each fundamental product that produces a 1 output in the truth table. other. 2. Encircle the octates, quads and pairs. Roll and overlap the largest groups possible. 3. 4. 5. If any isolated 1s remain, encircle each. Eliminate the redundant groups. Write the Boolean equation by OR-ing the products corresponding to the encircled groups. Dont care condition In figure (1) a BCD input drives the decoder circuit. The decoder produces a 1 output only for a BCD input of 1001. BCD digits are restricted to the 4 bit number from 0000 to 1001. 1001 to 1111 cannot occur for normal operation. This is why the truth table for the decoder of (1) lists only the inputs from 0000 through 1001 as in table (1) Table (1)
A 0 0 0 0 0 0 0 0 1 1
B 0 0 0 0 1 1 1 1 0 0 C 0 0 1 1 0 0 1 1 0 0 D 0 1 0 1 0 1 0 1 0 1 Y 0 0 0 0 0 0 0 0 0 1

Enter 0s in the

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Digital Electronics Table (1) has 1 output only for one input ABCD = 1001 The fundamental product is AB C D. The map for this table is shown in figure (2) The empty spaces on the map are forbidden BCD inputs that are not
CD AB CD
CD

CD

listed in table (1). Since forbidden BCD inputs dont occur under

0 0

0 0

0 0

0 0

AB AB
AB

normal operating conditions, the empty spaces in figure(2) can be treated as 0s or 1s whichever is more convenient. To

1 Figure (2)

indicate this, mark X as in figure (3). These X are called dont cares because they can be treated either as 0s or 1s. (4) shows the most efficient way to encircle the 1. The 1s is included in a quad, the highest group that is possible using X as 1s.

After grouping 1 in the quad, the remaining X are to be treated as 0s. In this way the Xs are used to be best advantage.
CD AB AB AB
AB

CD

CD

CD

CD AB AB AB
AB

CD

CD

CD

0 0 x 0

0 0 x 1 Figure 3

0 0 X X

0 0 X x

0 0 x 0

0 0 x 1 Figure 4

0 0 x 1

0 0 X X

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Digital Electronics The quad of (4) results in the equation Y=AD. The logic circuit

inside the decoder is nothing more than an AND gate. When A & D are both 1s the output Y = quad (1001). To simplify dont cares 1. Enter 1s on the map for the fundamental products. Enter 0s for the other inputs listed in the truth table. Enter xs for the forbidden inputs. 2. Encircle the actual 1s on the map in the largest groups treating xs as 1s. 3. After the actual 1s have been included in groups

disregarded the remaining dont cares by treating them as zeros. Product of Sum Form (POS) Suppose the truth table given is shown in (1). The Boolean

expression for the output can be written with the help of OR-AND gates as follows. The fundamental sum for the truth
A 0 0 1 1 B 0 1 0 1 Y 0 0 1 1

table

is

(A+B)

&

( A + B ).

(Fundamental sums are the basic ways to represent two signals by an OR gate for a low output). output function expression of is the The AND sums

fundamental

Y = ( A + B )( A + B ) .

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Digital Electronics This is the product of sum (POS) expression for the given truth table. Plotting K-map for POS expression 1. Plot the empty K-map. 2. 3. 4. 5. Enter 0s corresponding to fundamental sums. Enter 1s in the remaining places to complete the K-map. Group octet, quad & pairs for simplification using 0s. If possible roll & overlap the maps for further

simplification. 6. 7. Eliminate the redundant groups. Write the final expressions by ANDing all the sums.

POS equation are called max terms, equation is given by Y=M (0, 1, 2, . . . ) Number Systems Gray Code The Gray code belongs to a class of codes called minimum change codes, in which only one bit in the code group changes when going from one step to the next. The gray code is an unweighted code, meaning that the bit positions in the code groups do not have any specific weight assigned to them. Because of this, the gray code is not suited for arithmetic operations but finds applications in input or output devices and some types of analog to digital converters. Binary to gray conversion: 1. 2. Record the most significant bit. Add this bit to the next position, recording the sum and neglecting any carry. 3. Record successive sums until completed. Page 24 of 42

Digital Electronics

Binary

Gray

If we examine the gray code groups for each decimal no., it can be seen that in going from any one decimal no to next, only one bit of the gray code changes. Equation from 3 to 4, it is 0010 to 0110 with only second bit from left changing. But in binary it is 0011 to 0100,

i.e., three of the bits are changing. The gray code is often used in situations where other codes, such as binary, might produce erroneous or ambiguous results during those transitions in which more than one bit of the code is changing. The principle advantage of the Gray code over straight binary is that no intermediate states occur during transitions. Fig. shows
Binary to gray conversion using XOR gates

Binary input

B3

B2

B1

B0

Gray output

G3

G2

G1

G0

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Digital Electronics

Gray to binary conversion: 1) Recording the MSB. 2) Add the binary MSB to next bit of Gray code. 3) Recording the result, ignoring carries and continues until process is completed. Eg : Gray Code 1 0 1 1

Binary Cod e

Gray to Binary conversion using XOR gates

Gray input

G3

G2

G1

G0

Binary output

B3

B2

B1

B0

Page 26 of 42

Digital Electronics

Flip-Flops A Flip-Flop is a device with two stable states. It remains in one of the states until triggered into other. Flip-Flops are most important memory elements which are made up of logic gates. Even though a logic gate has no storage capability, several logic gates can be connected together so as to form flip-flops which can act as memory storing cells.
FLIP FLOP

Inputs

Outputs

Figure shows the general diagram of flip flop. It generally has two outputs, expressed as Q & Q which are complement to each other. If the output Q is High (or 1), then the output Q will be in the low state (or 0). If Q=1, Q =0, then the Flip-Flop is is said to be SET. If Q = 0, Q = 1 then the Flip-Flop is said to be RESET. Any flip flop can have one or more inputs. These inputs are used to cause the flip flop to switch back and forth [flip and flop] between its possible output states. A flip flop input has to be pulsed momentarily to cause a change in the flip flop output state and the output will remain in that new state after the input pulse is over. This is flip flops memory characteristic. Flip-flop is also called as Latch. Basic Flip-Flop (R-S Flip-Flop) is also called as Bistable Multivibrator. One of the simplest storage device is the Reset Set Flip Flop (R-S Flip-Flop) and can be formed by using NAND gates or NOR gates. R S Flip Flop: Logic Symbol of R S Flip Flop The output of the circuit (0 or 1) remains at the same level until an external trigger pulse causes the output to change the state. When logic high voltage (i.e., 1) is applied to the S input, output of the Flip Flop becomes HIGH. This is called SETTING the flip flop. When Page 27 of 42

Digital Electronics logic LOW voltage (i.e., O) is applied to the S input, the output of the Flip Flop becomes ZERO. This is called RESETTING the flip flop. R S Flip Flop (Latch) using NAND Gates ( R S Flip Flop): In R S Flip Flop, the output of each NAND gates is fed back to one of the inputs of the other NAND gate. The R & S inputs allow the Flip-Flop to RESET or SET the output respectively. Condition 1: When R = S = 0 When no trigger is applied to both the inputs, both the outputs Q and Q will try to become 1 which is not allowed. Hence this condition is prohibited. This state is known as Forbidden state. Condition 2: When R = 0 and S = 1, Trigger pulse applied to S input will SET the Flip-Flop i.e., Q=1 & Q =0. Condition 3: When R = 1, S = 0 Trigger pulse applied to R input will RESET the Flip-Flop i.e., Q=0 & Q =1. Condition 4: When R = 1 and S = 1. In this case, the output remains fixed at the state they were i.e., Q & Q will have their previous logic levels (last state). It is called as latched or stick to its last state.
R
Q
R
FLIP FLOP

Truth Table of basic ( R S Flip Flop) Input 0 0 1 1

R S

Output Q 1 1 0 0 1
Q

Condition / Action Forbidden SET RESET NO Change

0 1 0 1

1 0 1 1 0

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Digital Electronics Clocked R S Flip Flop The basic R S Flip Flop changes the state as soon as a triggering pulse to either R input or S input is applied. But sometimes it is desired to have a Flip Flop that can change their states at only certain requirements and in many cases synchronously with respect to other circuit elements which may be responding with either trailing edge or leading edge of the clock signal. This requirement is achieved with Clocked Flip Flop. The symbol Clk is used for the clock inputs. Clocked R S Flip Flop:
R CLK S 2 4 1 Logic symbol 3
Q

R CLK
FLIP FLOP

Q
Q

Figure shows the diagram of a clocked R S Flip Flop. It consists of four NAND gates with 3 inputs getting only 2 outputs, which are complement to each other. The Clk input is given to one of the inputs of NAND gates 1 & 2 in order to change their state under certain requirements. Clocked Flip-Flops have a clock input that is typically labeled as Clk, Ck or Cp. In most clocked Flip Flops the clk input is edge-triggered, which means that it is activated by a transition. This is indicated by the presence of a small triangle on the Clk input. Clocked Flip Flops also have one or more control inputs that can have various names depending on their operations. The control inputs will have no effect on Q until the active clock transition occurs. This effect is synchronous with the signal applied to Clk. So they are called as synchronous control inputs.
Truth Table of Clocked R S Flip Flop Clk 0 0 0 0 1 1 1 1 R 0 0 1 1 0 0 1 1 S 0 1 0 1 0 1 0 1 Q Q Q Q Q Q 1 0 * Condition

Q Q
Q

Q
Q

LATCH

Q
0 1 * SET RESET ILLEGAL

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Digital Electronics

Logic symbols of Level triggered, Positive edge and Negative edge Triggered RS flip-flop R CLK
S FLIP FLOP

Q
Q

R CLK
S FLIP FLOP

Q
Q

R
FLIP

Q
Q

CLK FLOP
S

Timing diagram of RS Flip-flop

CLK

S F Output Q Output Q L S L R L L F L R L S L L S L R L

D - Flip Flop A D-Flip Flop is also a latched flip flop which can be fed with a clock input. A variation of the clocked R-S latch is the clocked D-Latch. Figure shows the clocked D latch circuit which represents some data. It replaces the R & S input of the R S Latch. Thus for Clk = 1, the logic value of Q exactly equals that of D and will flow changes in D. For Clk = 0, the value of Q will maintain the last value. Prior to Clk becoming 0, with a D input instead of R & S inputs it is not Q = Q = 1 which would possible to obtain the undesirable output of result in the clocked R S latch if R = S = 1, while the clock input is asserted.

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Digital Electronics
D 1 3

CLK 2 4
Q

Figure shows that circuit diagram of D-Latch Flip Flop which is constructed using 4 NAND gates. The Clk input is applied to one of the two inputs of two NAND gates 1 & 2. The D input is applied directly to the NAND gate 1 and the same input is complemented and applied to the other input of NAND gate 2. The gates 3 & 4 are the latch part of the circuit. The truth table below shows the flip flop operations & their conditions. Truth table and Symbolic Representation of Negative edge triggered D Flip Flop Clk 0 0 1 1 D 0 1 0 1

Q
Q Q 0 1

Condition
No Change No Change Reset Set
D
FLIP

Q
Q

Q
Q

1 0

CLK

FLOP

The edge triggered D Flip Flop uses an edge detector circuit to ensure that the output will respond to the D input only when the active transition of the clock occurs. If this edge detector is not used, the resulted circuit operates some what differently. Operation: When a Clk input is HIGH, the D input will produce a LOW at the SET input of the NAND latch to cause Q to become the same level as D. If D changes while Clk is HIGH, Q will follow the changes exactly. That is, while Clk = 1, the Q output will look exactly like D. In this mode, the D-Latch is said to be TRANSPARENT. When Clk is LOW, D input is inhibited from affecting the NAND latch, Since the outputs of both steering gates will be held HIGH. Thus Q & Q outputs will stay at whatever level they had, just

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Digital Electronics before Clk went LOW. That is the outputs are latched to their current value and cannot change while Clk is Low even if D changes. Fig shows the realisation of D flip-flop using RS flip-flop and NOT gate. NOT gate prevents both the inputs R and S simultaneously to be in the same state.
D S
FLIP FLOP

R CLK

Timing diagram of D Flip-flop

CLK

R S

J K Flip Flop In Clk R S Flip Flop when both the inputs are 1 (R = S = 1) we could not get the proper output as it was indeterminate and was not allowed or forbidden. J K flip flop is the improved version of R S flip flop so that when both inputs are 1 then also the outputs Q and Q are complement of each other. The J K flip flop has two inputs J & K. The J input of this flip flop corresponds to S input & K input corresponds to R input of R S flip flop. The circuit for a clocked J K flip flop is as shown.

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Digital Electronics

J CLK K

Q
J

Logic symbol CLK

FLIP FLOP

Q
Q

From the figure & symbolic representation we find that it has 2 input signal J & K and the function of flip flop is determined by these signals when a clock pulse arrives. The J & K input controls the state of the flip flop in same way as the R & S inputs do for the clocked R S flip flop except that, the J = K = 1 condition does not result in an ambiguous result. For this, the flip flop will always go to its opposite state upon the +ve transition of the clock signal. This is called the toggle mode of operation. In this mode if both J & K are left HIGH, the flip flop will change states (Toggle) for each clock pulse. Truth Table CLK 0 0 0 0 1 1 1 1 J 0 0 1 1 0 0 1 1 K 0 1

Condition

0 1 0 1 0 1

}
Q
0 1
Q

LATCH

1 0

RESET SET Toggle

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Digital Electronics

Timing diagram of JK Flip-flop

CLK

Output Q Output Q

L S

R L

L T

L R

L T

The Race Around Condition If the flip flops outputs changes too fast or if latches were used a state could ripple (or) race down the chain. This is called the race problem. The difficulty with the use of a latch in a synchronous system is often called the Race Problem. We know that the conditions R = 1 & S =1 is not allowed in an R-S flip flop. This is eliminated in a J-K flip flop by using the feedback connection from outputs to the inputs of the gates 1 & 2. Because of the feedback connection Q ( Q ) at the input to K ( J ), the input will change during the clock pulse (Clk = 1) if the output changes state. eg. Let the inputs J = K = 1 & Q = 0, when the pulse width tp is applied, the output will change from 0 to 1 after a time interval t. t is the propagation delay through two NAND gates in series. Now after time t we have J=K=1 & Q = 1 after another interval of t the output Q will change back from 1 = 0.

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Digital Electronics Hence the output will oscillate back and forth between 0 & 1 in the duration tp of the pulse width. But at the end of clock pulse the value of Q is ambiguous. This situation is known as a Race-Around-Condition. The race-around condition can be avoided if tp < t < T. Lumped delay lines can be used in series with the feedback beyond tp and hence to prevent the race-around difficulty. Master Slave Flip Flop One method to avoid race around condition in JK flip-flop is by using Master slave flip-flop. Master slave flip flop uses 2 JK flip flops. One is called Master (Positive edge triggered) and the other is called Slave (Negative edge triggered). The master flip flop responds during the positive edge of each cycle and the slave responds for the corresponding negative edges. Fig. shows the realisation of M/S flip-flop.
QM
Master Flip-

JM CLK

JS CLK
Slave FlipK S Flop

QS

JM CLK

M/S FLIP FLOP

QS
QS

QM

QS
KM

KM

Flop

If JM = 1 & KM = 0 the master sets as soon as +ve edge of clock signal occurs forcing the output QM to be HIGH. The high output (QM=1) of the master drives the JS input of the slave and Q M =0 resets the KS input. Hence, when a ve edge of clock signal occurs, the slave sets repeating the same operation as master did during the positive edge of the clock. That is it copies the action of the master. If JM = 0 and KM = 1 the master resets on the occurance of the +ve edge of the clock signal which forces Q M to be at 1 or QM = 0. The high Q M output of the master drives the KS input of the slave. Hence when a ve edge of the clock signal occurs it forces the slave to reset. Again slave copies the master. Page 35 of 42

Digital Electronics If JM = KM = 1, i.e., both the inputs are high for the master, it toggles on arrival of +ve clock edge and the slave toggles on the occurrence of ve clock edge. From above we observe irrespective of the values of JM & KM the slave copies the master i.e., if master sets, slave also sets and if master resets slave also resets.
Timing diagram of M/S JK Flip-flop

CLK

K Output QM Output QS

T- Flip Flop Another basic flip flop called T or Toggle flip flop has only a single data (T) input and a clock input. It is obtained from a JK type. The designation T comes from the ability of the flip flop to toggle or complement its state on the application of each clock pulse. It is realised using M/S JK flip-flop as shown in the fig. Block Diagram & Operation
T J
FLIP

Q T
Q
FLIP

Q
Q

CLK

FLOP

CLK

FLOP

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Digital Electronics When the T input is LOW ( J = K = 0 ) state prior to the application of clock pulse, the Q output will not change its state on applying the clock pulse. When the T input is HIGH ( J = K = 1 ) state prior to the application of clock pulse, the Q output will change its state regardless of what output was present earlier. This is called Toggling, hence the name T-flip flop. The characteristic table & Equation shows that when T = 0, Q ( t + 1 ) = Q that is, the next state is the same as the present state and no change occurs. When T = 1, Q ( t + 1 ) = Q i.e., the state of the flip flop is complemented . Truth Table T Q (t) 0 0 0 1 1 0 1 1

Q 0 1 1 0

( t + 1 )

T 0 1

Qn+1 Qn
Qn

The wave forms of Q & Q are shown below.

Timing diagram of T Flip-flop

CLK

T type flip flop is most often seen in counters & sequential counting networks because of its inherent divide-by-2 capability. When a clock pulse is applied the output changes once every input cycle thus Page 37 of 42

Digital Electronics complementing one cycle for every input cycles. This is the action required in many cases for binary coded counters. Basic Flip Flip Applications Flip flops are used in counter ckts. Flip flops are also used in shift and storage registers. A wide variety of serial decode, comparision and timing functions can be accompanied by using flip flops. A variety of one-shots can be generated by using flip flops.

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Digital Electronics ONE mark questions: 1. Give the Boolean expression for an XOR gate output. 2. Give the output of a 2 input XNOR gate when the inputs are A = 1, B = 0. 3. What is meant by Bubble? What it denotes? 4. What is involution law? 5. What is complementation? 6. Draw the timing diagram for Inverter gate. 7. Write the truth table for two input XOR gate. 8. Write the Schematic symbol of X-OR gate. 9. Write the truth table for two input X-NOR gate. 10. What is meant by universal Logic gate? 11. Name the logic gates which can be used as universal logic gates. 12. 13. 14. 15. What is a Half Adder? Write the truth table of Half Adder. What is a Full Adder ? Write the truth table of full Adder. Full-

16. Write the Boolean expression for the SUM output of a Adder. 17. 18. 19. 20. 21. 22.

Write the Boolean expression for the CARRY output of a Full-Adder. Write the Boolean expression for the SUM output of a Half-Adder. Write the Boolean expression for the CARRY output of a Half-Adder Draw the diagram realising the NOT operation using NOR gates. Write the De Morgans laws? Which type of addition is called Mod 2 addition?

TWO mark questions : 1. Give the truth table for Half Adder. 2. Realise AND gate from only NAND gates. Page 39 of 42

Digital Electronics 3. Realise OR gate from only NAND gates. 4. Realise AND gate from only NOR gates. 5. Realise OR gate from only NOR gates. 6. Realise X-OR gate from only NAND gates. 7. Realise X-OR gate from only NOR gates. 8. State De Morgans theorems. 9. Draw the logic diagram of Half Adder using only NAND gates. 10. 12. 13. 14. 15. 16. Prove that A+BC = (A+B) (A+C). What are timing diagrams? Why are they used? Write the timing diagram for a two input AND gate. Write the timing diagram for a two input OR gate. Write the timing diagram for a two input X-OR gate. Write the timing diagram for a two input NAND gate. 11. Prove that A + AB = A+B

FOUR mark questions: 1. State and explain De-Morgans theorems. 2. Simplify Y = (A + B) ( A + B) (A + 1) using Boolean laws and write the simplified circuit. 3. Realise OR, NAND, AND and NOT gates using NOR gate. 4. Prove the Universal property of three basic gates. NAND gate by constructing

5. Construct an XOR gate using NAND gates and prove that its output is Y = AB + BA. 6. Construct and explain a Full adder. 7. Construct and explain the Half adder. Numerical problems 1. Show that AC + ABC = AC. 2. Show that ( A + B) ( A + C) = AC + AB using truth table. 3. Prove that AB + AC + BC = AC + BC. 4. Draw the logic circuit for Y = (AB + AB) (B + 1) 5. Draw the logic circuit for y = ( A B + AB) ( B + 1) .Simplify the expression and draw the corresponding logic circuit (Ans. Simplified expression is Y = A ) Page 40 of 42

Digital Electronics 6. Write the Boolean expression for the following logic circuit.
A B
Y

Simplify the expression and write the corresponding logic circuit. 7. Identify the logic gate for which the input and the output waveforms are shown below.
1 A 0 0 1

0 B

1
Y

1 0

7. Write the truth table for the following Boolean equations: i) Y = ( A + B + C)AB ii) A+BC+ CB 8. Apply De Morgans theorems for the following Boolean equations and simplify to the possible extent 1. A + A + B 2. AB 3. A + B + C + D 4. AB + CD 9. Using Boolean algebra simplify the following expressions. Realise them using basic logic gates. 1. PQ+P(Q+R)+ Q (Q+R).

+ AB C) . 2. A(ABC

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Digital Electronics 10. Write the Boolean equation for the output of the following logic diagram and simplify it. Draw the logic circuit for the simplified circuit using only NAND gates
A B
Y

ONE mark questions 1. Give the symbol of a 3 input NOR gate. 2. Give the Boolean expression for AND gate output. 3. What is a NOT gate? 4. Write the truth table for three input AND gate. 5. Write the logic symbol for the three input AND gate TWO mark questions 1. Draw a circuit for two input diode AND gate. 2. Give the truth table for 3 input NOR gate. 3. Draw the pin diagram of IC 7400. 4. Draw the logic symbol of a two input AND gate and write its truth table. 5. Draw the logic symbol of a two input OR gate and write its truth table. 6. Draw the logic symbol of a NOT gate and write its truth table. FOUR mark questions 8. Explain the action of a 3 input diode AND gate. 9. Construct a NOR gate using diodes and transistor and explain its operation 10. Explain the working of a two input diode AND gate with circuit diagram. 11. Explain the working of a two input diode OR gate with circuit diagram. 12. Explain the working of two input OR gate using transistors 13. Explain the working of two input AND gate using transistors

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