INDIAN INSTITUTE OF TECHNOLOGY GUWAHATI

Department of Computer Science and Engineering

CS221 (Digital Design): Mid Semester Examination
Date: 20th Sept 2011 Q1 Time: 10.00AM-12.00Nn Full Marks: 50 Answer all 5 questions

[10 Marks] [Topic: Boolean Logic and KMAP]

A. [4] Derive the corresponding min term canonical formula in algebraic form, m-notation and M-notation of 4 variable given Boolean function F(w, x, y, z) = wx + yz + xyz + xyz B. [2+2+2] Using Karnaugh map optimize the 4 variable Boolean expressions (No need to draw logic diagram)

a. F1(w, x, y, z)= b. c.
Q2

m(3,4,5,6) + dc(10, 11, 12, 13, 14, 15) , F2(w, x, y, z)= m(1, 2, 5, 6) + dc(10, 11, 12, 13, 14, 15) F3(w, x, y, z)= m(7, 8) + dc(10, 11, 12, 13, 14, 15)

[6 Marks] [Logic Implementation using MUX and Decoder]

A. [3] Implement the given two Boolean functions F1 (x, y, z) =

M(0, 1, 3, 5) and F2 (x, y, z)=M(1, 3, 6, 7)

F= F1 x F2) using one 4x1

using a 3 to 8 line decoder and two 4 input OR gate. B. [3] Implement Product of the above two Boolean functions (mentioned in Q2 A. Multiplexer and any one 2-input gate. Q3 [10 Marks] [ Quine-McCluskey (Tabular) minimization ]

Optimize the Boolean expression F (w, x, y, z) =

m(0, 2, 4, 6, 8) + dc (10, 11, 12, 13, 14, 15) using Quine-

McCluskey (Tabular) minimization method. (a) Generate all prime implicants using cubes generation (b) Use covering algorithms to find reduced Boolean expression. (No need to draw logic diagram). Q4 [10 Marks] [Topic: FSM Controller Design & Synchronous Counter Design using D/T/JK/RS FFs]

A. [5] Design a synchronous Mod 10 counter using either D or T Flip Flops. B. [5] Design a synchronous Mod 6 counter using JK Flip Flops. In both cases of designing counter: Draw FSM diagram for counter, derive excitation of FF to be used in your counter, create state table, minimize logic expression for FF inputs and draw logic diagram of counter. (You can use result of earlier questions directly) Q5 [14 Marks] [Topic: Digital System Design]

Assuming you have a 1Hz clock pulse generator and six BCD to 7-segment display driver with display, design a Digital clock with Hour (12 Hour Format), Minute and Second counter. You have to design all required counter and connection of all counters. Draw a neat Logic Block Diagram of your Designed Digital Clock. Hint: 12 hour format means, required hour counter has 12 states from 0 to 11, but it have 2 BCD output with one is 1 bit and other is 4 bits. For simplicity assume 12.30PM can be displayed as 00.30PM and 00.30AM as 00.30AM. (You can use result of earlier questions directly).