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Autonomous Test Structures for Synchronous Sequential Circuits

Miosaw Chodacki
Faculty of Computer Science and Materials Science University of Silesia Katowice, Poland miloslaw.chodacki@us.edu.pl
AbstractThe paper shows an influence of a choice of autonomous testing structure on fault coverage in synchronous digital sequential circuit testing. In order to increase testability of sequential circuit during testing, its memory module usually undergoes a disconnection. At the time the testing structure gains access to no-primary output of the testing circuit. The circuit undergoes transformation into combinational circuit. A possibility of disconnection of a memory module results from including of multifunctional registers which execute a circuit memory function. It turns out that high fault coverage may often be gained without disconnection of the module. Thus, it is not necessary to apply such registers. Therefore the complexity of circuit is limited as far as a circuit area overhead for its application and additional mode control during its work are concerned. Nevertheless, it is not always possible. Even partial disconnection of memory modules during testing phase enables to increase fault coverage due to increasing circuit testability. Simulation studies carried out on a considerate amount of ISCAS'89 testing circuits set show rightness of introduced conception of sequential circuits testing without interference with its memory function. An important factor enabling suggested approach is an adequate choice of autonomous testing structure. Keywords biult-in self-test, self-test path, pseudorandom test, digital circuit testing

Dariusz Badura
Institute of Information Technology Katowice, Poland dariusz.badura@wsti.edu.pl

I.

INTRODUCTION

The testing of digital circuits is a very important component in designing electronic devices. The Built-In Self Test (BIST) structures are most often designed as Test Pattern Generator (TPG) and Test Response Compactor (TRC) systems, based on Linear Feedback Shift Registers (LFSR) and Multi-Input Signature Registers (MISR) [1]. There are also alternative Autonomous Test Structures (ATS) completed basically with Self-Test Path (STP) and Circular Self-Test Path (CSTP). In general, however, it is impossible to cover all failures, thus it is justified to search for more effective ATSs. The design of minimal ATSs of appropriate high diagnostic efficiency is a difficult task. The functioning of STP or CSTP is highly dependent on the function of the circuit under test, thus posing the problem of proper ATS selection, in general. The commonly used mechanism enhancing testability of a

sequential system understood most generally as an ability to control and observe internal system nodes with its primary outputs is disconnection of its Memory Modules (MM) at the test stage. Then, a difficult to test synchronous sequential circuit by nature is converted into a more easily testable combinational circuit; such transformation requires, however, appropriate MM components and area overhead to be chosen to perform additional functional control, e.g. multi-functional BILBO registers. The problem is to design a ATS which can be used without transformation of a synchronous sequential circuit during testing, thus also without intervention in the sequential circuit specification, while expecting similar testing effectiveness measured at least with the value of Fault Coverage (FC). It has been found that this cab be achieved even by using a test of the length comparable to that of pseudodeterministic test and significantly shorter than that of pseudorandom test prevailing in BIST applications. The effective ATS that requires no intervention in MM block of a synchronous sequential system at the testing stage provides significantly easier hierarchical testing of digital circuits, packages and systems. However, sometimes this is impossible, and the implementation of a MM subset of a sequential circuit into ATS significantly enhances the testing efficiency, as described in this article. In this paper the results of simulations of various ATS configurations enabling enhancement of diagnostic effectiveness, and even in some cases the reduction of area overhead to its hardware implementation are presented. II. AUTONOMOUS TEST STRUCTURE

ATS basic structure is understood as a shift register, of which a feedback is the testing circuit. As an ATS structure role a self-test path (STP) or circular self-test path (CSTP) may be used [2]. Fig. 1 shows an ATS structure which covers matrixes of input and output connections, additional shift feedback and set of switches controlling type of ATS work, apart from above mentioned. Influence of choice of feedback and connection matrixes on the increase of testing effectiveness will be shown later on. The ATS structure shown on Fig. 1 has a simulate model character, of which operation is described by register with Non-linear Feedback Shift Register (NLFSR) in a simplified method [3].

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TOP-BOTTOM LFSR (id 6000-7500), additional external and internal linear feedback are possible.

To configure STP/CSTP register connections with the circuit CUT, the following connection diagram types were distinguished: INPUT MATRIX 1 (id 1-300), complex connections available to the part of the STP/CSTP register that controls inputs of the tested circuit. INPUT MATRIX 1 LONG (id 300-600), complex connections, while allowing connections with any component of the STP/CSTP register. INPUT MATRIX E (id 600-900), simple connections. INPUT MATRIX FREE (id 900-1200), connections through XOR matrices, but only with those STP/CSTP register cells that control input of tested circuit. INPUT MATRIX FREE LONG (id 1200-1500), connection through XOR matrices with any STP/CSTP register cells. OUTPUT MATRIX 1 (id 1-100), complex connections, available for those cells of STP/CSTP register that are responsible circuit response. OUTPUT MATRIX connections. E (id 100-200), simple


Figure 1. Autonomous Test Structure.

where: V(t+1) is a vector of register outputs in a consecutive, discreet moment of time t. V(t) is a vector of register outputs in current moment t, T is a square matrix of connections describing structure of a register, F(V(t)) is a vector of nonlinear functions introduced to the register as a feedback. The size of vectors V(t+1), V(t) and F(V(t)) as well as T matrix are connected with a length of p register (number of D type flipflops). NLFSR register operation may be described as follows (1):

V (t + 1) = T V (t ) F (V (t ))

(1)

OUTPUT MATRIX FREE (id 200-300), connections through XOR matrices, but only with those STP/CSTP register cells that control output of tested circuit.

Influence of output connection matrix on NLFSR register function may be shown as a square matrix form, OM (2):

V (t + 1) = T V (t ) OM F (V (t ))

(2)

OM matrix function is a modification of output signals of testing circuit by a change of connections of circuit primary outputs with an ATS register. Depending on a structure type of the matrix, there are various functionalities that can be singled out. Similarly, an operation of IM matrix of input connections may be shown. Under are ATS structure configuration modes taking into consideration additional non-linear feedback and connection matrixes. The following linear feedback types can be chosen when configuring ATS model: AIJ TOP-BOTTOM LFSR (id 1-1500), additional external and internal linear feedbacks are possible. BOTTOM LFSR (id 1500-3000), additional internal linear feedbacks is possible. SHIFT LFSR (id 3000-4500), no additional linear feedback. TOP LFSR (id 4500-6000), additional external feedback is possible.

In brackets above there are identifiers being useful in analysis of simulation graphs presented in Fig. 3, 4, 5 and 6. For example, the ATS identifier equals 5100 indicates an ATS with additional linear feedback of TOP LFSR type and the input connection matrix INPUT MATRIX 1 LONG enabling connection of the tested circuit input with any STP or CSTP register component, and the output connection matrix OUTPUT MATRIX FREE, allowing an additional XOR matrix structure containing logic functors of the exclusive sum ExOR to be generated. The effectiveness of STP/CSTP depends mainly on: Length of STP/CSTP register. Length of test sequence. First state of STP/CSTP register and initial state of MM for synchronous sequential circuits. Schema of connection STP/CSTP to circuit.

The function of Output Matrix E, that is an identity matrix, is described as follows (1)

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1 0 0 0 0 0

0 1 0

0 0 0 0 1 0 0 0 0 0

0 0 0

0 0 0

0 0 0 0 0 0

1 0 0 0 1 0 0 0

f0 (Vm 1 ( t ),..., V p 2 ( t ), V p 1 ( t )) f1 (Vm 1 ( t ),..., V p 2 ( t ), V p 1 ( t )) f (V ( t ),..., V ( t ), V ( t )) p2 p 1 2 m 1 (1) 0 fm 1 (Vm 1 ( t ),..., V p 2 ( t ), V p 1 ( t )) 0 0 0 1 0


0 0 0

III.

SIMULATION EXPERIMENTS

The function of Output Matrix 1 is shown in (2). The function of Output Matrix 1 is presented in (2). This type of matrix must satisfy the condition (3).

1 0 0 0 0 0

0 0 1 0

0 0 0 1 0 0 1 0 0 0

0 0 0

0 0 0

0 0 0 0 0 0

1 0 0 0 1 0 0 0

f0 (Vm 1 ( t ),..., V p 2 ( t ), V p 1 ( t )) f1 (Vm 1 ( t ),..., V p 2 ( t ), V p 1 ( t )) f (V ( t ),..., V ( t ), V ( t )) p 2 p 1 2 m 1 ( 2) 0 fm 1 (Vm 1 ( t ),..., V p 2 ( t ), V p 1 ( t )) 0 0 0 1 0


0 0 0

In a computer ATS structure simulation, 75 possible configuration types were identified. Each configuration is determined by a type of additional linear feedback, matrix of input connections, matrix of output connections (Fig. 1). For each configuration, a simulation of 100 random values of above mentioned parameters both for STP structure as well as circular CSTP. In a simulation of sequential circuit, the memory module was not disconnected, which hampers identification of faults but does not force the module multifunctional feature operation. Due to such approach, the realization of memory module (MM) is simpler. Additional control of work type of block MM is avoided and circuit area overhead is limited. The aim of the experiment is to investigate a possibility of a circuit sequential testing using only its primary outputs. For testing effectiveness purpose, measured by value of fault coverage (FC), researches with elements of MM module circuit partially implemented to an ATS structure were undertaken. (Fig. 5 and 6). These ATS structures generate pseudorandom tests that are used in BIST technique primarily. Simulation graphs, presented in the article, are related to s298 testing circuit of ISCAS'89 testing circuit benchmark [4]. The s298 circuit is a synchronous sequential circuit (traffic light controller), which has 3 inputs, 6 outputs, 15 D type flipflops, 119 logic gates and 308 declared faults like single stuck at 0 or 1 [5]. Instead of relatively low number of logic gates and memory modules elements, a detection of all faults is very difficult. Experiments results for most of ISCAS'89 testing circuit will be represented in the next subsection (Tables 2 and 3). In Fig. 3 is shown graphs of relations between a length of generated sequences (a), coverage FC (b) and configuration type ATS and a graph of relations between FC and sequences length for all ATS configurations with STP (c) structure. An analysis of 3.a graph results in observation of major differences in length of sequences generated for various STP configuration types. The smallest sequences lengths are generated by the simplest STP structure without additional feedback (id 30004500). Instead of such small lengths of sequences, STP path configured by this method enables to gain a substantial coverage STP value (Fig. 3.b). It is worth to underline significant concentration of FC value, especially for STP (id 3000-4500), which shows a relatively strong correlation between a configuration type and FC gained value. Table I shows values of sequences lengths, FC and above mentioned correlation for all ATS configuration for STP path (id 30004500). In the table it is noticeable that correlation factor for couple ATS configurations, that is with IDs 3100-3199, 34003499 and 4100-4199 is higher than 0.8, in such case there is a strong stochastic dependence between FC value and STP configuration type. Certainly, as stated earlier, an ATS structure diagnostic effectiveness depends on other parameters, for example text length and testing circuit structure, which is its feedback.

i row 1 jcol m

! OM irow jcol = 1

jcol 1 i row m

! [OM irow jcol ] = 1

(3)

The function of Output Matrix Free is shown in (4).

1 0 0 1 0 0 0 f0 (Vm 1 ( t ),..., V p 2 ( t ), V p 1 ( t )) 0 1 1 1 0 0 0 f1 (Vm 1 ( t ),..., V p 2 ( t ), V p 1 ( t )) 1 1 0 0 0 0 0 f (V ( t ),..., V ( t ), V ( t )) p 2 p 1 0 1 2 m 1 ( 4) 0 0 0 0 1 0 0 0 fm 1 (Vm 1 ( t ),..., V p 2 ( t ), V p 1 ( t )) 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 For this type of connection matrix there is the condition in (5).

irow 1 jcol m

[OM

irow jcol

]= 1

(5)

The connection schemas of these matrixes are presented in Fig. 2. The analogous notation can be applied to input connection matrices of Input Matrix type.

Figure 2. Output matrixes. a) Output Matrix E, b) Output Matrix 1, c) Output Matrix Free

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Fig. 4 shows analogical graphs for an ATS structure based on circular self test path. In comparison to graphs for STP (Fig. 3) CSTP structure generates longer sequences and enables to gain a little larger FC. Correlation between FC value and CSTP configuration type is smaller than for STP structure. It may be observed especially for structures identified by 3000-4500 range (Fig. 4.b). When comparing graphs in Fig. 5.a and 6.a or 5.c and 6.c, it may be observed that CSTP generates longer sequences than STP in a vast majority of various ATS configuration types. CSTP in 3000-4000 range generates sequences with length comparable with other CSTP configurations, in opposite to STP path. There are still noticeable areas of strong correlation between ATS configuration type and an FC (Fig. 5 and 6 in part b.). Some CSTP configuration types, identified by 49004999, 1700-1799 and 1800-1899 (Fig. 6.b) enable to gain FC coverage at 0.4 0.7 level, therefore being significantly smaller in comparison with other CSTP configuration types. In comparison, every STP configuration type (Fig. 5.b) enables to gain an FC more than 0.5 (apart from insignificant cases of single examples in range of those types, which are represented by separated points below 0.5 values Fig. 5.b).
Figure 3. Self-Test Path for s298 benchmark circuit. a) Length of sequence vs. type of ATS, b) FC vs. type of ATS, c) FC vs. Length of sequence for all ATS configuration.

An including of even a single memory modules MM elements to STP/CSTP structure results in a significant increase of gained FC. In comparison there was an research based on including of 7 randomly selected elements of a memory circuit, among 14 such elements existing in s298 circuit, to an ATS structure. Increases of an FC were illustrated in Fig. 5 and 6, respectively for STP and CSTP.
TABLE I. CORRELATION BETWEEN FAULT STP for s298 circuit ATS
Length of sequence Fault Coverage Correlation

MIN 3000-3099 3100-3199 3200-3299 3300-3399 3400-3499 3500-3599 3600-3699 3700-3799 Figure 4. Circular Self-Test Path for s298 benchmark circuit. a) Length of sequence vs. type of ATS, b) FC vs. type of ATS, c) FC vs. Length of sequence for all ATS configuration. 3800-3899 3900-3999 4000-4099 4100-4199 4200-4299 4300-4399 4400-4499 14 16 7 13 7 24 16 20 4 13 20 7 2 13 6

MAX 27 29 20 24 17 40 32 37 21 33 39 53 17 27 18

MIN 0.678 0.688 0.230 0.503 0.156 0.737 0.604 0.567 0.230 0.575 0.542 0.191 0.178 0.555 0.175

MAX 0.812 0.815 0.532 0.714 0.575 0.821 0.685 0.704 0.558 0.685 0.688 0.867 0.529 0.717 0.633 0.695 0.831 0.629 0.153 0.809 0.687 0.463 0.116 0.692 0.455 0.202 0.870 0.537 0.342 0.607

Couple types of STP configurations, with IDs 3300-3399, 3700-3799 and 4000-4099 have a small correlation factor (about 0.1 0.2). Other STP configurations enable to reach relatively high correlation value factor. A high correlation factor shows a large ATS structure stability in a sense of possibility of gaining FC at a certain level.

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COVERAGE AND ATS (STP)

IV.

RESULTS

Tables 2 and 3 show a comparison of values of fault coverage gained by various methods and testing structures and a comparison of FC with model presented in this paper. Due to a large number of ATS testing structure simulations made, (7500 simulations of ATS various configurations for a single testing circuit) in researches, length sequences were limited to 1000 testing vectors. Such limitation is too large for many ISCAS'89 circuits, for which tests are usually applied for the length of couple to several dozen thousands of testing vectors. Limitation of sequences to 1000 testing vectors is visible in Fig. 3 and 4, especially in Fig. 5 and 6 in part a) and c). In despite of such limitation and ATS structures testing simulation without direct access to circuit MM, given fault coverage results are better than less complex s298, s349, s641 and s713 circuits in comparison to resolutions from literature. In many cases FC results are comparable with, for example, s208.1, s953 circuits. Fault coverage for rest of testing circuit represented in tables 2 and 3 are significantly smaller in comparison with other methods or testing structures. Tables 1 and 2 for s298 circuit (marked *) gained FC significantly greater (for about 0.1) than those with a help of other methods or testing structures. In this case, to ATS structure only 7 out of 14 available circuit memory modules were introduced. An increase of FC in this ATS structure configuration is visible in Fig. 5 and 6 in part a) and c).
TABLE II. Iscas89 Circuit s208.1 s298 s349 s444 s641 s713 s820 s953 s1196 s1238 Figure 6. CSTP for s298 benchmark circuit with 7 D-type flipflop included. a) Length of sequence vs. type of ATS, b) FC vs. type of ATS, c) FC vs. Length of sequence for all ATS configuration. s1423 s1494 cite from
COMPARISION OF METHODS

Figure 5. STP for s298 benchmark circuit with 7 D-type flipflop included. a) Length of sequence vs. type of ATS, b) FC vs. type of ATS, c) FC vs. Length of sequence for all ATS configuration.

Fault Coverage
CA2 / ATPG Gatto ATPG LP Gatto+ CSTP In this paper

Simulation researches were directed to such ATS structure choice, without direct access the testing circuit memory block, would cover FC at a level comparable with classic structures of independent TPG generator and TRC compactor of circuit responses based on registers with LFSR/MISR linear feedback.

0.673 0.677 0.876 0.876 0.973 0.978 0.863 0.926 0.873 0.873 0.826 0.826 0.598 0.949 0.983 0.990 0.932 0.997 0.812 0.945 0.882 0.896 0.877 0.964 [6]

0.679 0.886 0.890 0.873 0.826 0.918 0.992 0.946 0.963 0.847 [7]

1.000 0.877 0.984 0.924 0.874 0.877 0.529 0.991 0.995 0.960 0.973 0.972 [8]

0.697 0.886 0.978 0.924 0.873 0.826 0.941 0.991 0.995 0.944 0.967 0.960 [9]

0.748 0.886 0.833 0.831 0.834 0.841 0.641 0.622 [10]

0.995 0.889 0.997* 0.991 0.875 0.921 0.862 0.493 0.987 0.891 0.836 0.530 0.714

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TABLE III. Iscas89 Circuit s208.1 s298 s349 s444 s641 s713 s820 s953 s1196 s1238 s1423 s1494 cite from

COMPARISION OF METHODS

Fault Coverage
FSM ATPG CA GA HITEC BDD CCPS CA 90/150 In this paper

0.976 0.913 0.954 0.317 0.887 0.848 0.965 0.995 0.999 0.971 0.445 0.984 [11]

1.000 0.893 0.969 0.924 0.886 0.846 0.528 0.993 0.894 0.854 0.866 0.960 [11]

0.860 0.860 0.954 0.957 0.787 0.820 0.956 0.956 0.518 0.564 [12]

1.000 0.893 0.968 0.924 0.886 0.846 0.528 0.993 0.894 0.854 0.866 0.960 [13]

0.948 0.238 0.610 0.138 0.886 0.847 0.456 0.994 0.942 0.915 0.635 0.559 [13]

0.995 0.889 0.997* 0.991 0.875 0.921 0.862 0.493 0.987 0.891 0.836 0.530 0.714

would require a simulation in general case in advance. It is not always possible, for many testing circuits a great fault coverage was gained after including of memory modules of testing circuit into ATS structure. A choice of ATS structure connection matrix configuration with tested circuit is of a great significance. As shown in researches (Table I), a particular connection matrix configuration has a large significance for gaining a high FC. A length of testing sequence is significant for an increase of fault coverage. Due to a large number of researches delivered, the test length was limited to 1000 vectors, which is too big limitation, in comparison to the most of ISCAS'89 circuits. Therefore, results shown in tables II and III for more complex test circuits have this inconvenience connected with test length limitation. Nevertheless, in the most cases fault coverage is comparable with resolutions from cited literature, taking into consideration that ATS structures have not had direct access to memory modules of tested circuits. An ATS structure choice, which would not require disconnection memory module during testing time and that would enable a properly high fault coverage makes sequential circuit testing an easier diagnostic process. REFERENCES
[1] [2] Ch. E. Stroud, A desginer's guide to built-in self-test, Springer, 2002 ISBN 1402070500, 9781402070501. M. Chodacki, D. Badura, The stochastic model of pseudorandom testing of digital sequential circuit, Proceedings of XXVIII th International Autumn Colloquium ASIS 2006 Advanced Simulation of Systems, Vranov near Brno 12-14 september, Czech Republic. D. Badura, Design techniques for self-testing circuits and boards using non-linear feedback shift register, Scientific work of the University of Silesia, No 1280, 1992 (in Polish). http://courses.engr.illinois.edu/ece543/iscas89.html http://www.eecs.umich.edu/~jhayes/iscas/s298.html F. Corno, P. Prinetto and M. Sonza Reorda, A genetic algorithm for automatic generation of test logic for digital circuits, IEEE International Conference on Tools with Artificial Intelligence, Toulouse, France, November 1996. F. Corno, P. Prinetto, M. Rebaudengo, M. Sonza Reorda, A parallel genetic algorithm for automatic generation of test sequences for digital circuits, International Conference on High-Performance Computing and Network, Brussels, Belgium, April 1996. F. Corno, P. Prinetto, M. Rebaudengo, M. Sonza Reorda, A test pattern generation methodology for low power consumption, VTS98, 16th IEEE VLSI Test Symposium, Monterey, CA (USA), April 1998. F. Corno, P. Prinetto, M. Sonza Reorda, R. Mosca, Advanced techniques for GA-based sequental ATGs, IEEE Design&Test Conference, Paris, France, March 1996. F. Corno, P. Prinetto, M. Rebaudengo, M. Sonza Reorda, An Experimental analysis of the effectiveness of the Circular Self-Test Path technique, EURO-DAC94, IEEE European Design Automation Conference, Grenoble, France, September 1994. S. Chiusano, F. Corno, P. Prinetto, M. Sonza Reorda, Cellular Automata for deterministic sequential test pattern generation, VTS97, 15th IEEE VLSI Test Symposium, Monterey, CA (USA), April 1997. F. Corno, H. J. Patel, E. M. Rudnicki, M. Sonza Reorda, R. Vietti, Enhancing topological ATPG with high-level information and symbolic techniques, ICCD98, International Conference on Circuit Design, Austin, Texas, USA, October 1998. F. Corno, M. Sonza Reorda, G. Squillero, Evolving Cellular Automata for self-testing hardware, ICES2000, Third International Conference on Evolable Systems, From Biology to Hardware, Edinburgh, UK, April 2000.

Diagnostic effectiveness of proposed ATS structure model is comparable with testers based on Cellular Automata, automatic test generators (ATPG) and evolutionary models and other structures described in [6], [7], [8], [9], [10], [11], [12], [13]. The essence of presented ATS model is testing sequential circuit without direct access to its memory module, which generally decreases sequential circuit testability. In such ATS structure configuration for circuits with lesser complexity level, more FC values were gained in comparison with resolutions from other papers. For more complex circuit, a comparable level of value was gained. In rare cases, gained fault coverage was significantly smaller. In those cases, in which FC circuit values were the smallest, the importance of test length as well as a lack of exploitation of direct access to no-primary outputs of testing circuit memory module have appeared. Even though in many cases the proposed resolution does not ensure sufficient level of fault coverage, in other cases it enables to reach an expected level of coverage with a simultaneous costs limitation. V. CONCLUSIONS

[3]

[4] [5] [6]

[7]

[8]

[9]

[10]

An ATS model structure proposed in this paper is based on a STP path or a CSTP together with additional connection matrixes and linear feedback. Even the simplest ATS structure (STP path, circular CSTP without additional feedback), which does not have direct access to circuit MM for many ISCAS'89 testing circuits enabled fault coverage at a very high level, greater to other methods and testing structures. This property of some ATS structures enables multifunctional register usage limitation, which fulfill a role of a sequential circuit memory, therefore it enables a limitation of general costs connected with its implementation and provide of control of their work mode. However, a cancellation of multifunctional feature of registers

[11]

[12]

[13]

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