Design of a Low-Noise Amplifier using Complementary and Current-Reused Technology

Chang-Hsi Wu* and Kuan-Lin Liu and Wei-Chen Chen Department of Electronic Engineering Lunghwa University of Science and Technology 300 Wan-Shou Rd. Sec.1, Kueishan, 33306 Taoyuan, Taiwan, R.O.C.
Abstract- A 3.5GHz CMOS low noise amplifier (LNA) for WiMax receiver based on CMOS 0.18m process is presented in this paper. To achieve low-power consumption and low noise, the proposed LNA employs complementary and current-reused techniques. The LNA provides a gain ( S 21 ) of 11dB while drawing 6.5mW from 0.75-V supply voltage. The LNA achieves 4.6dB noise figure (NF) in the frequency of 3.5GHz. The measured P1-1dB and IIP3 of the proposed LNA are -18 and -9dBm, respectively. The size of the chip is 0.95 mm x 0.85 mm. I. INTRODUCTION
VDD
L

VBIAS 2

Rbias

RFout

Cout

Ccopuling

CPass

RFin

WiMAX (Worldwide Interoperability for Microwave Access) is a communication technology for wirelessly delivering high-speed internet service to large geographical areas. The 2005 WiMAX revision provided bit rates up to 40 Mbit/s with the 2011 update up to 1 Gbit/s for fixed stations. It is a part of a fourth generation, or 4G, of wireless-communication technology, WiMAX far surpasses the 30-metre (100-foot) wireless range of a conventional WiFi local area network (LAN), offering a metropolitan area network with a signal radius of about 50 km (30 miles). The objective of the LNA design is to achieve high-gain, low power, low noise, low group delay and high linearity performance. There are four representative works of LNA designs up to now: (1)LC-filter-base [1] (2)Feedback [2] (3) Distributed [3] (4)Current-reused [4][5] Recently a LNA design is proposed with the technology of thermal noise and IM2 distortion canceling [6] which can effectively reduce noise generation. In addition, M. Ben Amor, A. Fakhfakh, H. Mnif and M. Loulou proposed Current-Reused architecture [4] to design a high linearity with low noise, low power consumption of the technology based on CMOS 0.18m process. In this paper, design and analysis of the proposed LNA topology are presented in Section II. Measured results and characterization of the designed LNA are described in Section III. And then, the conclusions are stated in Section IV of this paper. II. CIRCUIT DESIGN AND ANALYSIS

Cin

Rbias

L
VBIAS 1
Fig. 1. Schematic of a typical current-reused LNA

power consumption of LNA while preserve high-gain. However, the traditional current-reused LNA topology uses a NMOS as the cascaded stage which needs an additional DC bias at the gate terminal that will affect the integrity of signal. Besides, it requires a larger supply voltage of VDD to keep saturation operation of transistors. VDD
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LD1

R2

C2 C3 LG

C5

C4 M3

C1
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M1

R3

R1
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LS

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Fig. 2 Schematic of the proposed Complementary and Current-reused LNA

The typical schematic of current-reused LNA is shown in the Fig. 1. The technique of current-reuse can reduce the

In this paper, a complementary and current-reused LNA is proposed, as illustrated in Fig. 2. To reduce the power consumption, not only current-reused but also complementary techniques are used. Appling the technology of current-reused by the complementary NMOS and PMOS uses only two lower bias voltages which consumes lower power. In Fig. 2, M1 M2 are complementary common-

978-1-4673-2185-3/12/$31.00 2012 IEEE

source amplifier. And M 3 M 4 construct current-reused cascade amplifier which can achieve high gain and lower noise figure. In addition, noise optimization and input matching of the proposed LNA can be achieved by suitable choices of the passive components LG and C1 . The resistors R1 R2 R3 and R4 are used to provide the bias path of the transistors. LD1 LD 2 are equal parts divided from the center-tapped inductor. C2 C3 C5 are coupling capacitances. The capacitor C4 provides an ac ground to separate the loads of the first and second stages of the current-reused amplifier. The inductor LD 2 and capacitor

Cgd 4

VD

RFout
LD1
RD1


Vgs 4

LD 2

Cgs 4

g m 4Vgs 4

RD 2

Z out

Fig. 4. Small signal equivalent circuit of the output of the proposed LNA.

C. The Gain of LNA As shown in Fig. 5, the voltage gain of the proposed LNA can be approximately described as RFout g m3 g m 4 SLD1 LD 2 ( g m1  g m 2 ) (3) | RFin {Cgs 3  SLG Cgs 3 [SCgs1  Cgs 2 ]}(1  S 2Cgs 4 LD1 ) Equation (3) shows that the sizes of transistors M 1 and M 2 are significant for the voltage gain of the proposed LNA.
RFin

C6 are designed to achieve output matching.

A. Input Matching Consider the small signal equivalent circuit of input of the proposed LNA as shown in Fig. 3. The input impedance of the proposed LNA can be approximately described as
RF in R1 Zin LG


LG
Cgs1  Cgs 2


( g m1  g m 2 )Vgs1


g m 3Vgs 3


g m 4Vgs 4
Vgs 4


RFout

Vgs1


Vgs 3


Cgs 3

LD1 Cgs 4

LD 2

R2

Vgs1

Cgs1  Cgs 2


( g m1  g m 2 )Vgs1

LS

Fig. 3 Small signal equivalent circuit of the input of the proposed LNA .

where R1 R2 are bias resistors respectively. Thus the input impedance of the proposed LNA can be approximately described as 1 (1) Zin | RG  SLG  S (Cgs1  Cgs 2 ) where RG represents the equivalent resistances of the inductors LG . In the equation (1), the inductor LG is used to provide resonance of the imaginary part of impedance over the operation band. B. Output Matching To consider the output matching, the small signal equivalent circuit of output of the proposed LNA is described in Fig. 4. The output impedance of the proposed LNA can be written as 1 1 [( RD1  SLD1 ) / / ]+ SCgs 4 SCgd 4 Z out | / /( SLD 2  RD 2 ) (2) 1 1+g m 4 [( RD1  SLD1 ) / / ] SCgd 4 where RD1 and RD 2 represent the equivalent resistances of the inductors LD1 and LD 2 , respectively. From equation (2), output matching can be achieved by adjusting inductor LD1,2 and the size of the transistor M 4 . III.

Fig. 5. Small signal equivalent circuit of the proposed LNA.

PREFORMANCES IF THE PROPOSED LNA

The proposed LNA is implemented in 1P6M 0.18m CMOS process. The measurement results are described in Fig. 6-Fig. 9. The power gain shown in Fig. 6 has peak value of 11dB. In Figure 7, the input matching has S11 low than 12dB and the output matching has S22 lower than -14dB. The noise figure depicted in Fig. 8 is 4.6dB at 3.5GHz. As in Fig. 9, the 1dB compression point ( P1dB ) is -10dBm and the input third-order intercept point ( IIP3 ) can attain -9dBm. The specification of the proposed LNA is compared with other papers in Table I. The overall performances of the designed LNA are summarized in Table II. The die photograph of the proposed LNA with chip size of 0.950.85 mm2 is shown in Fig. 10.

Fig. 6. Measured results of power gain

Reverse isolation (S12) Input Match (S11) Output Match (S22)

-37dB -12dB <-14dB

IV. CONCLUSION A 3.5GHz CMOS LNA fabricated in CMOS 0.18m process for WiMax applications is presented in this paper. By using the complementary and current-reused technique, the power consumption, noise and the IIP3 can be improved. The proposed LNA has conversion gain of 11 dB, a good P 1dB of -18dBm and a better IIP 3 of -9dBm, respectively, while it consumes only 6.5mW from 0.75V supply voltage. The chip size including pads is 0.95mm 0.85mm.
Fig. 7. Measured results of input matching and output matching.

Fig. 9. Measured results of IIP3 and P1-dB Fig. 8. Measured results of noise figure. TABLE I COMPARISON BETWEEN THE PROPOSED LNA AND OTHER PAPERS

Technology Type Freq(GHz) S11(dB) S21(dB) S22(dB) NF(dB) PD(mW) IIP3(dBm)

This Work 3.5 -12 11 -14 4.6 6.5 -9

[6] 5 -10 16.3 -14 3.5 26.2 -7.8

[7] 5 -12 10.2 -21 4.5 0.9 -16

[8] 2.4 -29.6 16.2 -30.2 3.7 42 -13

[9] 5.2 -11 10.9 -17 3.7 5.7 -5

TABLE II SPECIFICATION FOR THE DESIGNED LNA

Technology Type RF Frequency Range Supply Voltage Power Consumption Power Gain (S21)

TSMC 0.18m 1P6M 3.5GHz 0.75V 6.5mW 11dB

Fig. 10. Chip photograph of the proposed LNA.

V.

ACKNOWLEDGEMENT

The authors would like to thank the National Chip Implementation Center (CIC) Steering Committee for their valuable comments and suggestions in design and fabrication of this chip. The chip is fabricated by Taiwan

Semiconductor Manufacturing Company (TSMC) through Chip Implementation Center (CIC), Taiwan, R.O.C. REFERENCES
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