Vous êtes sur la page 1sur 2

Data Transfer Techniques and 110 Ports

155

for both input and output operations. Controlling the PC6 bit, using the bit set/reset feature of the 8255, enables the interrupt. A number of combinations of the ports in various modes of operation are possible, 10 satisfy varied system requirements.

6.2.2

Interfacing of 8255 to the Microcontroller

The 8255 programmable 110 port chip can be interfaced to the 8051 microcontroller in the same way an external memory device is interfaced through the emulated system bus using port 0 and port 2. The schematic diagram is shown in Figure 6.13. It is connected as if it is a RAM memory. In fact, the addresses of the registers of the 8255A are mapped on the data memory address space (memory-mapped-I/O) of the 8051. So, the registers have to be accessed using MOVX instructions.
P3.7 f--RD P3.6 t--WR P2.7 P2.6 P2.S P2.4 A1~ A14 A13 A12

"'\

...,
0

./

CE WE OE

co

PA~7
II> II>

ALE PO(~7)

EAl

r-i "Ht
O Figure 6.13

'"
co PB~7

~
A~1 V

_..

PC~7

, ~7

Reset ~

Interfacing the 8255 to 8051.

EXAMPLE 6.1: (i) Given the circuit diagram of Figure 6.13, find out the addresses assigned to the ports PA, PB, PC and the control register of 8255. (ii) Write a program to configure port A as input port and port B and port C as output ports all operating in mode O. (iii)'1 ~rite a program to READ one byte of data from port A and send the data to port Band porr C,
Solution: PA PB
PC CNTLREG

(i) Al5 A14 Al3 Al2 All AlO A9


1 1 1

A8
X X X X

A7
X X X X

A6
X X X X

AS
X X X X

A4
X X X X

A3
X X X X

A2
X X X X

Al
0
0

AO
0 1 0 1

1
1

1 1

1 1

1 1

1 1

X X X X

X X X X

X X X X

1 1

156

Microcontrollers: Principles and Applications

Therefore, the base addresses are: PA PB PC

= FOOOH, = FOOlH, = FOOO2,

CNTLREG = FOOO3H Because of the redundancy used in the decoding circuit, there exist many alternative address values for which each register can be accessed. The addresses with the redundant bits shown as X. (ii) The control word to be written into the CNTLREG is 90H for port A as input port, port B and port C as output ports and all the ports are operating in mode O. (iii) The program to initialize the ports to operate in mode 0 with port A as input and ports PB and PC as output ports and read one byte of data through port A and send the data to ports Band C is given below: MOV A, 90H ;loads control word in register A MOV DPTR, #E003H ;initializes pointer register MOV @DPTR, A ;loads control register MOV DPTR, #EOOOH ;PA address in the pointer register MOVX A, @DPTR ;reads data in PA register INC DPTR ;PB address in pointer register MOv}{ DPTR, A ;data sent to port B INC DPTR ;PC address in pointer register MOVX DPTR, A ;data sent to port C Instead of using absolute port addresses, it is a better practice to use symbolic name of the addresses using the BQU assembly directive as given below: PORTA CTLPRT MOV MOV MOV MOV MOVX INC MOVX INC MOVX EQU EOOO BQU BOO3 A, 90H DPTR, #CTLPRT @DPTR, A DPTR, #PORTA A, @DPTR DPTR DPTR, A DPTR DPTR, A

;loads control word in register A ;initializes pointer register ;loads control register iPA address in the pointer register ;reads data in PA register ;PS address in pointer register ;data sent to port B ;PC address in pointer register idata sent to port C

EXAMPLE 6.2:

Interface a digital-to-analog converter (DAC) through the 8255 PPI and generate a sawtooth waveform at the output of the DAC. Solution: A DAC can be interfaced through anyone of the three port lines. An 8-bit DAC, the 1408, is 'interfaced through port A as shown in Figure 6.14. The port operates in mode 0 and data transfer takes place in synchronous mode. However, if the data is changed at high