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IEEE TRANSACTIONS ON SEMICONDUCTOR MANUFACTURING, VOL. 14, NO.

4, NOVEMBER 2001

311

Precise Characterization of Long-Distance Mismatch of CMOS Devices


Ulrich Schaper, Member, IEEE, Carsten G. Linnenbank, and Roland Thewes, Member, IEEE
AbstractA new test structure is presented for the characterization of long-distance mismatch of complimentary metaloxidesemiconductor (CMOS) devices. A single circuit is used to characterize both transistors and resistors. High resolution is achieved by applying a four-terminal method with regulated reference potential to compensate for parasitic resistance effects. Measured data are presented for 0.5-, 0.35-, and 0.25- m CMOS processes to demonstrate the performance of this approach. In particular, the long distance matching behavior is compared to that of neighboring devices. Examples for linear and nonlinear distance dependencies are shown. The long-distance mismatch has to be taken into account in circuit designs with short channel transistors and with narrow resistors. Index TermsAnalog circuits, mismatch, modeling, MOSFETs, parameter variation, resistor, spatial variation, transistors, statistical analysis.

I. INTRODUCTION ISMATCH of active and passive devices limits the performance of analog and mixed signal circuits. These limits become increasingly important in future technologies with lower supply voltages and scaled device sizes [1], [2]. In such applications, often pairs of directly neighboring devices are used whose matching behavior has been investigated thoroughly in the literature [1][8] since it determines the achievable circuit accuracy. In specific circuits, however, devices which are required to match are also used with distances of several millimeters between them, e.g., in a chain of resistors operating as a voltage reference in an analog-to-digital converter (ADC). Long-distance mismatch of these devices [3], [8][10] can result in a loss of resolution of such ADCs. In this paper, a new long distance matching test structure is presented extending over a length of several mm. The measurement principle compensates for the influence of parasitic interconnect resistances. The method is demonstrated using devices from several complimentary metaloxidesemiconductor (CMOS) processes and experimental data showing different long distance effects are discussed. II. TEST STRUCTURE AND CHARACTERIZATION PRINCIPLE The test structure concept (Fig. 1) combines nMOS and pMOS transistors as well as different types of polysilicon and diffusion resistors in a single test assembly.
Manuscript received September 22, 2000; revised May 30, 2001. U. Schaper and C. G. Linnenbank are with Infineon Technologies AG, Corporate Frontends CFE TD SIM, D-81739 Munich, Germany (e-mail: Ulrich.Schaper@infineon.com). R. Thewes is with Corporate Research CPR, D-81739 Munich, Germany. Publisher Item Identifier S 0894-6507(01)09773-1.

The shift register located at the center of the test structure addresses each device under test (DUT) individually. One stage of the shift register consists of two flip-flops, two pass gates which separates the flip-flops and two transistors to reset the flip-flops to a definite logical state. The output of one stage is connected to the input of the next stage in order to get a sequential operation mode of the shift register. The output is used for selecting (on state) or deselecting (off state) the DUT connected to this stage. Therefore, the shift register uses only three clock signals, one for the reset of the shift register, one for selecting and one for deselecting the DUT. The number of the externally applied clock signals does not depend on the number of stages of the shift register. This feature is an advantage compared to binary addressing methods for the selection of the DUTs. On both sides of the shift register the devices to be characterized are arranged. Different types of devices with different geometry and orientations are combined building a unit which is marked with a black box in Fig. 1. These units are repeated times so that equally designed devices located at different positions on the chip are available. The layout (Fig. 2) has the geometrical form of a stripe, the height is determined by the pad array, the length is only restricted by the chip size. The pads are used for supply voltage and substrate contacts (4 pads), for the clock signals (3 pads), for the current path, voltage measurement, and voltage sensing (2 4 pads). Current setting and voltage measurement are done separately for the upper part of the test structure with p-doped related devices and for the lower part of the test structure with the n-doped related devices. The microphotograph (Fig. 3) shows a blowup of the test structure with different device sizes and orientations. The characterization principle (Fig. 4) uses a four-terminal is method with regulated reference potential. A current forced through the selected DUT and the resulting voltage drop at the DUT is measured (cf. [4], [5]). For precise characterization of this voltage drop at different positions of the long test ) at the structure, regulation of the reference potential (node selected DUT is necessary. For this purpose, the voltage drops of the interconnect providing over parasitic resistances are compensated using a force/sense the reference voltage method. As depicted in the figure, this is performed by the regulation loop using an operational amplifier (OPA). This OPA is integrated into the parameter analyzer Agilent 4156B, where the two connectors force and sense are used. Alternatively, earlier versions of the parameter analyzer can be used, but then the OPA has to be supplied externally, e.g., Texas Instruments OP07. Note, that the parasitic interconnect resistances and between the reference terminal of the selected DUT and the sense connector of the analyzer (or the inverting

08946507/01$10.00 2001 IEEE

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IEEE TRANSACTIONS ON SEMICONDUCTOR MANUFACTURING, VOL. 14, NO. 4, NOVEMBER 2001

Fig. 1. Test structure circuit and measurement setup. The shift register points to a DUT of the upper and the lower circuit. Different types of devices with different geometry and orientations are combined building a unit which is marked by a black box. DUTs are emphasized by dotted lines, all other transistors are select devices, all other resistors are related to parasitic interconnect resistances. The OPAs indicated are integrated into the parameter analyzer.

Fig. 2.

Example for the layout of the test structure in process B, total size: 6.1 mm

2 0.4 mm.

input of the OPA) do not have an influence on the characterization result since current and thus also voltage drop in this path are negligible due to the high input resistance of the instrument (or OPA). The same argument is valid for the measurement of the DUT is connected to the voltmeter path where node with high input resistance via parasitic interconnect resistances . Voltage drops between the current source and the selected DUT also do not influence the measurement result due to the chosen characterization principle. III. RESULTS Results presented here originate from three different CMOS 0.5, 0.35, processes A, B, and C with minimal lengths and 0.25 m, respectively. The corresponding supply voltages and oxide thicknesses are given in Table I. Data acquisition was performed on wafer level with the semiautomatic

Fig. 3. Microphotograph showing a blowup of the test structure. The devices under test are arranged in blocks of both sides of the shift register located at the center.

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Fig. 4. Characterization principle. A predefined current I is forced through the selected device, the current path is depicted by a thick line. The voltage drop V (N ) V (N ) over the device is measured by a voltmeter V . The voltage drop due to the parasitic resistors R in the path providing the reference potential of the selected DUT is compensated externally. The on-chip elements are included in the dotted box. The parameter analyzer supplies current source, and the sense voltmeter and the OPA where the force connector supplies V connector senses V .

TABLE I PROCESS DATA V , L , AND t AND SHORT DISTANCE MATCHING CONSTANTS FOR TRANSISTORS A AND RESISTORS A OF THE CONSIDERED TECHNOLOGIES

Fig. 5. (a) Measured gate-source voltage V of nMOSFETs (W=L = = 40 A; process B) versus position x. V is measured 4:4=0:35, I without (open symbols) and with (full symbols) potential regulation. The error bar indicates the 2 value of the short-distance mismatch. (b) Measured gate-source voltage V of nMOSFETs (W=L = 35:2=0:35, I = 320 A; process B) versus position x. V is measured without (open symbols) and with (full symbols) potential regulation. The voltage drop (solid line) due to parasitic interconnect resistances is compensated (dashed line) by the regulation circuit.

This relation, e.g., holds for the parameters threshold voltage or current factor in case of MOSFETs, or for the resisand are width and length of tance in case of resistors. is the (pair) matching constant. The the active device area, matching constants for the devices considered here are listed in Table I for reference. The matching characterization of the transistors is performed in a diode mode operation of the transistor with gate and drain terminals connected. The matching behavior is characterized for typical analog bias points, i.e., the transistor is operated in saturation. Starting with the equation for the drain-source current (2)

probe system Suss PA200. The electrical measurements were done with the high precision parameter analyzer Agilent 4156B. The clock signals were generated by a digital I/O card National Instruments PC-OPDIO-16 implemented into a PC. The output stages of the card are optically isolated, therefore there is no electrical noise transferred from the PC to the measurement system. The whole measurement system is controlled by a PC with an in-house written control program for the National Instruments LabView system environment. In the following, the measurement results are compared to the mismatch of directly neighboring devices, commonly named device pairs. The latter is usually described by a Gaussian distribution of a considered parameter whose standard deviation (short distance) follows the relation [1][8] (short distance) (1)

the following expression for the variance of the difference of the can be derived [11] for fixed current gate-source voltages (3) For typical analog bias region, i.e., V, the threshold voltage variation contributes more than 90% to the right-hand-side of equation (3). Therefore, the analysis of determined at only one bias point is a very good estifor this bias region. The standard deviation mation of for the parameter of a single device is determined from the pair matching by (4) The characterization principle and the regulation loop has been verified, the results are shown in Fig. 5(a) and (b). nMOS

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Fig. 6. Typical examples of measured gate-source voltage V versus position x for transistors in 0.35-m technology. (a) nMOSFET with W=L : = : , I A. The long-distance mismatch is smaller than the short-distance mismatch. (b) nMOSFET with W=L : =: ,I A. The long-distance mismatch is comparable to the short-distance mismatch for distances of mm. (c) nMOSFET with W=L : = : , I A. The long-distance mismatch is larger than the short-distance mismatch for distances of > : mm.

= 14

= 320

1x = 1 1x 0 5

= 35 2 0 79

=88 17 = 112 = 35 2 0 35

Fig. 7. Typical examples of measured normalized resistance R=R versus position x for high-ohmic polysilicon resistors in 0.35-m technology. (a) P-polysilicon resistor with L=W A. The long-distance : = : ,I mismatch is smaller than the short-distance mismatch. (b) P-polysilicon : A. The long-distance mismatch is with L=W : = : ,I comparable to the short-distance mismatch for distances of : mm. (c) : A. The long-distance P-polysilicon with L=W : = : ,I mismatch is larger than the short-distance mismatch for distances of > : mm.

= 35 2 2 2 = 5 = 25 = 35 2 1 1 1x = 1 5 = 35 2 0 55 = 1 25 1x 0 5

transistors from process B with [Fig. 5(a)] [Fig. 5(b)] are characterized at equal and A for m and currents per width ( A for m, respectively) which results in V. The measured an effective gate-source voltage are shown versus the posivalues of the gate-source voltage tion with and without adjustment of the reference potential by the regulation circuit. For comparison the corresponding short (short distance) is distance (pair matching) sigma value shown as error bar in the figure. In Fig. 5(a), the effect of regulation can clearly be seen, the differences between open and full symbols for increasing values of the distance indicate the increasing measurement errors. In this case, however, the measurement error is of minor importance for practical purposes compared to the effect of short-distance mismatch on the measurement result. In Fig. 5(b), on the other hand, characterization of long-distance mismatch without regulation leads to completely erroneous interpretation of the measured data. The parasitic resistance of the interconnect with a square resistance of 90 m /square causes a voltage drop of 8.3 mV/mm for a current of 320 A. Thus, for a precise and reliable general concept to evaluate long distance parameter variations such voltage drops must be compensated by the proposed regulation loop. The voltage error caused by the regulation loop is given by the OPA, in our case this error is less than 10 V.

Experimental findings of different long-distance mismatch behaviors for nMOS and pMOS transistors and for polysilicon resistors with different geometry from the 0.35- and 0.25- m technology are depicted in Figs. 611. Several wafers have been tested for both technologies. For each chip an analysis of the distance dependence were done. The findings show very different patterns ranging from no distance dependence over a linear gradient behavior to nonlinear distance distributions. These patterns change not only from wafer to wafer but also from chip to chip of the same wafer. One successful method was to classify these different patterns with respect to the channel length in case of transistors and with respect to the width in case of resistors. The examples shown here in Figs. 69 are picked out from typical examples. Long channel transistors and resistors with large widths show no or negligible long-distance mismatch effects compared to the corresponding pair mismatch [Figs. 6(a), 7(a), 8(a), and 9(a)]. On the other hand, devices which are sensitive to long-distance mismatch show again different distribution patterns including linear gradients, nonlinear distributions and dependence on the device orientation with respect to the wafer orientation. The specific findings are as follows. The characterization of the transistors (Figs. 6 and 8) was V has been done at a typical analog bias point. chosen. For transistors with long channels [Fig. 6(a):

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Fig. 8. Typical examples of measured gate-source voltage V versus position x for transistors in 0.25-m technology. (a) pMOSFET with W=L : = : , I : A. The long-distance mismatch is smaller than the short-distance mismatch. (b) pMOSFET with W=L : = : ,I : A. The long-distance mismatch is comparable to the short-distance mismatch for distances of : mm. (c) pMOSFET with W=L : = : , I : A. The long-distance mismatch is larger than the short-distance mismatch for distances of > : mm.

= 1 86

1x = 2 5 = 85 6 1x 2 5

= 25 6 0 57

=32 12 = 30 6 = 25 6 0 25

Fig. 9. Typical examples of measured normalized resistance R=R versus position x for P-polysilicon resistors in 0.25-m technology. (a) P-polysilicon resistor with L=W : = : ,I A. The long-distance mismatch is smaller than the short-distance mismatch. (b) P-polysilicon resistor with : A. The long-distance mismatch is L=W : = : ,I comparable to the short-distance mismatch for distances of mm. : A. The (c) P-polysilicon resistor with L=W : = : ,I long-distance mismatch is larger than the short-distance mismatch for distances of > : mm.

= 13 4 3 2 = 119 = 31 2 = 26 2 1 6 = 26 9 0 4 1x 2 5

1x = 5 = 62

, Fig. 8(a): ] the long-distance mismatch influence is negligible compared to the short-distance mismatch depicted as error bar in the Figures. For short channel , Fig. 8(c): transistors, however, [Fig. 6(c): ] distance dependencies are found in terms of a linear gradient. The polysilicon resistors (Figs. 7 and 9) are characterized at V a bias point corresponding to a voltage drop of over the resistor. Resistors with large widths [Fig. 7(a): , Fig. 9(a): ] do not show significant long-distance mismatch effects compared to the value of (short distance). For resistors with narrow widths, , Fig. 9(c): however, [Fig. 7(c): ] linear distance dependencies are found. The devices compared in each Figure (Figs. 69) are selected from the same chip respectively. The length of the test structure for the 0.25- m technology is longer than the one for the 0.35- m technology resulting in a higher number of measured data for a single test structure. Compared to the short-distance mismatch the long-distance mismatch effect increases when the channel length or the resistor width decreases. This behavior can be described to first-order qualitatively in terms of a gradient. In Table II typical gradients are listed with the corresponding device lengths or widths and compared with short

Fig. 10. Measured normalized resistance R=R versus position x for the same resistors but with different orientation. Narrow width resistors are sensitive to long-distance mismatch. This sensitivity depends also on the device orientation. (a) P-polysilicon resistor with L=W : = : , I A, process B, orientation in parallel to the wafer flat. The long-distance mismatch shows the same range as the short-distance mismatch, example taken from 2 different chips (full and open symbol). (b) The same resistors of the same chips as in Fig. 10(a) are oriented perpendicular to the wafer flat. The long-distance mismatch is much larger than the short-distance mismatch.

= 119

= 35 2 0 55

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TABLE II DISTANCE GRADIENT PARAMETER j = j COMPARED TO THE PAIR MATCHING PARAMETER  FOR DIFFERENT TRANSISTOR LENGTHS AND RESISTOR WIDTHS FOR 0.35- AND 0.25-m TECHNOLOGY

1P 1x

Fig. 11. Measured normalized resistance R=R versus position x of polysilicon resistors with small widths of different technologies. Narrow width resistors are sensitive to long-distance mismatch. Alternatively to the linear gradients [Figs. 7(c) and 9(c)], a nonlinear behavior is observed. The long-distance mismatch behavior is approximated in all cases by a second-order polynome (solid line). The long-distance mismatch is much larger than the short-distance mismatch indicated by the arrows. (a) High-ohmic polysilicon resistor with L=W = : ,I : A, process A, different chips are marked by different symbols. (b) High-ohmic polysilicon resistor with L=W : = : ,I : A, process B, different chips are marked by different symbols. (c) P-polysilicon resistor with L=W : = : , I : A, process C.

same wafer, respectively. In these cases the long-distance mismatch can be approximated by a second-order polynome. These nonlinear findings impose a severe limit to the circuit design. In circuits where e.g., a chain of resistors is used as a voltage reference, a quadratic behavior over a few mm distance cannot be compensated by means of circuit techniques. The nonlinear long-distance mismatch behavior of resistors may limit the applicability of such chains of resistors. IV. SUMMARY A method and a test structure are presented for precise characterization of long-distance mismatch of CMOS devices. The characterization principle allows to combine transistors and resistors in a single test assembly. The influence of parasitic resistances of interconnect lines is completely compensated using an active regulation circuit. The performance of the new approach is demonstrated on the basis of measured data from different CMOS processes. It is demonstrated that the long-distance mismatch can be larger than the short-distance mismatch for short channel transistors and narrow width resistors over a distance of 1 mm. The long-distance mismatch has to be taken into account in circuit designs where minimum size devices are used under the constraint that their absolute values have to match over a distance of order of mm. REFERENCES
[1] M. J. M. Pelgrom, H. P. Tuinhout, and M. Vertregt, Transistor matching in analog CMOS applications, in IEDM Tech. Dig., 1998, pp. 915918. [2] K. R. Lakshmikumar, R. A. Hadaway, and M. A. Copeland, Characterization and modeling of mismatch in MOS transistors for precision analog design, IEEE J. Solid-State Circuits, vol. SC-21, pp. 10571066, Dec. 1986. [3] M. J. M. Pelgrom, A. C. J. Duinmaijer, and A. P. G. Welbers, Matching properties of MOS transistors, IEEE J. Solid-State Circuits, vol. 24, pp. 14331440, Oct. 1989.

= 48 0 75 = 1 5 = 35 2 0 55 = 1 25 = 6 21

= 26 9 0 4

distance matching. The linear gradient is determined using the whole length of the test structure. Furthermore, the long-distance mismatch of short channel transistors or narrow width resistors depends on the orientation of the devices with respect to the wafer orientation and more over the long-distance mismatch can be a strong nonlinear effect. Resistors with narrow widths are found to be sensitive to the long-distance mismatch [Fig. 7(c)]. This sensitivity depends on the orientation, if they are oriented e.g., in parallel to the wafer flat [Fig. 10(a)] they show no long-distance mismatch, whereas the same devices on the same chip oriented perpendicular to the wafer flat [Fig. 10(b)] show a dominant long-distance mismatch behavior. The origin of the orientation dependence may be found by a closer look to the device processing. For all technologies considered a nonlinear behavior of the long-distance mismatch of short channel transistors and narrow width resistors can be found. Examples for polysilicon resistors are shown in Fig. 11 for 0.5-, 0.35-, and 0.25- m technology. Fig. 11(a) and (b) show examples taken from several chips of the

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[4] R. Thewes, R. Brederlow, C. Dahl, U. Kollmer, C. G. Linnenbank, B. Holzapfl, J. Becker, J. Kissing, S. Kessel, and W. Weber, Explanation and quantitative model for the matching behavior of polysilicon resistors, in IEDM Tech. Dig., 1998, pp. 771774. [5] C. G. Linnenbank, W. Weber, U. Kollmer, B. Holzapfl, S. Sauter, U. Schaper, R. Brederlow, S. Cyrusian, S. Kessel, R. Heinrich, E. Hoefig, G. Knoblinger, A. Hesener, and R. Thewes, What do matching results of medium area MOSFETs reveal for large area devices in typical analog applications?, in Proc. Eur. Solid-State Devices Res. Conf. (ESSDERC), 1998, pp. 104107. [6] H. P. Tuinhout, A. H. Montree, J. Schmitz, and P. A. Stolk, Effects of gate depletion and boron penetration on matching of deep submicron CMOS transistors, in IEDM Tech. Dig., 1997, pp. 631634. [7] P. A. Stolk, F. P. Widdershoven, and D. B. M. Klassen, Modeling statistical dopant fluctuations in MOS transistors, IEEE Trans. Electron Devices, vol. 45, pp. 19601971, Sept. 1998. [8] J. Bastos, M. Steyaert, R. Roovers, P. Kinget, W. Sansen, B. Graindourze, A. Pergoot, and E. Janssens, Mismatch characterization of small size MOS transistors, in Proc. IEEE Int. Conf. Microelectronic Test Structures (ICMTS), 1995, pp. 271276. [9] H. Elzinga, On the impact of spatial parametric variations on MOS transistor mismatch, in Proc. IEEE Int. Conf. Microelectronic Test Structures (ICMTS), 1996, pp. 173177. [10] O. R. D. Buisson and G. Morin, MOSFET matching in a deep submicron technology, in Proc. Eur. Solid-State Devices Res. Conf. (ESSDERC), 1996, pp. 731734. [11] A. Papoulis, Probability, Random Variables, and Stochastic Processes. New York: McGraw-Hill, 1965, ch. 7, p. 212.

Carsten G. Linnenbank was born in Warendorf, Germany, in 1971. He received the Dipl.-Ing. degree in electrical engineering in 1997. From 1997 to 1999, he was with the Research Laboratories of Siemens and Infineon Technologies. Since 1999, he is with Infineon Technologies, Corporate Front End. He is engaged in characterization and modeling of active and passive CMOS-devices. Mr. Linnenbank is a member of the Association of German Electrical Engineers (VDE) and the German Microelectronics and Mechatronics Society (GMM).

Ulrich Schaper (M91) received the Ph.D. degree in physics in 1981 from the Technical University Munich, Munich, Germany. In 1984, he joined the Siemens Semiconductor Group where he worked on parameter extraction of MOS devices. From 1986 to 1997, he was with the Siemens Corporate Research where he has been active on the modeling of GaAs HBT and HEMT devices and on the development of RF circuits. Since 1997, he is working on the characterization of mismatch of CMOS devices, now he is responsible for the matching activities at Infineon Technologies. He has authored or co-authored some 25 publications. Dr. Schaper is member of the German Physical Society.

Roland Thewes (M99) was born in Marl, Germany, in 1962. He received the Dipl.-Ing. degree and the Dr.-Ing. degree in electrical engineering from the University of Dortmund, Dortmund, Germany, in 1990 and 1995, respectively. From 19901995, he worked in a cooperative program between the Siemens Research Laboratories, Munich, Germany, and the University of Dortmund in the field of hot-carrier degradation in analog CMOS circuits. Since 1994, he has been with the Research Laboratories of Siemens AG and Infineon Technologies, where he has been active in the design of nonvolatile memories and in the field of reliability and yield of analog CMOS circuits. From 19971999, he managed projects in the fields of design for manufacturability, reliability, analog device performance, and analog circuit design. In 2000, he became member of the board of directors of Corporate Research of Infineon Technologies. He has authored or co-authored some 50 publications. He served as a member of the technical program committees of the International Electron Device Meeting (IEDM) and of the European Solid State Device Research Conference (ESSDERC), and he is a member of the technical program committees of the International Reliability Physics Symposium (IRPS) and of the European Symposium on Reliability of Electron Devices, Failure Physics and Analysis (ESREF). Dr. Thewes is a member of the German Association of Electrical Engineers (VDE) and the German Information Technology Society (ITG).