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EE 504L

SOLID STATE PROCESSING AND INTEGRATED CIRCUITS LABORATORY FALL 2013 FINAL PROJECT REPORT
INSTRUCTOR: Dr. KIAN KAVIANI

Submitted By

KARTHIK RAMASAMY USC ID: 5539-4733-38

University of Southern California

MING HSIEH DEPARTMENT OF ELECTRICAL ENGINEERING

TABLE OF CONTENTS

1. ABSTRACT 2. INTRODUCTION 3. THEORY 3.1 3.2 3.3 3.4 4. RESULT 5. DISCUSSION 6. CONCLUSION 7. REFERENCES MOSFET MOS CAPACITOR PN DIODE RESISTOR

1 2 3 3 8 10 13 16 33 35 35

LIST OF FIGURES
Figure 1: Figure 2: Figure 3: Figure 4: Figure 5: Figure 6: Figure 7: Figure 8: Figure 9: Figure 10: Figure 11: Figure 12: Figure 13: Figure 14: Figure 15: Figure 16: Figure 17: Figure 18: Figure 19: Figure 20: Figure 21: Figure 22: Figure 23: Figure 24: Figure 25: Figure 26: Figure 27: Figure 28: Metal Oxide Semiconductor Field Effect Transistor Two terminal MOS structure MOS transistor in accumulation region MOS transistor in depletion region MOS transistor in inversion region Structure of n-channel enhancement-type MOSFET Regions of operation of NMOS transistor V-I Characteristics of MOSFET Flat Band Energy Diagram of Al-SiO2-Si C-V Characteristics of MOS Capacitor PN Diode without external bias V-I Characteristics of PN Diode I-V Characteristics of Linear Resistor Transfer Line Measurement Test Structure Total resistance vs. length C-V Characteristics of Capacitor C-V Characteristics of Capacitor I-V Characteristics of PN DIODE PN DIODE Forward Voltage vs. ln( ) I-V Characteristics of MOSFET Extraction of MOSFET Threshold Voltage Extraction of MOSFET Saturation Velocity Graph of vs. Extraction of MOSFET and corresponding Plot of vs. Plot of

vs.

I-V Characteristics of MOSFET in linear region Extraction of Mobility and in Linear Region

ii

LIST OF TABLES

Table 1: Table 2: Table 3: Table 4: Table 5: Table 6: Table 7: Table 8:

Resistance of Three IC Resistors Sheet Resistance Measurement using Transfer Line Measurement (TLM) Iterative Approach for calculation of Value for plotting SQRT( ) vs. at = 6V vs. for

calculation

vs.

vs.

Calculation of

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NOMENCLATURE

K n F W L (lin)

Sheet Resistance [ohm/square] Ohmic Contact Resistance [ohm/square] Build-in Potential [V] Boltzmann Constant =8.617 x 10-5 [e V K-1] Ideality factor Permittivity of the free space = 8.85 *10-14 [F /cm] Oxide (Si02) relative permittivity =3.9 Oxide thickness [cm] Doping density of body [cm-3] Fermi Potential [V] Deby Length [cm] Oxide Charge [F] Flat band capacitance [F] Flat band voltage [V] The number of charges per unit area of the capacitor [F/cm2] MOSFET width [m] MOSFET channel length [m] Threshold Voltage [V]

(sat) Average mobility of carriers in the channel in saturation region [cm2/ V.sec] Saturation Velocity [cm/sec] Transconductance at saturation [m.S] Output transconductance [m.S] Channel Conductance [m.S] Average mobility of carriers in the channel in linear region [cm2/V.sec]

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1. ABSTRACT:

This report presents the results of a semiconductor device fabrication process done manually. The fabrication was conducted in a clean room 100 environment. The wafer used is a P-Substrate. The fabrication steps for applying each mask include deposition of photo-resist, prebake, exposure, development, post bake, ashing and etching. A total of 5 masks were used to create multiple MOSFETS, resistor, capacitor and diodes on the wafer. These devices were tested and the results are gathered for analysis. It was found that the extracted values deviates from the theoretical values and the reason behind are explained. Fabrication was carried in the Photonics Instructional Laboratory at the University of Southern California.

2. INTRODUCTION:
The first transistor was discovered at Bell Laboratories, which is the Point Transistor. Later due to the advancements in technology, the number of transistors tends to increase. According to MOOREs LAW, the number of transistors would double every 1.5 years. Today there are billions of transistors on a chip and the semiconductor industry is now a billion dollar business. The modern electronic circuits have now been evolved into ultra-large-scaled integrated (ULSI) circuits with extremely high performances. The silicon microchips, constituting with some silicon metal-oxidesemiconductor (MOS) transistors, have become indispensable key elements for our information society. For example, internet, mobile phones, video game players, digital cameras, and human-like robots could never be realized without the tremendous progress of the integrated circuit (IC) technology. The integrated circuits as well as their core device technology are expected to evolve further and with increasing importance in future intelligent society. The electronic circuit development has been accomplished with the downscaling of component size since the replacement of vacuum tubes with transistors 40 years ago. The circuit characteristics have benefited a lot from the downsizing. We are now able to integrate millions of transistors in a silicon chip with few centimeters square. The capacitance values are smaller in a smaller device. This leads to faster operating speed and lesser power consumption. The size reduction in individual device makes higher integration density possible and allows parallel operations, which in turn further increases the circuit speed. In addition to the device downsizing, the IC manufacturing methodologies have also been changed a lot during the past four decades. A readily thinkable change is the wafer size. The diameter of early wafer size was 50 mm and the latest one is 300 mm representing a 36 times increase in the chip area. The throughput is further enhanced with the downsizing, improved yield and the use of fully automatic highprecision machines and super clean environment. Thus the per-transistor and per-function cost has been reduced greatly. The key to minimum feature size is decided by photolithographic process. State-of-the-art photolithography processes use 193nm deep ultraviolet (DUV) light for imaging but, as device dimensions shrink ever more, the capabilities of such technologies have been exhausted and process costs are becoming prohibitive. EUV (Extreme Ultra Violet) has the potential if photo-resist limitation and increasing the intensity of laser are met. Immersion lithography involves replacing the air-filled gap between the lens and the wafer with liquid. However, there are some obstacles that must be surpassed in order for the process to be implemented. Such hurdles include the logistics of maintaining clean fluid on the wafer without bubbles or any other optical distortions and ensuring that the fluid does not cause the resist to adhere or degrade more than it should. These technological challenges need to be solved for the deep submicron technology. This project report discusses MOSFET, MOS Capacitor, Resistor, and PN junction Diode theory in section 3. Extracted data is analyzed and the behaviors of each of these devices are studied in section 4. The reasons for the strange behavior of these devices for some data sets are discussed in detail in section 5. Finally, conclusion and references are mentioned in section 6 and section 7.

3. THEORY
3.1 MOSFET (Metal Oxide Semiconductor Field Effect Transistor)

Figure 1: Metal Oxide Semiconductor Field Effect Transistor

The idea of MOSFET was patented well before the invention of bipolar transistors. It initially had issues with processing. However it has better performance compared to the bipolar junction transistor (BJT), the MOS transistor occupies a relatively smaller silicon area, and its fabrication involves fewer processing steps. The technological advantages, together with the relative simplicity of MOSFET operation, have helped make the MOS transistor the most widely used switching device in VLSI and ULSI. To understand the overall operation of MOS transistor, let us analyze the two terminal MOS transistor. The figure below shows the two terminal MOS structure. It consists of three layers: the metal gate electrode, the insulating oxide (SiO2) layer, and the p-type bulk semiconductor (Si), called substrate.

Figure 2: Two terminal MOS structure

The MOS structure forms a capacitor with metal plate on one side and semiconductor on the other, the oxide acts as dielectric. Under the thermal equilibrium condition, concentrations of mobile carriers in a semiconductor is given by

. =

Here, n and p denotes the mobile carrier concentrations of electrons and holes respectively, and n i denotes the intrinsic carrier concentration of silicon, which is a function of the temperature. To understand the electrical behavior of the MOS structure under externally applied bias voltages, assume that substrate voltage is set at = 0. The gate voltage is the controlling parameter. Let us assume to have a P-channel MOS n-type device. We obtain three different types of regions depending on the applied voltage to gate terminal. 1) When negative voltage is applied the gate gets negatively charged, the semiconductor which acts as other plate of capacitor gets positively charged. Holes present in the semiconductor which are majority charge carriers get attracted towards the junction of Si/SiO2. Hence carrier accumulation is observed figure below.

Figure 3: MOS transistor in accumulation region

2) When a small positive gate bias Vg, less than the threshold voltage is applied to the gate electrode, electric field in the oxide region will be directed towards the substrate. The majority carriers will be repelled back into the substrate as a result of the positive gate bias and like charges repelling, and these holes will leave negatively charged fixed acceptor ions behind. Thus, a depletion region is created near the surface.

Figure 4: MOS transistor in depletion region

3) If a positive voltage is increased further, above the threshold level positive gate potential attracts additional minority carriers (electrons) from the bulk substrate to the surface. The n-type region is created near the surface by the positive gate bias called the inversion layer. A sheet of electrons is formed in semiconductor side of Si/SiO2 junction.

Figure 5: MOS transistor in inversion region

STRUCTURE MOS TRANSISTOR (MOSFET) The basic structure of n-channel MOSFET is shown in figure. There are two types of MOSFET 1. Enhancement type MOSFET which will be turned ON i.e. the inversion layer formation controlled by gate voltage control and 2. Depletion type MOSFET which is independent of applied gate voltage

Figure 6: Structure of n-channel enhancement-type MOSFET

CURRENT EQUATIONS FOR LINEAR REGION,

FOR SATURATION REGION,

= [( ) ]

( )

Where, Ids : Drain to source current [A] : Average mobility of carriers in the channel [cm2/V.sec] Co : Capacitance per unit area of the MOS structure [F/cm2] W : MOSFET width (m) L : MOSFET Gate Length (m) Vgs : Gate to source voltage [V] Vds : Drain to source voltage [V] Vth : Threshold Voltage [V]

Figure 7: Regions of operation of NMOS transistor

Figure 8: V-I Characteristics of MOSFET

Some of the important parameters in MOSFETs are discussed below. They will be calculated in result section. Threshold Voltage ( ) It is the minimum value of Vgs required to invert the channel and inversion layer is formed near the surface. Channel Mobility at Saturation () It the maximum value of mobility of the electron in the saturation region of MOSFET. Saturation Velocity ( ) It is the maximum value of velocity with which electron can travel in the saturation region of MOSFET. Transconductance ( ) It is the rate of change of drain-source current to the rate of change of gatesource voltage at constant drain-source voltage. Output Conductance ( ) It is the rate of change of drain-source current to the rate of change of drainsource voltage at constant gate-source voltage. Voltage Swing Represents the Vgs corresponding to [( / ) - 10 %( / ) ]

3.2 MOS Capacitor Flat-Band Diagram in MOS Capacitor The term flat band refers to fact that the energy band diagram of the Metal-oxide-semiconductor is flat, under the unbiased condition, which implies that no charge exists in the semiconductor. The flat-band diagram of an aluminum-silicon dioxide-silicon (MOS) structure is shown. Theoretically we consider having a flat band but practically in unbiased condition it is not observed. In order to get a flat band we need to bias it externally. It is needed to neutralize oxide charge, fixed charges, interface charge and fixed ion charge. Note that a voltage must be applied to obtain this flat band diagram. Indicated on the figure is also the work function of the aluminum gate, the electron affinity of the oxide, and that of silicon, X, as well as the band gap energy of silicon, . The band gap energy of the oxide is 0.9 electron volt. The flat band voltage is obtained when the applied gate voltage equals the work function difference between the gate metal and the semiconductor.

Figure 9: Flat Band Energy Diagram of Al-SiO2-Si

The above conditions help us to obtain the C-V characteristics for the MOS Capacitors. The ideal characteristics are shown in figure 12.

Figure 10: C-V Characteristics of MOS Capacitor

Using the above shown Characteristics we can extract the thickness of the oxide using the following equation,

= =

Where, : Oxide (SiO2) relative permittivity = 3.9 : Permittivity of the free space = 8.85 1014 (F / cm) A : Area of the Capacitor (either square with the side of 400mm, or circle with the diameter of 400 mm) : Oxide Thickness (cm) We can calculate the doping of the substrate, , using the Fermi work function , and ,

=().()

P-type semiconductor N-type semiconductor . +

=().( )

The calculation of is an iterative process with an initial guess of and stops when and become equal. In order to calculate the net oxide charges, the flat band capacitance must be found first with the equation,

[( ) + ( . )] .

Where, Deby length, and oxide capacitance, , are given by

. . = ( ) .
=

The number of charges per unit area of the capacitor ( ) can be found by, = (. )

3.3 PN Diode A PN Diode is formed at the junction of P-type and N-type semiconductor, which is created by selectively doping part of substrate with group V and group III, by ion implantation, diffusion or epitaxial (growing a doped layer of crystal over the other doped layer) . If two separate pieces of material were used, this would introduce a grain boundary between the semiconductors that severely inhibits its utility by scattering the electrons and holes or in our case diffusion of dopants. In our case we have used diffusion technique. P-N Junction with no external bias In a "P-N" junction, in unbiased mode, an equilibrium condition is reached in which a potential difference is formed across the junction. This potential difference is called built-in potential . After diffusing p-type and n-type semiconductors, electrons near the interface diffuse into the p region. As electrons diffuse, they leave positively charged ions (donors) in the n region. Similarly, holes near the interface diffuse into the n-type region, leaving fixed ions (acceptors) with negative charge left behind. The regions nearby the pn interfaces lose their neutrality and become charged, forming the space charge region or depletion layer. The electric field created by the space charge region opposes the diffusion process for both electrons and holes. There are two concurrent phenomena: (i) (ii) The diffusion process that tends to generate more space charge, The counteracting electric field generated by the space charge that opposes diffusion.

The space charge region is a zone with a net charge provided by the fixed ions (donors or acceptors) that have been left uncovered by majority carrier diffusion. When equilibrium is reached, the charge density is approximated by the step function. In fact, the region is completely depleted of majority carriers leaving a charge density equal to the net doping level.

Figure 11: PN Diode without external bias

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P-N Junction with external forward bias In forward bias, the p-type is connected with the positive terminal and the n-type is connected with the negative terminal. With this connection, the holes in the P-type region and the electrons in the N-type region are pushed toward the junction due to the property of like charges repelling each other. This reduces the width of the depletion region. The positive charge applied to the P-type material repels the holes, while the negative charge applied to the N-type material repels the electrons. As a result, electrons and holes are pushed toward the junction, the distance between them decreases. This lowers the barrier potential. With increasing forward-bias voltage, the depletion zone eventually becomes thin enough that the zone's electric field cannot counteract charge carrier motion across the pn junction. The electrons that cross the pn junction into the P-type material or holes that cross into the N-type material will diffuse in the near-neutral region. Therefore, the amount of minority diffusion in the near-neutral zones determines the amount of current that may flow through the diode. P-N Junction with external reverse bias In reverse bias mode we connect positive terminal of source to the N-type of semiconductor and the negative terminal to the P-type semiconductor. As the p-type material is now connected to the negative terminal of the power supply, the 'holes' in the P-type material are pulled away from the junction, causing the width of the depletion zone to increase. Similarly, the N-type region is connected to the positive terminal; the electrons will also be pulled away from the junction. Therefore, the depletion region widens, and does so increasingly with increasing reverse-bias voltage. This increases the voltage barrier causing a high resistance to the flow of charge carriers, thus allowing minimal electric current to cross the pn junction. The increase in resistance of the pn junction results in the junction behaving as an insulator. The strength of the depletion zone electric field increases as the reverse-bias voltage increases. Once the electric field intensity increases beyond a critical level, the pn junction depletion zone breaks down and current begins to flow, due to Zener breakdown. If reverse biasing is further increased in magnitude, avalanche breakdown occurs and it completely destroys the diode, if the diode is not avalanche diode.

Figure 12: V-I Characteristics of PN Diode

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The built-in electric field causes a built-in potential barrier that opposes the flow of electrons and holes. The built-in potential is called and is given by:

( )

is the built in potential across the depletion region of a PN junction under equilibrium conditions, caused due to depletion region formation. V-I characteristic of an ideal diode in either forward, reverse bias or unbiased mode is given as,

= (( ) )
It is derived with the assumption that the only processes giving rise to current in the diode are drift (due to electrical field under biasing condition), diffusion, and thermal recombination-generation. It also assumes that the recombination- generation current in the depletion region is insignificant. This means that the Shockley equation doesn't account for the processes involved in reverse breakdown and photonassisted recombination- generation.

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3.4 RESISTOR The resistance R of a rectangular block of uniformly doped material is given by:

R= R = (.)
.

Since A=W t

= . ( )
Where, R : Resistivity of the material (ohm cm) L : Length of the block of material (cm) W : Width of the block of material (cm) A : Area of cross section of the block of material (cm2) t : Thickness of the block of material(cm) : Sheet Resistance of the block of material (ohm/square)

The most commonly used techniques in industrial environment to measure resistance are the Transmission Line Measurement and Transfer Line Method. We use Transfer Line Method in lab to characterize the resistor; and hence discussed in detail. A resistor is a two-terminal electronic component that produces a voltage drop across its terminals that is proportional to the electric current through it in accordance with ohms law i.e., V = IR.

Figure 13: I-V Characteristics of Linear Resistor

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TRANSFER LINE METHOD TLM is a technique used in semiconductor physics and engineering to determine the contact resistance between a metal and a semiconductor. The basic idea is the same as in transfer line measurement described above, but the test structure is somewhat different as shown below in the figure. The technique involves making a series of metal-semiconductor contacts separated by various distances. Probes are applied to pair of contacts, and the resistance between them is measured by applying a voltage across the contacts and measuring the resulting current. The current flows from the first probe, into the metal contact, across the metal semiconductor junction, through the sheet of semiconductor, across the metal semiconductor junction again, into the second contact, and from there in the second probe and into the external circuit to be measured by an ammeter. The resistance measured is a linear combination of the sheet resistance of the semiconductor in-between the contacts.

Figure 14: Transfer Line Measurement Test Structure

The total Resistance ( ) measured on the scope is sum of the Resistance due to the wire and probe tips (usually small and neglected) + Resistance due to the contact metal ( ) + Resistance due to the metalsemiconductor contact (Ohmic Contact : ) and the resistance of the doped layer ( ) = 2 + 2 + , << [ , ] and hence neglected, this results in:

RT = 2 +
Where,

= ( )
Using d1 & d2, and their corresponding measured total resistance of 1 and 2 , we obtain:

= 2 + ( ) = 2 + ( )
If we solve the above system for , we obtain:

( . . ) ( )

=A(

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Figure 15: Total resistance vs. length

This method is used to calculate the sheet resistance as well as contact resistance in the ensuing calculations. The slope obtained from the graph plotted between the total resistances vs. the distance between the pads gives the value . Also the y-intercept in the graph gives the value of . Figure above shows the top view of the transmission line realized by transfer line method. The parameters d1, d2, d3, d4, d5 and d6 are the distances between the pads and z is the width of the transmission line.

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RESULTS RESISTANCE The Resistance for the three IC resistors with lengths 400 m, 800 m and 5400 m and the transmission line are shown in the table below: LENGTH [m] 400 800 5400 RESISTANCE [] 475 870 5540

Table 1: Resistance of Three IC Resistors

The pads in the resistor account for 40 m in the total length of the resistors. So the length becomes 400 m, 840 m and 5440 m. The correction factor of the bends is 0.44 times the total number of bends. Sheet Resistance is given by,

()

( ) = ( ) + ( )

Sheet resistance with length 400 m (R400) R400 =

[ + ]

= 10.79 /square

Sheet resistance with length 800 m (R800) R400 =

[ + ]

= 10.35 /square

Sheet resistance with length 5400 m (R5400) R400 = Average Sheet Resistance (_) _ _ = =
[400 + 800 + 5400] 3 [
+ (.) ]

= 10.32 /square

(.+.+.)

= 10.48 /square

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TRANSMISSION LINE METHOD LENGTH 9-8 8-7 7-6 6-5 5-4 DISTANCE [m] (380um) (300um) 200um) (100um (60um) RESISTANCE [] 195 145 115 80 54

Table 2: Sheet Resistance Measurement using Transfer Line Measurement (TLM)

250

200

y = 0.4092x + 32.696

150 Series1 100

50

0 0 100 200 300 400

Figure 16: Resistance vs. Distance Equation of line is, y = 0.4092x + 32.696 From the graph, y-intercept,

= 32.696 = 16.34 Slope = 0.4092 = Slope W, W = 20m

= 0.4092 20 = 8.18 /square

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MOS CAPACITOR: EXTRACTION OF OXIDE THICKNESS (TOX) FROM C-V CHARACTERISTICS:

C-V CHARACTERISTICS
4E-10 3.5E-10 3E-10 2.5E-10

C (Farad)

2E-10 1.5E-10 1E-10 5E-11 0

-5

-4

-3

-2

-1 Voltage (V)

Figure 17: C-V Characteristics of Capacitor

From graph, 2 = = 376 pF = = 31.7 pF

= =
Where,

. .

Oxide (2 ) relative permittivity = 3.9 Permittivity of the free space = 8.85 1014 F/cm Area of the Capacitor (Circle with the diameter of 400m) Oxide Thickness (cm)

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Area of circle = 2 = 3.142 (200 )2 = 0.1256 106 2 = 0.1256 102 2 Therefore, =


[. . . ] [ ]

= 1.152 cm = 115.2

=
=

.
+

. (+.)

= 29.23 pF

EXTRACTION OF =

= [/] ( ) We will use iterative approach to find the value of (v) 0.349 0.329 0.327 0.327

NA (cm-3) 1016 4.56 1015 4.30 1015 4.28 1015

Nsub (cm-3) 4.56 1015 4.30 1015 4.28 1015 4.28 1015

Table 3: Iterative Approach for calculation of

= 4.28 1015 cm-3 = 0.327 V

Deby Length = (

. . / ) .

= {[11.7 x 8.85 x 10-14 x .0259] / [1.602 x 10-19x 4.28 x 1015]}1/2 Deby Length = 6.27 x cm

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Flat Band Capacitance

[( ) + ( . )] .

Where, = 376 pF, = /A = 133.67 pF The value is obtained from the graph as -0.95V. EXTRACTION OF QSS

= +
: :

Metal work function [for Al gate, = 4.10 V] Semiconductor work function

= +
: : = = = = Electron Affinity of Silicon = 4.05 V Bang gap of Si at T = 300 K = 1.12 V 4.05 + 0.56 + 0.327 = 4.937 V - 0.837V -0.95 V 0.42 x 1010 C

EXTRACTION OF

(. )

= (0.42 x 1010 ) / (1.602 x 1019 x 0.1256 x 102) = 2.08 x 2

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PN DIODE The characterization of the forward bias regions of the PN diode is performed. The PN diode was tested by setting one of the probe needles on the square pad of the diode and the other needle on the substrate. The voltage was applied in increasing steps of 0.015V, between 0V and 1.5V and the current was measured at each step. THE EXTRACTION OF (BUILT IN POTENTIAL) The formula for is,

= [exp (q /nKT) 1]

I - V CHARACTERISTICS OF PN DIODE
0.012 0.01 0.008

Id (Amps)

0.006 0.004 0.002 0 0 -0.002 0.2 0.4 0.6 0.8 Vf (V) 1 1.2 1.4 1.6

Figure 18: I-V Characteristics of PN DIODE

The built in voltage is calculated by drawing a tangent to the I-V characteristics of PN Diode. So we observed that,

= 0.56V
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EXTRACTION OF IDEALITY FACTOR (N): From the following equation we extract the formula for ideality factor,

ln( ) = ln( ) + (q/nKT)


The Ideality factor,

Ideality factor (n) = (1/slope) (q/KT)


And

q / KT = 38.6832 /V
Where, T= 300K (Room temperature) K = 8.617 105eV Plot vs. ln( ) and we get three distinct regions on the curve for which we find three distinct slopes and three different ideality factors.

0 -1 -2 -3 0 0.5 1 1.5 2

ln (Id) (Amps)

-4 -5 -6 -7 -8 -9 -10 Vf (V) region #3 region #2

region #1

Figure 19: PN DIODE Forward Voltage vs. ln( )

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From slopes, we can find the value of n1, n2 and n3. =

Equation of line in region 1 (1V- 1.5V) y = 1.8441x - 7.2986 Slope Region #1 = 1.8441 n1 = 38.6832/1.8441 n1 = 20.9767

Equation of line in region 2 (0.8V- 1V) y = 3.8738x - 9.3496 Slope Region #2 = 3.8738 n2 = 38.6832/3.8738 n2 = 9.9858

Equation of line in region 3 (0.6V -0.8V) y = 11.052x - 14.919 Slope Region #3 = 11.052 n3 = 38.6832/11.052 n3 = 3.5001

EXTRACTION OF LEAKAGE CURRENT ( ) From the equation of line in region3, we can find the Y-intercept that gives ln ( ) y = 11.052x - 14.919 Consider x =0, we get y intercept ln( ) = -14.919 = 3.31 Amp = 0.331 A

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MOSFET The MOSFET with the channel width of W=40um and the channel length L=16um is used for the Characterization. I - V CHARACTERISTICS OF MOSFET
1.60E-02 1.40E-02 1.20E-02 1.00E-02 vgs = 0V vgs = 1V vgs = 2V vgs = 3V vgs = 4V vgs = 5V vgs = 6V vgs = 7V vgs = 8V vgs = 9V vgs = 10V vgs = 11V 0.00E+00 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 vgs = 12V

Ids (Amps)

8.00E-03 6.00E-03 4.00E-03 2.00E-03

Vds (V)
Figure 20: I-V Characteristics of MOSFET

The following assumptions are made for the n-channel MOSFET.

The mobility of electrons is held constant in the channel. The electrical field along the channel is the dominant electric field and the component of electric field perpendicular to the channel inside the semiconductor is negligible. Long channels (L > 5 mm) The shape of the channel (same as MOS inversion layer) as a function of the drain source bias changes linearly (Gradual Channel Approximation-GCA).

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The characterization was done for thirteen levels of gate to source voltage while the drain to source voltage ( ) swings from 0V to 15V with a step of 0.5 V. (V) 0 1 2 3 4 5 6 7 8 9 10 11 12 = 8V (Amps) 0.018343 0.024869 0.033166 0.041689 0.049855 0.057807 0.065646 0.073632 0.081695 0.089183 0.09574 0.101454 0.106348 (Amps) 3.36E-04 6.18E-04 1.10E-03 1.74E-03 2.49E-03 3.34E-03 4.31E-03 5.42E-03 6.67E-03 7.95E-03 9.17E-03 1.03E-02 1.13E-02

Table 4: Value for plotting SQRT( ) vs. at = 8V

EXTRACTION OF THRESHOLD VOLTAGE


0.12 y = 0.0076x + 0.019 0.1

Idss (Amps)

0.08 0.06 0.04 0.02 0 0 5 10 15

Vgs (V)
Figure 21: Extraction of MOSFET Threshold Voltage

The Threshold voltage can be found out by extrapolating the slope line of the graph. The observed Threshold voltage is = -2.5V

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EXTRACTION OF AVERAGE CHANNEL MOBILITY AT SATURATION

= (
Where,


W L Slope

: Capacitance per unit area of the MOS structure [F/2 ] : 29.93 108 [F/cm2] (as calculated from measured above) : MOSFET Width [40 = m] : MOSFET Gate Length [16 = m] = 0.0076 (from graph)

After solving, = 154.38 /. at saturation

EXTRACTION OF SATURATION VELOCITY:

EXTRACTION OF SATURATION VELOCITY


1.20E-02 1.00E-02

Idss (Amps)

8.00E-03 6.00E-03 4.00E-03 2.00E-03 0.00E+00 0 5 10 15

Vgs (V)
Figure 22: Extraction of MOSFET Saturation Velocity

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EXTRACTION OF SATURATION VELOCITY


1.20E-02 1.00E-02 8.00E-03 y = 0.0012x - 0.0008

Idss (Amps)

6.00E-03 4.00E-03 2.00E-03 0.00E+00 -2.00E-03 0 5 10 15

Vgs (V)
Figure 23: Graph of vs.

The equation which incorporates the saturation velocity after modifying the square law model in saturation region is given as:

= ( ) ( )
Slope = ( ) = 0.001 (from graph) Therefore, = 0.0012 / [29.93 x 108 x 40 x 104] = 1.03 x cm/sec

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EXTRACTION OF AND CORRESPONDING Vgs1 0 1 2 3 4 5 6 7 8 9 10 11 Idss1 1.98E-04 4.80E-04 9.66E-04 1.59E-03 2.34E-03 3.20E-03 4.17E-03 5.23E-03 6.30E-03 7.30E-03 8.24E-03 9.13E-03 Vgs2 1 2 3 4 5 6 7 8 9 10 11 12 Idss2 5.17E-04 1.00E-03 1.63E-03 2.38E-03 3.24E-03 4.21E-03 5.31E-03 6.47E-03 7.56E-03 8.60E-03 9.56E-03 1.05E-02

gm (ms) 0.31901 0.52494 0.6684 0.789 0.899 1.0093 1.1425 1.2381 1.2605 1.2953 1.3127 1.3364
calculation

gm/W (ms/mm) 7.97525 13.1235 16.71 19.725 22.475 25.2325 28.5625 30.9525 31.5125 32.3825 32.8175 33.41

Table 5: vs. for

EXTRACTION OF gmmax and Vgs


40 35 30

gm/W (ms/mm)

25 20 15 10 5 0 0 2 4 6 Vgs (V) Figure 24: Extraction of MOSFET and corresponding 8 10 12

The maximum value of = 1.33 when = 11V

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Vgs 0 1 2 3 4 5 6 7 8 9 10 11 12

Ids1 4.03E-04 6.85E-04 1.17E-03 1.80E-03 2.55E-03 3.40E-03 4.37E-03 5.48E-03 6.74E-03 8.08E-03 9.38E-03 1.05E-02 1.17E-02

Vds1 8.5 8.5 8.5 8.5 8.5 8.5 8.5 8.5 8.5 8.5 8.5 8.5 8.5

Ids2 5.65E-04 8.47E-04 1.33E-03 1.96E-03 2.70E-03 3.55E-03 4.51E-03 5.62E-03 6.88E-03 8.25E-03 9.69E-03 1.10E-02 1.24E-02 Table 6: vs.

Vds2 9.5 9.5 9.5 9.5 9.5 9.5 9.5 9.5 9.5 9.5 9.5 9.5 9.5

gd (ms) 0.16248 0.16132 0.162 0.157 0.1531 0.15 0.1433 0.1409 0.1323 0.1674 0.3033 0.57 0.65

gd/W (ms/mm) 4.062 4.033 4.05 3.925 3.8275 3.75 3.5825 3.5225 3.3075 4.185 7.5825 14.25 16.25

EXTRACTION OF gdmax and Vgs


18 16 14

gd/W (ms/mm)

12 10 8 6 4 2 0 0 2 4 6 Vgs (V) Figure 25: Plot of vs. 8 10 12 14

From the graph, the /W max is 16.25 at = 12V Hence, = 0.65 mS 29

Vgs 0 1 2 3 4 5 6 7 8 9 10 11

gm/W 7.97525 13.1235 16.71 19.725 22.475 25.2325 28.5625 30.9525 31.5125 32.3825 32.8175 33.41

gd/W 4.062 4.033 4.05 3.925 3.8275 3.75 3.5825 3.5225 3.3075 4.185 7.5825 14.25

gm/gd 1.96338 3.254029 4.125926 5.025478 5.871979 6.728667 7.972784 8.787083 9.527589 7.737754 4.328058 2.344561

Table 7:

vs.

gm/gd Vs Vgs
12 10

gm/gd

8 6 4 2 0 0 2 4 6 8 10 12

Vgs (V)
Figure 26: Plot of

vs.

Voltage Swing = ( ) % ( ) = 9.52 8.56 = 0.95V


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Linear region Here we use a MOSFET whose length is 16um and width is 40um LINEAR REGION OF MOSFET OPERATION
2.00E-04 1.80E-04 1.60E-04 1.40E-04 Vgs = 0V Vgs = 1V Vgs = 2V Vgs = 3V Vgs = 4V Vgs = 5V Vgs = 6V Vgs = 7V Vgs = 8V Vgs = 9V Vgs = 10V Vgs = 11V Vgs = 12V

Ids (Amps)

1.20E-04 1.00E-04 8.00E-05 6.00E-05 4.00E-05 2.00E-05 0.00E+00

Vds (V)
Figure 27: I-V Characteristics of MOSFET in linear region

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Vgs 0 1 2 3 4 5 6 7 8 9 10 11 12

Ids1 8.94E-06 2.99E-05 4.60E-05 6.12E-05 8.02E-05 9.79E-05 1.13E-04 1.27E-04 1.39E-04 1.50E-04 1.60E-04 1.69E-04 1.78E-04

Vds1 0.095 0.095 0.095 0.095 0.095 0.095 0.095 0.095 0.095 0.095 0.095 0.095 0.095

Ids2 9.14E-06 3.11E-05 4.82E-05 6.49E-05 8.43E-05 1.03E-04 1.19E-04 1.33E-04 1.46E-04 1.58E-04 1.68E-04 1.78E-04 1.87E-04

Vds2 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1

gc 3.92E-05 0.000241 0.000435 0.000725 0.000821 0.001 0.00117 0.00128 0.00149 0.00152 0.00159 0.00172 0.0019

Table 8: Calculation of gc

EXTRACTION OF MOBILITY IN LINEAR REGION WITH Vth CALCULATION


0.0025 0.002 y = 0.0001x + 0.0002 Series1 0.001 0.0005 0 0 5 Vgs (V) Figure 28: Extraction of Mobility and Vth in Linear Region 10 15 Linear (Series1)

gc (A/V)

0.0015

Slope = 0.0001 Calculation of threshold voltage (by extrapolation) Vth = -2V (linear) = (Slope * L) / (Cox * W) (linear) = 133.64 / V.sec

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5. DISCUSSION RESISTOR A number of sets of three different lengths of resistances were fabricated on the 3 inch wafer. The physical lengths were 400 m, 800 m and 5400 m. The resistances of these three resistances were measured to determine the sheet resistance. Also, TLM structure is used to measure sheet resistance. , calculated from Transmission Line Method = 14.31 ohms/square , calculated from Transfer Line Method = 8.18 ohms/square Calculated from TLM is more accurate, as this method does not require the cross sectional area of the resistor and the cross sectional area varies in our devices. PN DIODE The PN diode is a unidirectional device and blocks the current flow in reverse direction. However, a small current due to minority carriers called leakage current I0 flows through it. It was observed that in one of the diode characteristics, current starts flowing even before the threshold voltage are reached. This may be due to non-uniform doping of P/N on substrate. Practically, leakage current should be as small as possible and usually observed in nano-Amp. The leakage current and threshold voltage in our case are 0.331 A and 0.56 V respectively. Even though threshold value is different than the usually observed value of 0.7 V, threshold voltage can be varied as per the requirement. The ideality factor of a diode is a measure of how closely the diode follows the ideal diode equation. The ideality factor comes from the differential of a signal so it is very prone to noise. Temperature variation should also be taken into consideration during measurement. To reduce noise the slope is usually taken as a fit over several points. The ideal diode equation assumes that all the recombination occurs via band to band or recombination via traps in the bulk area of the device (i.e. not in the junction). However, recombination occurs in other ways and other areas of the device. Thus ideality factor deviates from the unity. These ideality factors vary with a little difference between them. Irrespective of all the precautions, some defects are always introduced due to equipment (no chlorinated oxidation, not so cleaned furnace, etc.), non-uniform doping of active regions, dust particles, not as clean process as to the industry standard etc. Due to this, ideality factor calculated comes in three different values n3 =3.5001, n2 = 9.9858, n1 = 20.9767 CAPACITOR Two types of MOS capacitor were fabricated: square and circular. Characterization was done on circular MOS capacitor and data was extracted for the same. This extracted data helps us to get the oxide thickness. O xide thickness (tox) calculated is 115.2 . Iterative process yields to get the impurity concentration. Nsub = 4.28 3. It was observed that the plotted C-V curve is shifted from the regular curve because of trapped ionic charges in the oxide region. The value of these charges calculated Qss = 3.38 x C. Trapped ionic charges play major role in threshold voltage shift of MOSFET. These charges get trapped after the gate oxide is formed. Hence, usually gates oxide and the material to be deposited chamber are put side by side so there wont be any trapped charges in gate oxide. The total number of trapped charges Nf = 3.04 x 2

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MOSFET MOSFET is an active device and also called as voltage controlled device. During the fabrication of MOSFET, controlling the terminal voltage i.e. gate voltage is one of the important criteria needs to be taken into consideration. In the current processes a very thin layer of oxide is grown with advanced techniques. Even though such a thin layer of oxide cannot be grown in this laboratory; we grow the oxide which is thick. But the important thing it helps to understand the overall physics behind it. As number of charges increase in gate oxide, it changes the threshold voltage. Although channel is not required at zero bias, these trap charges forces electron to form channel. This is the motivation for MOSFET built in this laboratory. Trapped charges are categorized as Interface trapped charges; Oxide trapped charges, fixed oxide charges, and Mobile ionic charges. Major shift in threshold voltage is due to Mobile ionic charges. Usually, in all the digital processing applications, MOSFETs are operated at maximum frequency where electron velocity is saturated. When device enters into saturation, it is the temperature which guides electrons fast motion for some time. But as the temperature increases, collision between the neighboring atoms start increasing, which reduces the further motion of electrons. However, after that it is the threshold voltage which is responsible for fast movement of electrons. At a point, electrons motion gets saturated and this is electron saturation velocity. Hence, mobility of the electrons in the linear region should be less than that mobility in saturation region. However, calculated mobility is the linear region is less than mobility is saturation region; but difference is very small. The calculated values are shown in the table below. The values observed are as per the process parameters and satisfies the requirement.

Vth (n)sat Vs (gm)max Voltage swing (n)linear

-2.41 V 154.38 cm2/(V.sec) 1.03 106 cm/sec 1.33 mS at Vgs = 11V 0.95V 133.64 cm2/(V.s)

Table 9: MOSFET Parameters for W=40 m and L = 16 m

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6. CONCLUSION Prof. Dr. Kian Kaviani has given an enriching experience and its a privilege to learn this course under him. I have registered for this course as a once in a lifetime opportunity to have firsthand fabrication lab experience. The learning experience was very good. Processing techniques, limitations and the solutions to surmount the problems were discussed which gave a gist of processing industry of last three decades. As an Electrical Engineering Graduate, specializing in VLSI, this course has given me a good understanding of the theory that I study in my other design courses. Much of the concepts of processing were cleared which gives better and logical understanding about variations in theoretically expected and practically obtained data. The clean-room learning experience was the best, and the best TA at USC Mr. Moh Amer, who gave us a good learning experience.

7. REFERENCES

Book CMOS Digital Integrated Circuits, Analysis and Design by Kang and Leblebici www.wikipedia.org Dr. Kian Kaviani EE504, Fall 2013,USC, class notes K. Monahan, Yield Challenges at the 90nm Technology Node and Beyond, The Electrochemical Society International Semiconductor Technology Conference, Shanghai, Keynote session (2004) J. J. Lin, 300 mm Manufacturing, IEDM Short Course The Future of Semiconductor Manufacturing (2002)

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