IEC LAB ASSIGNMENT II

Question 1 Design a Inverter

a) Plot switching threshold Vs (W/L)pmos : (W/L)nmos.
VTC of INVERTER for different value of (W/L)pmos: (W/L)nmos

Plot of Switching Threshold Vs (W/L)pmos : (W/L)nmos.

0.00625 0.0062 0.00615 Switching threshold Vm(volt) 0.0061 0.00605 0.006 0.00595 0.0059 700 800 900 1000 1100 1200 (W/L)pmos/(W/L)nmos

b) What should be the value of switching threshold? Why? Choose this value for W/L s for all further simulations.
Switching threshold voltage generally choose around middle of the available voltage swing because this give the comparable value of low and high noise margins, symmetrical voltage transfer characteristics and equal high to low and low to high propagation delays. For Switching Threshold (VM) = 0.6V, W/LPMOS=789/120 W/LNMOS=160/120

c) Make a symbol for Inverter

c) Make a test bench schematic for following calculations. Attach a snapshot of this schematic.

d) Calculate tpHL and tpLH for inverter for PVT variations. Process (ss,tt,ff) ,Temp(-40, 27, 85).
Process ss Temperature(Celsius) -40 27 85 Process tt Temperature(Celsius) -40 27 85 Process ff Temperature(Celsius) -40 27 85 TPHL(picoseconds) 20 20 30 TPLH(picoseconds) 20 20 20 Td(picoseconds) 20 20 25 TPHL(Picoseconds) 30 30 30 TPLH(Picoseconds) 30 30 30 Td(Picoseconds) 30 30 30 TPHL(Picoseconds) 40 50 50 TPLH(Picoseconds) 40 40 40 Td(Picoseconds) 40 45 45

Question2: Design a master slave positive edge triggered register using multiplexer
a) Use the inverter designed in part 1also use transmission gates with minimum size transistors to design the circuit.

b) Tabulate setup time, hold time and propagation delay.

Theoretical Value Simulated Value

Setup time (picoseconds) 100 116

Hold time (picoseconds) 0 0

Propagation delay (picoseconds) 40 60

c) Plot the limiting case for setup time violation as shown in fig. 7-11. Mark all the important information on the plot.
Plot for Tsetup = 116ps

From the plot it is clear that output (red colour) follow the input (green colour) at the rising edge of the clock (black colour). Plot for Tsetup=115ps

From the time delay between input and clock is less than the setup time. So the output (red colour) does not follow the input (green colour) at the rising edge of the clock (black colour).

d) Calculate the maximum frequency of operation theoretically and compare it with the simulated values.
Maximum frequency of operation (Theoretically) = 7.14GHz Maximum frequency of operation (Simulated) = 5.68GHz

Question3: Design a circuit for generating non-overlapping clock

a) Calculate delay for all elements for typical corner .

Delay of inverter = 30ps Delay of NOR gate = 30ps

b) Show theoretical calculations for tnon-overlap.

Tnon-overlap (theoretical) = 30ps. Tnon-overlap (simulated) = 30ps.

b) Show transient simulation result and compare with theoretical calculations.