UNIT V Microcontroller I

Consider 8051 family microcontroller in the following questions 1. (a) A, B and PSW (b) A is accumulator, only B and PSW (c) PSW is not among ones, which (d) None of the A, B and PSW are the special functions registers 2. Number of ports used in an expanded mode are: (a) two (b) three (c) four in case of additional devices present in a family member (d) depends according to the use of external program memory or on use of external as well as data memory 3. RS0 and RS1: (a) are not in the PSW as these are not the flags (b) are in the register sets (banks) (c) are the bits-4 and 5, respectively, for selecting the register bank in the PSW (d) are the bits-3 and 4, respectively, for selecting the register bank in the PSW. Note: Bit 7 is C (carry or borrow) flag

4. (a) We can use a common memory chip for the program and data, if we join the and pins (b) If we join the and pins, the 8051 will not save the program at external memory (c) If we connect pin to Vcc then we cannot use the external program memory (d) The 8-bit address of a byte as 0x00 refer to internal RAM if = 1 and external RAM if =0 5. Reset pin is: (a) active when connected to 1 (b) active for a few cycles only (c) active when connected to 0 (d) active only on watchdog timer reset

6. (a) Port P0 can be used as an output only because it is used as AD0-AD7 in the expanded mode: (b) All port bits can be used as input or output in single-chip mode (c) A port bit can be used as an input after writing 0 at it (d) Two ports P0 and P2 are the output ports and P1 and P3 are the input ports: 7. Bit address 0x00 and byte address 0x00 are for the: (a) Bit 0 at 0x20 and the byte at 0x00 in the internal RAM (b) Bit 0 at 0x00 and the byte at 0x00 in the internal RAM (c) Bit = 0 in a SFR and the byte = 0x00 (d) Bit 0 at 0x20 and byte at 0x00, respectively 8. TH1, TL1, TH0 and TL0 SFRs are at the addresses: (a) 0x8D, 0x8C, 0x8B and 0x8A (b) 0xAD, 0xAB, 0xAC and 0xAA (c) 0x8D, 0x8B, 0x8C and 0x8A (d) not between 0x80 and 0xFF as these are not the SFRs 9. Mode bits M1 and M0 can: (a) be set as 11 at TMOD.5 and TMOD.4 and get assigned to TH0 as an 8-bit timer (b) be set as 00 only (c) can be set as 00 and 10 only (d) not be set as 11 at TMOD.5 and TMOD.4 because timer 1 does not function in mode 3 10. Timer 1 runs and timer 0 stops: (a) when TCON.6 = 1 and TCON.4 = 0 (b) when TCON.4 = 0 and TCON.5 = 1 (c) when TCON.7 = 1 and TCON.5 = 0 (d) when TCON all bits are 1s 11. (a) Synchronous mode of operation of serial interface can either be to transmit or receive at a given instant (b) asynchronous mode of operation of serial interface can only either be transmit or receive at a given instant (c) synchronous and asynchronous mode of operation of serial interface can be transmit and receive at a given instant

(d) only asynchronous 10T period and 11T periods exist in the serial interface using TB8 and RB8, bits 12. When SM2 is set to: (a) 1, it facilitates the multiprocessor communication in case of mode 1 and 3 (variable baud rate serial UART mode) (b) 1, it facilitates sending the address for the multiprocessor communication in case of mode 2 and 3 (total 11 bit serial UART mode) (c) 0, it facilitates the multiprocessor communication in case of mode 2 and 3 (total 11 bit serial UART mode) (d) 0, it facilitates the multiprocessor communication in case of mode 0 only (synchronous communication mode) 13. If a period is 0.33 ms between the serial bits, we can transfer in one second when SCON sets for mode 2: (a) 300 characters (b) 275 only (c) 30 characters (d) 272 characters 14. At the RS232C because of the need to provide a margin for the attenuation and noise pickups: (a) 0 means + 3V down to + 25V (b) 0 means + 5V down to + 25V (c) 1 means + 3V down to + 25V (d) 1 means + 5 V down to + 12V 15. IP.4 is set to 1 in the interrupt priority register: (a) synchronous serial communication mode priority becomes highest (b) timer T1 priority becomes highest (c) interface serial communication mode priority becomes highest (d) synchronous serial communication mode priority becomes lowest 16. If IP register has been set as 0x00 then: (a) INT1 has the highest priority (b) INT0 has the highest and serial interface as the lowest priority (c) timer overflows have the highest priorities (d) there is no priority, interrupt processes in the order of its occurrence

17.In the MCU 8051 family, which one of the following options is true? (a) An opcode is of 1 byte length in each instruction (b) An opcode has variable number of bits in an instruction (c) An opcode must have the operands also specified in each instruction (d) Opcode bits cannot coexist with the bits for the program counter 18.(a) Routine cannot be used as an independent program (b) Routine can be used as an independent program (c) Routine can be used as an independent program but it affects the stack pointer by decrementing by 2 (d) Routine and interrupt service routine are the programs handled identically by the CPU 19. There are distinct MOV instructions to transfer into an SFR. (a) Three (b) Four (c) Five (d) Six 20.MOVC instructions uses as a pointer for transferring a byte of the code or constant into the accumulator. (a) PC (b) Ri, DPTR, A + DPTR, A +PC, Ri (c) Ri + PC, DPTR, A +PC (d) No DPTR 21.SFR at address 83H has 20H and at 82H has FEH. INC DPTR (a) Will not affect the SFRs (b) Will effect the DPH of DPTR (c) Will effect DPL of DPTR (d) Will affect both DPH and DPL 22.All logic operations on a byte (a) Place the result into A or direct and takes the same time (b) Place the result into A or direct and takes the same time except for the operations on immediate data (c) Place the result into A and takes the same time except for the direct and dataoperations

(d) Place the result into A or direct and takes the same time except for the direct and data operations 23.If A = 05H and B = 64H, then after MUL AB the SFRs at F0H and E0H (a) Do not change (b) Equal 01 H and F4H (c) Equal F4H and 01H (d) None of these equal F4H 24.OV flag affects in (a) Multiply and divide (b) Addition, subtract, multiply and divide (c) Addition and subtraction (d) Addition, subtraction and multiply operations 25.AC flag affects in (a) Addition, subtraction, multiply and divide (b) Multiply and divide (c) Addition and subtraction (d) Addition, subtraction and multiply operations 26.A bit address using an instruction can change a bit at (a) Bit addressable valid SFRs or select internal RAM area (b) Bit addressable valid SFRs only (c) Carry and bit addressable valid SFRs and select internal RAM area (d) Carry and bit addressable valid SFRs only 27.The carry flag affects in (a) Add, subtract, multiply and divide (b) Add, subtract, increment and decrement (c) Add, subtract, RRC, RLC and Boolean processing instructions (d) Add, subtract, RRC, RLC, CJNE and Boolean processing instructions 28.NOP instruction (a) Is a jump to the next instruction within just one cycle (b) Does no operation and does not change the program counter

(c) Stops the clock of the CPU and does not do any operations (d) Increments the PC by 1, stops the clock of the CPU and does not do any operation 29.If C = 1 and bit at P2.1 = 0, the ANL C, A0H execution is such that (a) C can be either 1 or 0 (b) C = 0 (c) P2.1 = 1 (d) C and P2.1 are both 1 30.There is DJNZ 18H, 0FDH instruction at the address 1000H. After the execution of this instruction, the new instruction address is (a) 1000H if the accumulator is 00H after decrementing (b) 1002H if R0 is 00H after decrementing (c) 1003H if the accumulator is 00H after decrementing (d) 1002H if R0 is not 00H after decrementing 31.Consider following instructions: MOV D0H, #00H MOV R7, #20H SUBB R7, #02H MOV F0H, R7 MOV A, #21H MUL AB MOV R6, 0F0H CJNE R6, #31H, 0F0H Assume the starting address of the codes is 1000H. The last CJNE instruction address is (a) 100DH (b) 100EH (c) 100FH (d) 1010H 32.In the above instructions, if R6 equals 31H and R6 is not equal, then the next instruction addresses will be (a) 1011H and 1007H (b) 1011H and 1201H

(c) 100EH and 1001H (d) 100EH and 10FEH, respectively 33.A programmer should, wherever possible for temporary data or pointer address storage (a) Use registers (b) Use registers and internal memory (c) Use registers and also use the stack if the register space is insufficient (d) Use the stack 34.Registers are used in the instructions (a) For the temporary variables (b) For the temporary variables or pointers (c) As an internal RAM as well as SFRs (d) For the temporary variables or pointers or specific purposes like an accumulator

UNIT VI Microcontroller II

1. Interrupt service routine and called routine have the following features: (a) Both save the PC at the stack and have an identical instruction for return (b) Both save the PC at the stack but have different instructions for the return (c) Both save the PC as well as the registers in all MCUs (d) The routine is called using the instruction by LCALL, ACALL or CJNE. This is save the PC onto the stack 2. Nested interrupts (another ISR starts execution within an ISR) for the maskable sources are permissible in (a) 8051 and 80x86 (b) 68HC11/12 (c) 8051, 80x86 and 68HC11/12 (d) 8051 and 68HC11/12 3. Which of the following statement is correct? (a) Flag sets on interrupt occurrence and does not reset automatically on ISR start for all the sources (b) Flag sets on interrupt occurrence and resets automatically on ISR start for all the cases (c) Flag sets on interrupt occurrence and resets automatically on ISR start in specific cases, for example, for the case when the vector address is for one interrupt source like INT0 or INT1 or TF0 (d) Flag resets on interrupt occurrence and sets automatically on ISR start for the case when the vector address is for one interrupt source 4. 8051 (a) IT0 is in TCON SFR and defines the interrupt type (edge-triggered or level-activated interrupt) (b) IT0 is in IE SFR and defines the interrupt type (edge-triggered or level-activated interrupt) (c) IT0 is in TCON SFR and defines the flag, which sets on interrupt (d) IT0 is in IE SFR and defines the flag, which sets on interrupt 5. Vector addresses for the multiple sources of interrupts exist in priority order, higher priority vector at the lower address and lowest priority vector at the higher address (a) True for 80x86 only and the reverse is true for 68HC11/12 (b) True for processors 80x86 and 8051 and the reverse is true for 68HC11/12 (c) True for 8051 and the reverse is true for 68HC11/12

(d) The reverse is true for all processors 6. An 8051 vector address to which CPU vectors for servicing (a) is not the ISR start address (b) is the address of the interrupt level (c) is the address of the pointer for the ISR interrupt (d) is the start address of the ISR 7. Which of the following statement is correct? (a) 8051 primary-level interrupt enable-all bit EA enables the interrupts from all the maskable sources (b) EA enables the interrupt from the sources, which are masked by the secondary-level bits and which have a high assigned priority in the IP register (c) EA enables the interrupt from the sources, all maskable and unmaskable sources (d) EA enables the interrupt from the sources, which are also not masked by the secondarylevel bits 8. Vectored priority interrupt in 8051 for which the ISR is to be executed takes place (a) At the end of each ISR instruction (b) At the end of each ISR instruction as well as at the end of the return instruction (c) At the end of the ISR return instruction only (d) At all instances 9. For example, there are three interrupts, 1, 2 and 3 in priority order; highest priority assignment is for 1 and lowest to interrupt 3 and assume that each has an equal execution time of 1 ms in 8051. Let interrupt 1 be under service and let its execution time be 100 s still left for return at an instant t. Interrupt 2 is pending at t since 200 s. Now, an interrupt 3 occurs after 50 s. Interrupt 2 and interrupt 3 latency intervals will be (a) 0.3 s and 1.05 s, respectively (b) 1,300 s each (c) 200 s and 1,200 s, respectively (d) 1.3 s and 0.3 s, respectively 10. Consider an ISR 0023 CLR TI 0025 MOV SBUF, @ R0 0027 RETI Bytes transmitted by successive run of the ISR are as follows:

(a) Bytes transmitted = 2 if R0 initial value at the first interrupt = 2 (b) As per bytes put in R0 in the bank defined by RS1-RS0 before the first interrupt (c) As per address pointed by R0 (d) As per SBUF