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An FPGA Implementation of Array LDPC Decoder

Lo Den!ity Parity C"ec# $LDPC% code i! an error correctin& code' FPGA implementation for array (a!ed LDPC code! "elp! ac"ie)e a trade*off (et een "ard are comple+ity and decodin& !peed'

,)er -./ memory can (e red0ced and 11-1(p! t"ro0&"p0t can (e ac"ie)ed' Calc0lation! are independent (et een )aria(le node! or c"ec# node! at eac" iteration'

LDPC code! are !0ita(le for parallel implementation' Lo lo&ic con!0mption'


It ta#e! 6- cloc# cycle! to fini!" per iteration' In t"e fir!t cloc# cycle7 t"e mo!t left 6- col0mn! are proce!!ed (y 6- VPU!' T"i! i! repeated for t"e ne+t 6- col0mn! and !o on'

In e)ery cloc# cycle7 eac" VPU &et! 6 c"ec#*to* )aria(le me!!a&e! and comp0te t"e 6 )aria(le*to*c"ec# me!!a&e7 !o t"at 188 CPU! &et one inp0t eac"'

T"en7 eac" CPU deal! re!0lt! in memory'

it" one !tep of t"e c"ec# node proce!! and !tore t"e

T"e "ole c"ec# node proce!! i! di)ided into 6- !tep!'


1e!!a&e memory can (e red0ced 0p to -./' Ro0tin& pro(lem! in "i&" parallel le)el decoder de!i&n can (e totally re!ol)ed' T"e propo!ed arc"itect0re di)ide! t"e c"ec# node operation into 6- !tep!' Eac" !tep contain! only one le)el comparator' ;ence7 t"e cloc# !peed can (e !i&nificantly increa!ed'

Can (e 0!ed in application!

"ic" need! "i&" rate LDPC code! in area<!peed

!en!iti)e comm0nication !y!tem!'

V;DL De!i&n and FPGA Implementation of a f0lly parallel =C; SIS, Decoder

A de!i&n and $FPGA% implementation of arc"itect0re of a f0lly parallel SIS, decoder for t0r(o decodin& of t"e prod0ct code! rate application! i! propo!ed' it" lo comple+ity for "i&" data

In t"i!7 >oint e+ploitation of paralleli!m !ym(ol and paralleli!m of !0( (loc#! are done to to ac"ie)e "i&" data rate'

C"a!e*Pyndia" al&orit"m i! 0!ed in t"e propo!ed !y!tem' T"e decoder can reac" !ome data rate !0perior to t"e G(it<! comple+ity (y limitin& t"e de&radation' it" a rea!ona(le


T"e !0(*(loc# of t"e recei)in& part !im0ltaneo0!ly'

or#! in parallel on t"e inp0t !ym(ol!

T"e!e operation! are t"e comp0tation of t"e !yndrome and t"e !ortin& to &et t"e lea!t relia(le component!'

All data on t"e fir!t ri!in& ed&e of t"e cloc# i! o(tained' ,ne period allo ! to proce!! all te!t )ector!@ calc0latin& !yndrome7 decodin& and comp0tin& metric for eac" "ard deci!ion related to te!t )ector'

T"e c"o!en arc"itect0re reA0ire! only 2*cloc#*cycle latency'

V;DL De!i&n and FPGA Implementation 3ei&"ted 1a>ority Lo&ic Decoder!


V;DL de!i&n and FPGA $Field Pro&ramma(le Gate Array!% implementation of t o parallel arc"itect0re! for ma>ority lo&ic decoder i! propo!ed'

T"e arc"itect0re! are "ard deci!ion arc"itect0re and t"e SI;, t"re!"old decodin&' Aim i! to o(tain lo comple+ity for "i&" data rate application!' T"e code 0!ed i! t"e Difference Set Cyclic code' In electronic de!i&n7 t"e comple+ity of t"e circ0it i! a critical parameter and operatin& !peed m0!t (e ma+imiCed paralleli!m of calc0lation!' it" limitation of comple+ity ind0ced (y t"e


T"e arc"itect0re of t"e t"re!"old decodin& "a! t"ree f0ndamental 0nit!' T"e !"ift re&i!ter contain! t"e A0antified !ym(ol! recei)ed in parallel7 t"e loadin& of t"e re&i!ter i! controlled (y inp0t on t"e fir!t ri!in& front of t"e cloc#'

In t"e implementation of t"e add*min operator and t"e adder7 t"e n0m(er of inp0t port! m0!t (e confi&0ra(le a! ell a! t"e n0m(er of (it! per port to a)oid poor performance of t"e correction error!'

T"e re!0lt! of t"e add*min operation7 t"e addition and t"e deci!ion are a)aila(le at t"e o0tp0t at eac" ri!in& ed&e of t"e cloc#'


T"e approac" of t"e V;DL de!i&n and FPGA implementation of t"e decoder propo!ed allo to ac"ie)e )ery "i&" data rate it" red0cin& comple+ity'

A com(inatorial arc"itect0re adopted'

or#in& in pipelined and paralleliCed mode "a! (een

T"e "ard deci!ion decoder re!pond! on t"e fir!t ri!in& ed&e of t"e cloc# t"e code ord i! decoded it" a comple+ity of 2?D Le!'

it" a

comple+ity of 1-9 LE!7 for t"re!"old decodin& reA0irin& 22 cloc# cycle! !o a! t"at

T"e decoder can (e 0!ed on a t0r(o proce!! in order to ac"ie)e a "i&" data rate t0r(o decoder it" a rea!ona(le comple+ity'

De!i&n and FPGA Implementation of Stoc"a!tic T0r(o Decoder


Stoc"a!tic decodin& i! an alternati)e tec"niA0e for decodin& of error*correctin& code!'

T"e ! itc"in& acti)ity !en!iti)ity i! circ0m)ented and t"e latc"in& pro(lem i! red0ced (y tran!formin& t"e !toc"a!tic addition! into !toc"a!tic m0ltiplication! in t"e e+ponential domain and 0!in& m0ltiple !tream! it" determini!tic !"0ffler!'

T"e pro(a(ilitie! are con)erted into !tream! of !toc"a!tic (it! 0!in& =erno0lli !eA0ence! in "ic" t"e information i! &i)en (y t"e !tati!tic! of t"e (it !tream!'


T"e t o main feat0re! of t"i! approac" for iterati)e decodin& are )ery !imple "ard are !tr0ct0re! of comp0tin& node! and "i&"*t"ro0&"p0t decodin&'

T0r(o code! are a family of FEC! t"at are e!pecially attracti)e for mo(ile comm0nication !y!tem!' E+ploitation of t"e ma+im0m fea!i(le amo0nt of paralleli!m in t0r(o decoder! i! preferred for t"e !a#e of "i&"er t"ro0&"p0t'

,ne ma>or pro(lem in !toc"a!tic decodin&

"ic" deeply de&rade! t"e performance

i! related to t"e !en!iti)ity to t"e le)el of random ! itc"in& acti)ity'

T"e propo!ed arc"itect0re7 0!e! m0ltiple !tream! in parallel'



For con)ol0tional t0r(o code!7 t"e decodin& i! performed 0!in& t"e =CER al&orit"m7 al!o #no n a! t"e 1AP al&orit"m'

T"e !toc"a!tic decodin& of t0r(o code! reA0ire! t"e !toc"a!tic comp0tation to (e applied to a tail*(itin& A Po!teriori Pro(a(ility $APP% al&orit"m7 trelli! repre!entation' "ic" relie! on t"e

T"ere are a! many !ection! a! !ym(ol! to decode and eac" !ection i! made 0p of fi)e mod0le!'

Eac" !toc"a!tic decodin& !tep i! referred to a! a decodin& cycle $DC% and corre!pond! to t"e o0tp0t of one ne (it for eac" !toc"a!tic 0nit' T"e decodin& proce!! terminate! "en a ma+im0m n0m(er of DC! i! reac"ed'



To !ol)e t"e latc"in& pro(lem7 and to impro)e t"e =ER performance of !toc"a!tic decodin&7 proced0re! are 0!ed7 !0c" a! 0!in& !0pernode!7 !calin& t"e recei)ed Lo&*Li#eli"ood Ratio! $LLR!% 0p to a ma+im0m )al0e7 Ed&e 1emorie! $E1!% in!ertion and 5oi!e* Dependent Scalin& $5DS%'

T"e!e !ol0tion! aim at re*randomiCin& and decorrelatin& !toc"a!tic !tream!' An E1 i! a comple+ 0nit (a!ed on a re&i!ter in read' "ic" only )al0a(le (it! referred to ritten and randomly

a! re&enerati)e (it!7 i'e' a)oidin& !i&nal! !t0c# at F.F or F1F7 are


S0c" a 0nit i! efficient to !ol)e t"e latc"in& pro(lem "en t"e re&i!ter dept" i! !0fficient $typically (et een 92 and B6% and "en it i! d0plicated for any )erte+ of t"e decodin& &rap" An E1 pic#! 0p a re&enerati)e (it from a pool "en correlation occ0r!' An E1 pic#! 0p a re&enerati)e (it from a pool "en correlation occ0r!' To red0ce t"e correlation (et een t"e conc0rrent !tream!7 more t"an t o are reA0ired' In a m0ltiple !tream arc"itect0re7 all t"e !tream! and t"e lo&ic &ate! are d0plicated p time! $pG2% and t"e random (it !election i! done (y a !imple !"0ffler' T"e e+ponential !toc"a!tic approac" ena(le! t"e n0m(er of DC! to (e red0ced from 2?.4 to 924' T"e 92*!tream! !toc"a!tic decoder it" !"0ffler! reA0ire! only 14 DC!'



T"e n0m(er of decodin& cycle! i! con!idera(ly red0ced

it" no performance

de&radation (y tran!formin& t"e !toc"a!tic addition! into !toc"a!tic m0ltiplication! in t"e e+ponential domain and 0!in& m0ltiple !tream! it" determini!tic !"0ffler!'

An FPGA*(a!ed arc"itect0re for a f0lly*parallel 8*!tream! !toc"a!tic decoder of a $n H 6.7 R H 1<9% t0r(o code i! propo!ed'

T"e propo!ed arc"itect0re ma#e! f0lly*parallel t0r(o decodin& )ia(le on FPGA de)ice!'


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