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ky converter and its derivatives

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ky converter and its derivatives

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2699

Letters

A KY Boost Converter

K. I. Hwu, Member, IEEE, and Y. T. Yau, Student Member, IEEE

AbstractIn this letter, a KY boost converter is presented, which is the KY converter combined with the traditional synchronously rectied (SR) boost converter. Such a converter has continuous input and output inductor currents, different from the traditional SR boost converter, and has a larger voltage conversion ratio than the traditional SR boost converter does, and hence, this converter is very suitable for low-ripple applications. A detailed description of the proposed converter is presented herein along with a mathematical deduction and some experimental results. Index TermsInput inductor current, KY boost converter, KY converter, output inductor current, voltage-conversion ratio.

I. INTRODUCTION

Fig. 1.

OR THE application of the power supply using the lowvoltage battery, analog circuits, such as RF amplier, audio amplier, etc., often need high voltage to obtain enough output power and voltage amplitude. This is done by boosting the low voltage to the high voltage required. Therefore, for many of computer, communication, and consumer electronic products to be considered, there are some converters needed to supply one boosted voltage or more under a given low voltage, especially for portable communications systems, such as MPEG-3 (MP3) players, Bluetooth devices, personal digital assistant, etc. For such applications, the output voltage ripple must be taken into account seriously. Regarding the traditional nonisolated voltage-boosting converter, such as the boost converter and the buckboost converter, their output currents are pulsating, thereby, causing the corresponding output voltage ripples to tend to be large. As generally acknowledged, to overcome this problem, one way is to use the capacitor with large capacitance and low equivalent series resistance (ESR), another way is to add an LC lter, and the other way is to increase the switching frequency. Recently, some voltage-boosting converter topologies [1][4] with low output voltage ripples have been investigated. In [1], the coupling inductor is used in the boost/buckboost converter. Giral et al. [2] employed the interleaved control scheme in the dual buckboost converter. Luo and

Ye [3], [4] utilized the voltage-lift technique to boost the output voltage along with the output voltage ripple taken into account. However, in [1][4], each has one right-half-plane zero in the continuous conduction mode (CCM) [5], [6], and hence, the KY converter [7] is presented to overcome this problem. However, the KY converter has the voltage conversion ratio limited up to one plus D, where D is the duty cycle created from the control effort of the controller. Consequently, the KY converter combined with the traditional synchronously rectied (SR) boost converter is presented herein to create a new voltage-boosting converter, named as KY boost converter, so as to enlarge the voltage ratio of the KY converter. Besides, this converter possesses a special feature that not only this converter always operates in CCM but also both its input and output sides have individual inductors, thereby, making the corresponding current ripples small. A detailed description of the proposed converter with a mathematical deduction is given herein along with some experimental results to demonstrate the effectiveness of such a converter. II. PROPOSED CIRCUIT TOPOLOGY Fig. 1 shows the proposed KY boost converter constructed by the KY converter combined with the traditional SR boost converter, to be described as follows. The KY converter is composed of two switches S1 and S2 , one diode Db , one energytransferring capacitor Cb , one output inductor Lo , and one output capacitor Co . Furthermore, the input of the KY converter is replaced by one buffer capacitor Cm . On the other hand, the traditional SR boost converter consists of two switches S1 and S2 , and one input inductor Li . Moreover, the output of the traditional SR boost converter is replaced by the buffer capacitor Cm . That is to say, the buffer capacitor Cm is a buffer between

Manuscript received October 20, 2009; revised January 17, 2010 and March 22, 2010; accepted May 8, 2010. Date of current version October 29, 2010. This work was supported by the National Science Council under Grant NSC-98-2221E-027-109. Recommended for publication by Associate Editor R. Ayyanar. K. I. Hwu is with the Department of Electrical Engineering, National Taipei University of Technology, Taipei 10608, Taiwan (e-mail: eaglehwu@ ntut.edu.tw). Y. T. Yau is with the Department of Electrical Engineering, National Taipei University of Technology, Taipei 10608, Taiwan, and also with the Industrial Technology Research Institute, Hsinchu 31040, Taiwan. Color versions of one or more of the gures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identier 10.1109/TPEL.2010.2051235

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IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 25, NO. 11, NOVEMBER 2010

Fig. 2.

Fig. 3.

A. Mode 1 the KY converter and the traditional SR boost converter. Besides, the output load is represented by one load resistor RL . In Fig. 2, S1 is turned off and S2 is turned on. In this case, the negative terminal of Cb is pulled to the ground, and hence, Db is forward-biased and turned on. During this mode, Cm is discharged, whereas Cb is charged. Therefore, the voltage across Li is vi , thereby, causing Li to be magnetized, whereas the voltage across Lo is vo subtracted from vC m , thereby, causing Lo to be demagnetized. Also, the current owing through Co is equal to iL o minus the current owing through RL , whereas the current owing through Cm is equal to the sum of iC b and iL o , and hence, the corresponding differential equations are i Li Li = vi t iL o = vC m v o L o t vo vo = iL o Co t R L v Cm = iC b iL o . Cm t B. Mode 2 In Fig. 3, S1 is turned on and S2 is turned off. In this case, S1 is in the ON-state, and hence, Db is reverse-biased and turned off. During this mode, Cm is charged, whereas Cb is discharged. Therefore, the voltage across Li is vC m subtracted from vi , thereby, causing Li to be demagnetized, whereas the voltage across Lo is vo subtracted from 2vC m , thereby, causing Lo to be magnetized. Also, the current owing through Co is equal to iL o minus the current owing through RL , whereas the current owing through Cm is equal to the sum of iL i and iL o . And hence, the corresponding differential equations are i Li = vi v C m Li t iL o = 2vC m vo L o t vo vo = iL o Co t R L vC m = iL i iL o . (2) Cm t

III. BASIC OPERATING PRINCIPLES Before this section is taken up, there are some assumptions are given as follows: 1) dead times between the switches are omitted; 2) voltage drops across the switches and diodes during the turn-ON period are negligible; 3) currents owing through Li and Lo are indicated by iL i and iL o , respectively; and 4) since the energy-transferring capacitor Cb , operating based on the charge pump principle, is abruptly charged to vC m within a very short time, which is much less than the switching period Ts , the value of Cb is large enough to keep the voltage across itself constant at vC m [7]. Prior to discussion of the basic operating principles of the proposed converter, how to start this converter is discussed. As soon as the input voltage is applied to the proposed converter, the capacitor Cm is charged via the body diode D1 of the switch S1 . After this, the pulsewidth-modulated (PWM) control signals are generated and sent to the switches. At the moment, the switch S2 is turned on, and the capacitor Cb is abruptly charged to the voltage across the capacitor Cm . After some switching periods, the proposed converter goes into the steady state. The following analysis contains the explanation of the power ow direction for each mode, the corresponding differential equations and the resulting relationship between the dc input voltage and the dc output voltage. Since this converter is a single-stage converter combining the KY converter and the traditional SR boost converter, it operates always in CCM all over the load range. It is noted that CCM means that the currents owing through the input and output inductors can be positive or negative, but their average values must be positive, that is to say, the average power ow is always from the input to the output. Therefore, there are only two operating modes in this converter, and the turn-ON type of two switches is dened to be (1 D, D), where 1 D and D are for S 1 and S 2 , respectively, and D is the duty cycle of the gate driving signal for S 2 . In addition, since all components are considered ideal, the voltage across Cm follows the voltage across Cb tightly for any time, thereby, making a fth-order derivation reasonably reduced to a fourth-order derivation.

(1)

IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 25, NO. 11, NOVEMBER 2010

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Prior to obtaining the averaged equations from (1) and (2), there is a symbol x that is used to represent the average value of a time-varying variable x, where x indicates voltage or current, as follows: x = 1 Ts

Ts

Then, by substituting (7) into (6), the following equations are obtained: (IL i + iL i ) )(VC m + v Li = (Vi + v i ) (1 D d C m ) t (IL o + iL o ) )(VC m + v = (2 D d Lo C m ) (Vo + v o ) t (Vo + v o ) o ) (Vo + v Co = (IL o + iL o ) t R L C m ) Cm (VC m + v )(IL o + = (2 D d iL o ) t )(IL i + + (1 D d iL i ). (8) Consequently, the quiescent equations can be obtained from (8) to be

xd.

0

(3)

(4)

where d is a variable denoting the time-varying duty cycle of the PWM control signal for S2 . Based on the ampere-second balance, iC b can be expressed as a function of iL o to be iC b = (1 d) iL o d (5)

(9)

and hence, from (9), the corresponding the relationship between VC m and Vi , and the resulting voltage conversion ratio of the KY boost converter can be obtained to be VC m = Vi 1D Vo 2D . = Vi 1D (10)

From (10), as the duty cycle is approaching to 1, the voltage conversion ratio is approaching to innity, whereas as the duty cycle is approaching to 0, the voltage conversion ratio is approaching to 2. On the other hand, with the second-order ac terms neglected, the small-signal ac equations can be obtained from (8) to be (6) iL i (1 D) =v i + VC m d vC m Li t iL o v = (2 D) vC m V C m d L o o t v o v o = iL o Co t RL v + (1 D) Cm C m = (2 D) iL o IL o d iL i IL i d t (11) and hence, the resulting small-signal ac model of the KY boost converter is shown in Fig. 4 according to (11), where T1 and T2 are the ideal transformers with the turns ratios of 1 D : 1 and 1 : 2 D, respectively. By taking the Laplace transform of (11), the corresponding control-to-output transfer function Gv d (s) can be obtained

Prior to obtaining the small-signal ac model from (6), the perturbation and linearization of (6) are indispensable. First of all, x is represented by the corresponding dc quiescent value X plus the superimposed small ac value x , with the assumption that the ac variation is small in magnitude compared to the dc quiescent value. Let vi = Vi + v |v i | i Vi | d=D+d |d D iL i | iL i IL i iL i = IL i + | , with iL o = IL o + iL o | iL o | IL o vo = V o + v o |v o | Vo C m C m | VC m . (7) vC m = V C m + v |v

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IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 25, NO. 11, NOVEMBER 2010

Fig. 4.

Fig. 5.

Fig. 6. Voltage gain versus duty cycle.

From (12), it is obvious that there is no right-half-plane zero in the KY boost converter. IV. CONTROL METHOD APPLIED Fig. 5 shows the overall system conguration for the KY boost converter. The one-comparator counter-based PWM control without any AD converter based on the eld-programmable gate array (FPGA) [8] is utilized, and the parameters of the proportional-integral (PI) controller within FPGA are obtained at rated load to be a proportional gain of kp and an integral gain of ki . The output voltage information VFB after the voltage divider is obtained through the comparator COMP, and then sent to FPGA having a system clock of 100 MHz so as to create the desired PWM control signals M1 and M2 to drive the MOSFET switches S1 and S2 after the gate drives, respectively. V. EXPERIMENTAL RESULTS Before this section is discussed, several requirements, together with the component selection criterion shown in Table I, are given as follows: 1) rated dc input voltage is 12 V; 2) rated dc output voltage is 36 V; 3) rated dc output current is 2.5 A; 4) switching frequency is 195 kHz; 5) value of Li is 15 H created by the T80-52D core produced by Micrometals with the winding of 14 turns, and the value of Lo is the same as that of Li ; 6) one 1000-F Rubycon capacitor is chosen for Cm ; 7) one 680-F Rubycon capacitor is selected for Cb ; 8) one 470-F Rubycon capacitor is chosen for Co ; 9) product names of S1 , S2 , Db , and FPGA are IRL3705ZS, IRL3705ZS, STPS20L60,

and EP1C3T100, respectively; and 10) parameters of the PI controller, kp and ki , are set to 0.75 and 0.016, respectively. The values of the input and output inductors shown earlier are obtained according to the given inductor current ripple, the given switching frequency, and the calculated duty cycle. Regarding the values of three capacitors shown earlier, the value of the output capacitor is rst gured out according to the given inductor current ripple, the given maximum output voltage ripple, and the rule of thumb that capacitance times ESR is about 6.5 105 for the electrolytic capacitor. After this, based on [9], the value of the input capacitor is larger than that of the output capacitor, to stabilize the system. Since the value of the output capacitor has been calculated, the value of the capacitor Cm takes double the value of the output capacitor Co . This is because the capacitor Cm can be considered to be the input capacitor of the KY converter. For the value of the capacitor Cb , it takes the mean values of the two. But, if the detailed design of Cm and Cb is required, allowable variations in capacitor voltage should be taken into account, and this can be seen in [7]. From (10), as the duty cycle is approaching to zero, both the two inductors are considered short-circuited and the output voltage is approaching to double the input voltage. In the meantime, as the duty cycle is approaching to one, the output voltage is approaching to innity, which is impossible. Therefore, there are limitations of duty cycle. From Fig. 6, with one load resistor of 14.4 , the difference in voltage gain between actual and predicted is negligible up to the duty cycle of 85%. That is to

IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 25, NO. 11, NOVEMBER 2010

2703

Fig. 7.

Fig. 10.

whereas above the half load, the proposed converter has worse efciency than the traditional SR boost converter does. It can be seen that for the proposed converter to be considered, the efciency at half load is about 92% and that at rated load is about 90%. VI. CONCLUSION The proposed KY boost converter has higher voltage conversion ratio than the traditional SR boost converter does. Besides, the input and output inductor currents are continuous, different from the traditional SR boost converter, and hence, this converter is very suitable for low-ripple applications. As for the efciency, this converter has the efciency of 90% or more above the half load. Indeed, the proposed converter is suitable for the small-power applications because the surge current created by the charge pump is indispensable. But, using the soft switching with surge current suppressed [10] can overcome this problem, and hence, makes this converter likely to be operated in high-power applications. REFERENCES

[1] H. B. Shin, J. G. Park, S. K. Chung, H. W. Lee, and T. A. Lipo, Generalized steady-state analysis of multiphase interleaved boost converter with coupled inductors, IEE Proc. Electr. Power Appl., no. 152, vol. 3, pp. 584594, 2005. [2] R. Giral, E. Arango, J. Calvente, and L. Martinez-Salamero, Inherent DCM operation of the asymmetrical interleaved dual buck-boost, in Proc. IEEE IECON Conf., 2002, vol. 1, pp. 129134. [3] F. L. Luo and H. Ye, Negative output super-lift converters, IEEE Trans. Power Electron., vol. 18, no. 5, pp. 11131121, Sep. 2003. [4] F. L. Luo and H. Ye, Positive output super-lift converters, IEEE Trans. Power Electron., vol. 18, no. 1, pp. 105113, Jan. 2003. [5] H. Rodriguez, R. Ortega, and G. Escobar, A new family of energy-based non-linear controllers for switched power converters, in Proc. IEEE ISIE Conf., 2001, vol. 2, pp. 723727. [6] S.-C. Tan, Y. M. Lai, C. K. Tse, and C. K. Wu, A pulse width modulation based integral sliding mode current controller for boost converters, in Proc. IEEE PESC Conf., 2006, pp. 17. [7] K. I. Hwu and Y. T. Yau, KY converter and its derivatives, IEEE Trans. Power Electron., vol. 24, no. 1, pp. 128137, Jul. 2009. [8] K. I. Hwu and Y. T. Yau, Applying a counter-based PWM control scheme to an FPGA-based SR forward converter, in Proc. IEEE APEC Conf., 2006, pp. 368372. [9] N. Mohan, T. M. Undeland, and W. P. Robbins, Power Electronics, 2nd ed. New York: Wiley, 2003. [10] K. I. Hwu and Y. T. Yau, Soft switching of KY converter, in Proc. IEEE APEC Conf., 2008, pp. 14771482.

Fig. 8.

Fig. 9. iL o .

say, the useful duty cycle range is about 0%85%. The effect of parasitic parameters on the voltage gain causes the actual to deviate from the predicted. Figs. 79 show the gate-driving signals M1 and M2 for S1 and S2 , respectively, the input inductor currents, and the output inductor currents, at 10%, 50%, and 100% of the rated load, respectively. It is noted that this converter always operates in CCM, since the current owing in the inductor at light load can be negative. On the other hand, for the convenience of efciency comparison between the proposed converter and the traditional SR boost converter, assume that the traditional SR boost converter has the same component specications as the proposed converter does. From Fig. 10, it can be seen that below the middle load, the proposed converter has better efciency than the traditional SR boost converter does,

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