1.sr ff library IEEE; use IEEE.STD_LOGIC_1164.

ALL;

-- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values --use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating -- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all; entity srflipflop is Port ( sr : in STD_LOGIC_VECTOR (1 downto 0);

clk : in STD_LOGIC; reset : in STD_LOGIC; q : inout STD_LOGIC; qbar : inout STD_LOGIC); end srflipflop;

architecture Behavioral of srflipflop is

begin process(sr,clk,reset)

begin if(reset='1') then q<='0'; qbar<=not q; elsif(clk='1' and clk'event) then if(sr="00") then q<=q; qbar<=not q; elsif(sr="01") then q<='0'; qbar<=not q; elsif(sr="10") then q<='1'; qbar<=not q; elsif(sr="11") then q<='X'; qbar<='X'; end if; end if; end process;

end Behavioral; 2.alu library IEEE; use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values --use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating -- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all;

entity alu is Port ( p : in STD_LOGIC_VECTOR (7 downto 0); q : in STD_LOGIC_VECTOR (7 downto 0); r : out STD_LOGIC_VECTOR (7 downto 0); cin1 : in STD_LOGIC; sell : in STD_LOGIC_VECTOR (3 downto 0)); end alu;

architecture Behavioral of alu is signal r1,r2:std_logic_vector(7 downto 0); component arith Port ( sel : in STD_LOGIC_VECTOR (2 downto 0); a : in STD_LOGIC_VECTOR (7 downto 0); b : in STD_LOGIC_VECTOR (7 downto 0); cin : in STD_LOGIC;

z : out STD_LOGIC_vector(7 downto 0)); end component; component logic Port ( a : in STD_LOGIC_VECTOR (7 downto 0); b : in STD_LOGIC_VECTOR (7 downto 0); sel : in STD_LOGIC_VECTOR (2 downto 0); x : out STD_LOGIC_VECTOR (7 downto 0)); end component; component muxalu Port ( x : in STD_LOGIC_VECTOR (7 downto 0); z : in STD_LOGIC_VECTOR (7 downto 0); sel : in STD_LOGIC; y : out STD_LOGIC_VECTOR (7 downto 0)); end component; begin a1:arith port map(sell(2 downto 0),p,q,cin1,r1); l1:logic port map(p,q,sell(2 downto 0),r2); m1:muxalu port map (r1,r2,sell(3),r);

end Behavioral; 3. clockdivider library IEEE; use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using

-- arithmetic functions with Signed or Unsigned values --use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating -- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all;

entity clockdivider is generic(n:positive:=5); Port ( clockin : in STD_LOGIC; reset : in STD_LOGIC; clockout : inout STD_LOGIC); end clockdivider;

architecture Behavioral of clockdivider is begin process(clockin,reset) variable count:natural; begin if(reset='1') then count:=0; clockout<='0'; elsif(clockin='1' and clockin'event) then count:=count+1;

if(count=n) then clockout<=not clockout; count:=0; end if; end if; end process; end Behavioral; 5.decoder library IEEE; use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values --use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating -- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all;

entity decoder is Port ( a : in STD_LOGIC_VECTOR (2 downto 0); d : out STD_LOGIC_VECTOR (7 downto 0)); end decoder;

architecture Behavioral of decoder is

begin d(0)<=(not a(0)) and (not a(1)) and (not a(2)); d(1)<=(not a(2)) and (not a(1)) and a(0); d(2)<=(not a(2)) and a(1) and (not a(0)); d(3)<=(not a(2)) and a(1) and a(0); d(4)<= a(2) and (not a(1)) and (not a(0)); d(5)<= a(2)and (not a(1)) and a(0); d(6)<= a(2)and a(1) and (not a(0)); d(7)<=a(2) and a(1) and a(0);

end Behavioral; 6.demux

library IEEE; use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values --use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating -- any Xilinx primitives in this code.

--library UNISIM; --use UNISIM.VComponents.all;

entity demux is Port ( d : out STD_LOGIC_VECTOR (3 downto 0); a : in STD_LOGIC_VECTOR (1 downto 0); f : in STD_LOGIC); end demux;

architecture Behavioral of demux is

begin

d(3)<=a(1) and a(0) and f; d(2)<=a(1) and (not a(0)) and f; d(1)<= (not a(1)) and a(0) and f; d(0)<= (not a(1)) and (not a(0)) and f; end Behavioral;

7.dff

library IEEE; use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using

-- arithmetic functions with Signed or Unsigned values --use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating -- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all;

entity dflipflop is Port ( d : in STD_LOGIC; clk : in STD_LOGIC; reset : in STD_LOGIC; q : inout STD_LOGIC; qbar : inout STD_LOGIC); end dflipflop;

architecture Behavioral of dflipflop is

begin process (d,clk,reset) begin if(reset='1')then q<='0'; qbar<='1'; elsif(reset='0')then

if(clk='1' and clk'event) then q<=d; qbar<=(not q); end if; end if; end process; end Behavioral; 8.downcounter

library IEEE; use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values --use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating -- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all;

entity downcounter is Port ( reset : in STD_LOGIC; clk : in STD_LOGIC; d: inout STD_LOGIC_VECTOR (2 downto 0));

end downcounter;

architecture Behavioral of downcounter is

signal y,x:std_logic; component tflipflop Port ( t : in STD_LOGIC; clk : in STD_LOGIC; reset : in STD_LOGIC; q : inout STD_LOGIC; qbar : inout STD_LOGIC); end component; begin y<= (not d(0)) and (not d(1)); x<=not d(0); t1:tflipflop port map('1',clk,reset,d(0)); t2:tflipflop port map(x,clk,reset,d(1)); t3:tflipflop port map(y,clk,reset,d(2));

end Behavioral;

9.encoder library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values --use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating -- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all;

entity encoder is Port ( d : in STD_LOGIC_VECTOR (7 downto 0); a : out STD_LOGIC_VECTOR (2 downto 0)); end encoder;

architecture Behavioral of encoder is

begin a(2)<= d(4) or d(5) or d(6) or d(7); a(1)<=d(2) or d(3) or d(6) or d(7); a(0)<=d(1) or d(3) or d(5)or d(7);

end Behavioral;

10.fulladder

library IEEE; use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values --use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating -- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all;

entity fulladder is Port ( a : in STD_LOGIC; b : in STD_LOGIC; cin : in STD_LOGIC; sum : out STD_LOGIC; carry : out STD_LOGIC); end fulladder;

architecture Behavioral of fulladder is signal x,y,z:std_logic ;

begin x<=a xor b; y<=a and b; z<=x and cin; sum<=x xor cin; carry<=z or y; end Behavioral;

11.fulladder 1

library IEEE; use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values --use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating -- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all;

entity fulladder1 is Port ( x1 : in STD_LOGIC; y1 : in STD_LOGIC;

cin : in STD_LOGIC; sum : out STD_LOGIC; cout : out STD_LOGIC); end fulladder1;

architecture Behavioral of fulladder1 is signal sum1,carry1,carry2:std_logic; component halfadder Port ( a : in STD_LOGIC; b : in STD_LOGIC; sum : out STD_LOGIC; carry : out STD_LOGIC); end component; component or1 port(l,m:in std_logic; n: out std_logic); end component; begin h1:halfadder port map(x1,y1,sum1,carry1); h2:halfadder port map(sum1,cin,sum,carry2); o1:or1 port map(carry1,carry2,cout);

end Behavioral;

12.fibanocci

library IEEE; use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating -- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all;

entity fibonacci is generic (count:positive:=16); Port ( reset: in STD_LOGIC; clk : in STD_LOGIC; fib : inout integer range 0 to 255); end fibonacci;

architecture Behavioral of fibonacci is signal a,b,c:integer range 0 to 255; begin process(clk,reset) begin

if(reset='1') then a<=0; b<=1; fib<=0; elsif(clk='1' and clk'event) then a<=b; b<=c; end if; c<=a+b; fib <=a; end process; end Behavioral;

13.fullsubtractor

library IEEE; use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values --use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating -- any Xilinx primitives in this code. --library UNISIM;

--use UNISIM.VComponents.all;

entity fullsubtractor is Port ( a : in STD_LOGIC; b : in STD_LOGIC; borin : in STD_LOGIC; d : out STD_LOGIC; borout : out STD_LOGIC); end fullsubtractor;

architecture Behavioral of fullsubtractor is signal x,y,z: std_logic; begin x<=a xor b; y<=(not a) and b; z<=(not x)and borin; d<=borin xor x; borout<=y or z;

end Behavioral; 14.fullsub1

library IEEE; use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values --use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating -- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all;

entity fullsubtractor1 is Port ( a1 : in STD_LOGIC; b1 : in STD_LOGIC; borin : in STD_LOGIC; difference : out STD_LOGIC; borout : out STD_LOGIC); end fullsubtractor1;

architecture Behavioral of fullsubtractor1 is signal dif1,bor1,bor2: std_logic; component halfsubtractor Port ( a : in STD_LOGIC; b : in STD_LOGIC; d : out STD_LOGIC; bor : out STD_LOGIC); end component;

component or1 port(l,m:in std_logic; n: out std_logic); end component;

begin h1:halfsubtractor port map(a1,b1,dif1,bor1); h2:halfsubtractor port map(dif1,borin,difference,bor2); o1:or1 port map(bor1,bor2,borout); end Behavioral;

15.half adder

library IEEE; use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values --use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating -- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all;

entity halfadder is Port ( a : in STD_LOGIC; b : in STD_LOGIC; sum : out STD_LOGIC; carry : out STD_LOGIC); end halfadder;

architecture Behavioral of halfadder is

begin sum<=a xor b; carry<=a and b;

end Behavioral;

16.half subtractor

library IEEE; use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values --use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating

-- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all;

entity halfsubtractor is Port ( a : in STD_LOGIC; b : in STD_LOGIC; d : out STD_LOGIC; bor : out STD_LOGIC); end halfsubtractor;

architecture Behavioral of halfsubtractor is

begin

d<=a xor b; bor<=(not a) and b; end Behavioral;

18.instruction decoder

library IEEE; use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using

-- arithmetic functions with Signed or Unsigned values --use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating -- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all;

entity INSTDEC is Port ( I : in STD_LOGIC_VECTOR (7 downto 0); HLT,Jmp,Lda,Add,Sub,Sta,Mjmp,Pjmp,IN1,OUT1,ALS,ARS,LLS,LRS : out STD_LOGIC); end INSTDEC;

architecture Behavioral of INSTDEC is component And2 is Port ( A1,A2 : in STD_LOGIC; Y : out STD_LOGIC); end component; component and3 is Port ( A1,A2,A3 : in STD_LOGIC; Y : out STD_LOGIC); end component; component and5 is Port ( A1,A2,A3,A4,A5 : in STD_LOGIC;

Y : out STD_LOGIC); end component; component and6 is Port ( A1,A2,A3,A4,A5,A6 : in STD_LOGIC; Y : out STD_LOGIC); end component; component nor3 is Port ( A1,A2,A3 : in STD_LOGIC; Y : out STD_LOGIC); end component; signal P,Q,R,S:std_logic; signal x:std_logic_vector(7 downto 0); begin x<=not I; S<=NOT R; P1:and3 port map(x(7),x(6),I(5),Lda); P2:and3 port map(x(7),I(6),x(5),Add); P3:and3 port map(x(7),I(6),I(5),Sub); P4:and3 port map(I(7),x(6),x(5),Sta); P5:and3 port map(I(7),I(6),x(5),Mjmp); P6:and3 port map(I(7),x(6),I(5),Pjmp); P7:nor3 port map(I(7),I(6),I(5),P); P8:and3 port map(I(7),I(6),I(5),Q); P9:and5 port map(x(4),x(3),x(2),x(1),x(0),R); P10:And2 port map(R,Q,IN1);

P11:and6 port map(Q,x(4),x(3),I(2),x(1),x(0),out1); P12:and6 port map(Q,x(4),x(3),x(2),x(1),I(0),als); P13:and6 port map(Q,x(4),x(3),x(2),I(1),x(0),ars); P14:and6 port map(Q,x(4),x(3),I(2),x(1),I(0),lls); P15:and6 port map(Q,x(4),x(3),I(2),I(1),x(0),lrs); P16:And2 port map(P,R,HLT); P17:And2 port map(P,S,Jmp); end Behavioral;

18.jk ff

---------------------------------------------------------------------------------library IEEE; use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values --use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating -- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all;

entity jkflipflop is

Port ( jk : in STD_LOGIC_VECTOR (1 downto 0);

clk : in STD_LOGIC; reset : in STD_LOGIC; q : inout STD_LOGIC; qbar : inout STD_LOGIC); end jkflipflop;

architecture Behavioral of jkflipflop is

begin process(jk,clk,reset) begin if(reset='1') then q<='0'; qbar<=not q; elsif(clk='1' and clk'event) then if(jk="00") then q<=q; qbar<=not q; elsif(jk="01") then q<='0'; qbar<=not q; elsif(jk="10") then q<='1';

qbar<=not q; elsif(jk="11") then q<=not q; qbar<=not q; end if; end if; end process; end Behavioral; 19.mealy

library IEEE; use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values --use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating -- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all;

entity mealy is Port ( a : in STD_LOGIC; clk : in STD_LOGIC;

z : out STD_LOGIC); end mealy;

architecture Behavioral of mealy is type state_type is (st0,st1,st2,st3); signal mealy_state:state_type; begin process(a,clk) begin if(clk='0') then case mealy_state is when st0=> if(a='1') then mealy_state<=st3; z<='1'; else mealy_state<=st0; z<='0'; end if; when st1=> if(a='1') then mealy_state<=st0; z<='0'; else mealy_state<=st1; z<='1'; end if;

when st2=> if(a='1') then mealy_state<=st1; z<='1'; else mealy_state<=st2; z<='0'; end if; when st3=> if(a='1') then mealy_state<=st1; z<='0'; else mealy_state<=st2; z<='0'; end if; end case; end if; end process; end Behavioral;

20.moore

library IEEE; use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values --use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating -- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all;

entity moore is Port ( a : in STD_LOGIC; clk : in STD_LOGIC; z : out STD_LOGIC); end moore;

architecture Behavioral of moore is type state_type is (st0,st1,st2,st3); signal moore_state:state_type; begin process(a,clk) begin if(clk='0') then case moore_state is when st0=> z<='1'; if(a='1') then

moore_state<=st2; end if; when st1=> z<='0'; if(a='1') then moore_state<=st3; end if; when st2=> z<='0'; if(a='0') then moore_state<=st1; else moore_state<=st3; end if; when st3=> z<='1'; if(a='1') then moore_state<=st0; end if; end case; end if; end process; end Behavioral;

21.mux

library IEEE; use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values --use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating -- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all;

entity mux is Port ( c : in STD_LOGIC_VECTOR (3 downto 0); a : in STD_LOGIC_VECTOR (1 downto 0); z : out STD_LOGIC); end mux;

architecture Behavioral of mux is signal p,q,r,s: std_logic; begin p<=c(0) and (not a(0)) and (not a(1)); q<=c(1) and (not a(0)) and a(1); r<=c(2)and a(0) and (not a(1)); s<=c(3) and a(0) and a(1); z<=(p or q) or (r or s);

end Behavioral;

22.mux21

library IEEE; use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values --use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating -- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all;

entity mux2 is Port ( d : in STD_LOGIC_VECTOR (1 downto 0); a : in STD_LOGIC; z1 : out STD_LOGIC); end mux2;

architecture Behavioral of mux2 is signal p1,q1:std_logic; begin

p1<=d(0) and (not(a)); q1<=d(1) and a; z1<=p1 or q1; end Behavioral; 23.mux41

library IEEE; use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values --use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating -- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all;

entity mux41 is Port ( c: in STD_LOGIC_VECTOR (3 downto 0); a1 : in STD_LOGIC; a0: in STD_LOGIC; m: out STD_LOGIC); end mux41;

architecture Behavioral of mux41 is signal q:std_logic_vector(1 downto 0); component mux2 Port ( d : in STD_LOGIC_VECTOR (1 downto 0); a : in STD_LOGIC; z1 : out STD_LOGIC); end component;

begin m1:mux2 port map(c(1 downto 0),a0,q(1)); m2:mux2 port map(c(3 downto 2),a0,q(0)); m3:mux2 port map(q(1 downto 0),a1,m); end Behavioral;

23.pipo

library IEEE; use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values --use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating -- any Xilinx primitives in this code.

--library UNISIM; --use UNISIM.VComponents.all;

entity pipo is Port ( clk : in STD_LOGIC; reset : in STD_LOGIC; d : in STD_LOGIC_VECTOR (3 downto 0); q : inout STD_LOGIC_VECTOR (3 downto 0)); end pipo;

architecture Behavioral of pipo is

begin process(clk,reset,d,q) begin if(reset='1') then q<="0000"; elsif(clk='1' and clk'event) then q(0)<=d(0); q(1)<=d(1); q(2)<=d(2); q(3)<=d(3); end if; end process;

end Behavioral;

24.piso

library IEEE; use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values --use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating -- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all;

entity piso is Port ( load : in STD_LOGIC; clk : in STD_LOGIC; reset : in STD_LOGIC; d : in STD_LOGIC_VECTOR (3 downto 0); q : inout STD_LOGIC); end piso;

architecture Behavioral of piso is signal a,b,c:std_logic; begin

process(load,clk,reset,q,d) begin if(reset='1') then q<='0'; elsif(clk ='1' and clk'event) then if(load='1') then a<=d(3); b<=d(2); c<=d(1); q<=d(0); else q<=a; a<=b; b<=c; c<=d(3); end if; end if; end process; end Behavioral;

25.ripple carry

library IEEE; use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values

--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating -- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all;

entity ripplecarryadder is Port ( a : in STD_LOGIC_VECTOR (3 downto 0); b : in STD_LOGIC_VECTOR (3 downto 0); cin : in STD_LOGIC; s : out STD_LOGIC_VECTOR (3 downto 0); cout : out STD_LOGIC); end ripplecarryadder;

architecture Behavioral of ripplecarryadder is signal c:std_logic_vector(2 downto 0);

component fulladder Port ( a : in STD_LOGIC; b : in STD_LOGIC; cin : in STD_LOGIC; sum : out STD_LOGIC; carry : out STD_LOGIC); end component;

begin f1:fulladder port map(a(0),b(0),cin,s(0),c(0)); f2:fulladder port map(a(1),b(1),c(0),s(1),c(1)); f3:fulladder port map(a(2),b(2),c(1),s(2),c(2)); f4:fulladder port map(a(3),b(3),c(2),s(3),cout);

end Behavioral;

26.sequence

library IEEE; use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values --use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating -- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all;

entity sequence is Port ( x : in STD_LOGIC; clk ,reset: in STD_LOGIC;

z : out STD_LOGIC); end sequence;

architecture Behavioral of sequence is type state_type is (a,b,c,d); signal state:state_type; begin process(x,clk,reset) begin if(reset='1') then z<='0'; state<=a; elsif(clk='0') then case (state) is when a => if(x='1') then state<=b; z<='0'; else state<=a; z<='0'; end if; when b=> if(x='0') then state<=c; z<='0'; else

state<=b; z<='0'; end if; when c=> if(x='1') then state<=d; z<='0'; else state<=a; z<='0'; end if; when d=> if(x='1') then state<=a; z<='1'; else state<=c; z<='0'; end if; end case; end if; end process; end Behavioral;

28.sequence 1

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values --use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating -- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all;

entity sequence1 is Port ( x : in STD_LOGIC; clk ,reset: in STD_LOGIC; z : out STD_LOGIC); end sequence1;

architecture Behavioral of sequence1 is type state_type is (a,b,c,d,e); signal state:state_type; begin process(x,clk,reset) begin if(reset='1') then z<='0';

state<=a; elsif(clk='1' and clk'event) then case (state) is when a => if(x='1') then state<=b; z<='0'; else state<=a; z<='0'; end if; when b=> if(x='1') then state<=c; z<='0'; else state<=a; z<='0'; end if; when c=> if(x='0') then state<=d; z<='0'; else state<=c; z<='0'; end if; when d=> if(x='1') then

state<=e; z<='0'; else state<=a; z<='0'; end if; when e=> if(x='1') then state<=c; z<='1'; else state<=a; z<='0'; end if;

end case; end if; end process; end Behavioral;

29.sipo

library IEEE; use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using

-- arithmetic functions with Signed or Unsigned values --use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating -- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all;

entity sipo is Port ( clk : in STD_LOGIC; reset : in STD_LOGIC; d : in STD_LOGIC; q : inout STD_LOGIC_vector(3 downto 0)); end sipo;

architecture Behavioral of sipo is --signal x,y,z:std_logic; begin process(d,clk,reset,q) begin if(reset='1') then q<="0000"; elsif(clk='1' and clk'event) then q(3)<=d; q(2)<=q(3); q(1)<=q(2); q(0)<=q(1); end if;

end process; end Behavioral;

29.siso

---------------------------------------------------------------------------------library IEEE; use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values --use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating -- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all;

entity siso is Port ( d : in STD_LOGIC; clk : in STD_LOGIC; reset : in STD_LOGIC; q : inout STD_LOGIC); end siso;

architecture Behavioral of siso is signal x,y,z:std_logic; begin process(d,clk,reset,q) begin if(reset='1') then q<='0'; x<='0'; y<='0'; z<='0'; elsif(clk='1' and clk'event) then x<=d; y<=x; z<=y; q<=z;

end if; end process; end Behavioral;

30.srff

library IEEE; use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values

--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating -- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all; entity srflipflop is Port ( sr : in STD_LOGIC_VECTOR (1 downto 0);

clk : in STD_LOGIC; reset : in STD_LOGIC; q : inout STD_LOGIC; qbar : inout STD_LOGIC); end srflipflop;

architecture Behavioral of srflipflop is

begin process(sr,clk,reset) begin if(reset='1') then q<='0'; qbar<=not q; elsif(clk='1' and clk'event) then if(sr="00") then

q<=q; qbar<=not q; elsif(sr="01") then q<='0'; qbar<=not q; elsif(sr="10") then q<='1'; qbar<=not q; elsif(sr="11") then q<='X'; qbar<='X'; end if; end if; end process;

end Behavioral;

tff

library IEEE; use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values --use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating -- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all;

entity tflipflop is Port ( t : in STD_LOGIC; clk : in STD_LOGIC; reset : in STD_LOGIC; q : inout STD_LOGIC; qbar : inout STD_LOGIC); end tflipflop;

architecture Behavioral of tflipflop is

begin process (t,clk,reset,q,qbar) begin if(reset='1')then q<='0'; qbar<='1'; elsif(clk='1' and clk'event) then if(t='1') then q<=(not q);

qbar<=(not qbar); else q<=q; qbar<=qbar; end if; end if; end process;

end Behavioral;

30.usr

library IEEE; use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values --use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating -- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all;

entity usr is Port ( q : inout STD_LOGIC_VECTOR (3 downto 0); i : in STD_LOGIC_VECTOR (3 downto 0); s : in STD_LOGIC_VECTOR (1 downto 0); clk ,ir,il: in STD_LOGIC; reset : in STD_LOGIC); end usr;

architecture Behavioral of usr is signal o:std_logic_vector(3 downto 0); signal qb:std_logic_vector(3 downto 0);

component muxusr Port ( a0 : in STD_LOGIC; a1 : in STD_LOGIC; a2 : in STD_LOGIC; a3 : in STD_LOGIC; s : in STD_LOGIC_VECTOR (1 downto 0); z : out STD_LOGIC); end component; component dflipflop Port ( d : in STD_LOGIC; clk : in STD_LOGIC; reset : in STD_LOGIC;

q : inout STD_LOGIC; qbar : inout STD_LOGIC); end component; begin m1:muxusr port map(q(3),ir,q(2),i(3),s,o(3)); m2:muxusr port map(q(2),q(3),q(1),i(2),s,o(2)); m3:muxusr port map(q(1),q(2),q(0),i(1),s,o(1)); m4:muxusr port map(q(0),q(1),il,i(0),s,o(0)); d1:dflipflop port map(o(3),clk,reset,q(3),qb(3)); d2:dflipflop port map(o(2),clk,reset,q(2),qb(2)); d3:dflipflop port map(o(1),clk,reset,q(1),qb(1)); d4:dflipflop port map(o(0),clk,reset,q(0),qb(0));

end Behavioral;

muxusr

library IEEE; use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values --use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating -- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all;

entity muxusr is Port ( a0 : in STD_LOGIC; a1 : in STD_LOGIC; a2 : in STD_LOGIC; a3 : in STD_LOGIC; s : in STD_LOGIC_VECTOR (1 downto 0); z : out STD_LOGIC); end muxusr;

architecture Behavioral of muxusr is

begin process(a0,a1,a2,a3,s) begin case s is when "00"=> z<=a0; when "01"=> z<=a1; when "10"=> z<=a2; when "11"=> z<=a3; when others=>null;

end case; end process; end Behavioral;

31.upcounter

library IEEE; use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values --use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating -- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all;

entity upcounter is Port ( reset : in STD_LOGIC; clk : in STD_LOGIC; q : inout STD_LOGIC_VECTOR (2 downto 0)); end upcounter;

architecture Behavioral of upcounter is

signal y:std_logic; component tflipflop Port ( t : in STD_LOGIC; clk : in STD_LOGIC; reset : in STD_LOGIC; q : inout STD_LOGIC; qbar : inout STD_LOGIC); end component; begin y<=q(0) and q(1); t1:tflipflop port map('1',clk,reset,q(0)); t2:tflipflop port map(q(0),clk,reset,q(1)); t3:tflipflop port map(y,clk,reset,q(2)); end Behavioral;

upcounter

library IEEE; use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values --use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating -- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all;

entity upcounter is Port ( reset : in STD_LOGIC; clk : in STD_LOGIC; q : inout STD_LOGIC_VECTOR (2 downto 0)); end upcounter;

architecture Behavioral of upcounter is signal y:std_logic; component tflipflop Port ( t : in STD_LOGIC; clk : in STD_LOGIC; reset : in STD_LOGIC; q : inout STD_LOGIC; qbar : inout STD_LOGIC); end component; begin y<=q(0) and q(1); t1:tflipflop port map('1',clk,reset,q(0)); t2:tflipflop port map(q(0),clk,reset,q(1)); t3:tflipflop port map(y,clk,reset,q(2));

end Behavioral;

updowncounter

library IEEE; use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values --use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating -- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all;

entity updowncounter is Port ( q: inout STD_LOGIC_VECTOR (2 downto 0); clk : in STD_LOGIC; reset : in STD_LOGIC; mode : in STD_LOGIC); end updowncounter;

architecture Behavioral of updowncounter is signal u,d:

component muxcounter Port ( x : in STD_LOGIC_VECTOR (2 downto 0); z : in STD_LOGIC_VECTOR (2 downto 0); sel : in STD_LOGIC; y : out STD_LOGIC_VECTOR (2 downto 0)); end component; component upcounter Port ( reset : in STD_LOGIC; clk : in STD_LOGIC; q : inout STD_LOGIC_VECTOR (2 downto 0)); end component; component downcounter Port ( reset : in STD_LOGIC; clk : in STD_LOGIC; d: inout STD_LOGIC_VECTOR (2 downto 0)); end component;

begin u1:upcounter port map(reset,clk,u); d1:downcounter port map(reset,clk,d); m1:muxcounter port map(u,d,mode,q); end Behavioral;

usr

library IEEE; use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values --use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating -- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all;

entity usr is Port ( i : in STD_LOGIC_VECTOR (3 downto 0); q : inout STD_LOGIC_VECTOR (3 downto 0); s : in STD_LOGIC_VECTOR (1 downto 0); clk : in STD_LOGIC; reset,ir,il : in STD_LOGIC); end usr;

architecture Behavioral of usr is --signal d :std_logic(3 downto 0); begin process(i,s,clk,reset) begin

if(reset='1') then q<="0000"; elsif(clk='1' and clk'event) then if(s="00") then q<=q; elsif(s="10") then q(3)<=q(2); q(2)<=q(1); q(1)<=q(0); q(0)<=il; elsif(s="01") then q(3)<=ir; q(2)<=q(3); q(1)<=q(2); q(0)<=q(1); elsif(s="11") then q<=i; end if; end if; end process; end Behavioral;