FORMAT NO ISSUE NO REVISION NO

: CCE/ACAD/11 : 01 : 00

CHANDY COLLEGE OF ENGINEERING, CHANDY NAGAR, TUTICORIN 628 005. (Approved by AICTE and Affiliated to Anna University) DEPARTMENT OF COMPUTER SCIENCE AND ENGINEERING

Subject Name Leo Branch/ Year

: Advanced Computer Architecture

Subject Code: CS 2354

Faculty Name

: Mr.E.Sathesh Abraham

: CSE/ III

Batch

: 2011-2015

AIM: The course provides an introduction to advance principles and current practise in computer architecture. It covers topics such as instruction set design, hardware and software for parallelism and input output system. The course is also introduces multiprocessor concepts.

OBJECTIVE: To learn the various concepts and challenges of instruction level parallelism To understand the advanced principles of current practise in computer architecture. To learn the computer design concepts and principles To efficiently implement the various multiple issue processors and its techniques To learn memory and input/output system. To understand the multi-core architectures and its operations.

UNIT I INSTRUCTION LEVEL PARALLELISM Sl.No 1. 2. 3. 4. 5. 6. 7. Topics Instruction Level Parallelism Concepts and challenges Hardware and software approaches Dynamic scheduling Speculation Compiler techniques for exposing ILP Branch prediction Text Books T1 T1 T1 T1 T1 T1 T1 Page No 66-74 66-74 104-114 89-97 121-131 74-80 80-89 Proposed Date Actual Date Reason for Deviation No. Of Hours Required 2 1 1 1 1 1 1 No of Cumulative Hours 2 3 4 5 6 7 8

UNIT II - MULTIPLE ISSUE PROCESSORS Sl.No 1. 2. 3. 4. 5. 6. 7. VLIW & EPIC Advanced compiler support Hardware support for exposing parallelism H/W versus software speculation mechanisms speculation mechanisms IA 64 and Itanium processors Limits on ILP Topics Text Books T1 T1 T1 T1 T1 T1 T1 Page No 97-108 110-116 170-172 120-131 120-131 131-137 154-165 Proposed Date Actual Date Reason for Deviation No. Of Hours Required 1 1 1 1 1 2 1 No of Cumulative Hours 9 10 11 12 13 15 16

UNIT III - MULTIPROCESSORS AND THREAD LEVEL PARALLELISM Sl.No 1. 2. 3. 4. 5. 6. Topics Symmetric shared memory architectures Distributed shared memory architectures Performance issues Synchronization Models of memory consistency Introduction to Multithreading Text Books T1 T1 T1 T1 T1 T1 Page No 205-211 211-226 226-231 237-243 243-246 145-154 Proposed Date Actual Date Reason for Deviation No. of Hours Required 1 1 1 1 1 1 No of Cumulative Hours 17 18 19 20 21 22

UNIT IV - MEMORY AND I/O

Sl.No 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. Cache performance

Topics

Text Books T1 T1 T1 T1 T1 T1 T1 T1 T1 T1 T1

Page No 293-295 295-304 304-309 310-315 316-320 322-340 340-352 353-365 411-412 371-379 392-398

Proposed Date

Actual Date

Reason for Deviation

No. of Hours Required 1 1 1 1 2 1 1 1 1 2 1

No of Cumulative Hours 23 24 25 26 28 29 30 31 32 34 35

Reducing cache miss penalty and miss rate Reducing hit time Main memory and performance Memory technology Types of storage devices Buses RAID Reliability, availability and dependability I/O performance measures Designing an I/O system

UNIT V MULTI-CORE ARCHITECTURES

Sl.No 1. 2. 3. 4. 5. 6. 7.

Topics Software and hardware multithreading SMT and CMP architectures Design issues Intel Multi-core architecture SUN CMP architecture heterogenous multi-core processors IBM Cell Processor

Text Books T1 T1 T1 T1 T1 T1 T1

Page No 415-425 450-470 425-430 431-440 441-449 475-490 505-520

Proposed Date

Actual Date

Reason for Deviation

No. Of Hours Required 1 1 1 2 1 2 2

No of Cumulative Hours 36 37 39 40 41 43 45

TEXT BOOKS: 1. John L. Hennessey and David A. Patterson, Computer architecture A quantitative Approach, Morgan Kaufmann /Elsevier Publishers, 4th. Edition, 2007. REFERENCES: 1. David E. Culler, Jaswinder Pal Singh, Parallel computing architecture: A hardware / software approach, Morgan Kaufmann /Elsevier Publishers, 1999. 2. Kai Hwang and Zhi.Wei Xu, Scalable Parallel Computing, Tata McGraw Hill, New Delhi, 2003.

STAFF IN CHARGE

HOD

DEAN ACADEMIC

PRINCIPAL