EXPERIMENT AIM- Design and Implementation of Universal Asynchronous Transmitter & Receiver. TOOL USED:1.

Xilinx ISE Design Suite 12.4

THEORY: Most computers and micro controllers have one or more serial data ports used to communicate with serial input/output devices such as keyboards and serial printer. By using a modem connected to serial port, serial data can be Transmitted to and Received from a remote location via telephone lines. The serial communication interface, which receives and transmits serial data, is often called a UART (Universal Asynchronous Receiver Transmitter).

Figure 1 Serial Data Transmission

UART OPERATION:

The UART Transmitter is always part of larger environment in which a host processor controls transmission by fetching a data word in a parallel format and directing the UART to transmit in a serial format. Likewise, the Receiver must detect transmission, receive the data in serial format, strip off the start and stop bits, and store the data word in a parallel format.
RXD
8 Data bits

Start Bit

Stop Bit

Figure 2 Standard serial data format

Block diagram of UART :-

Figure 3: Block Diagram of UART

VHDL code for UART Transmitter:library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_unsigned.ALL; entity uart_txm is port(data_bus : in std_logic_vector(7 downto 0); byte_ready,transmit_byte,reset,clk: in std_logic;

serial_out:out std_logic); end uart_txm; architecture behavioral_uart of uart_txm is signal txm_data_reg : std_logic_vector(7 downto 0); signal txm_shift_reg: std_logic_vector(8 downto 0); signal load_shift_reg: std_logic; signal load_data_reg: std_logic; type state is (idle,waiting,sending); signal next_state,pre_state :state; signal bit_count: integer range 0 to 9; signal clear,shift:std_logic; begin process(pre_state,clk,transmit_byte,byte_ready,bit_count) begin clear<='0'; shift<='0'; serial_out<=txm_shift_reg(0); case pre_state is when idle => if(byte_ready='1')then load_data_reg<='1'; next_state<= waiting; end if; when waiting=> if(transmit_byte='1')then load_shift_reg<='1'; next_state<= sending; end if; when sending=> if(bit_count/= 9)then shift<='1'; else clear<='1';

next_state<= idle; end if; end case; end process; process(reset,clk) begin if(reset='1')then txm_shift_reg<="111111111"; pre_state<= idle; elsif(clk'event and clk='1')then pre_state<=next_state; end if; if(load_data_reg='1')then txm_data_reg<=data_bus; end if; if(load_shift_reg='1')then txm_shift_reg <=txm_data_reg(7 downto 0)& '0'; end if; if(clear='1')then bit_count<=0; elsif(shift='1')then bit_count<= bit_count + 1; txm_shift_reg<='1' & txm_shift_reg(8 downto 1); end if; end process; end behavioral_uart;

RTL View of Transmitter:-

Wave form of transmitter:-

Device utilization summary:Device Utilization Summary (estimated values) Logic Utilization Number of Slices Number of Slice Flip Flops Number of 4 input LUTs Number of bonded IOBs Number of GCLKs Used 6 10 11 5 1 Available 768 1536 1536 124 8 Utilization 0% 0% 0% 4% 12% [-]

Timing Summary:Speed Grade: -5 Minimum period: 2.670ns (Maximum Frequency: 374.574MHz) Minimum input arrival time before clock: 2.285ns Maximum output required time after clock: 9.216ns Maximum combinational path delay: No path found VHDL code for UART receiver:library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity uart_rcv is port(reset,serial_in,sample_clk:in std_logic; read_not_ready_out:out std_logic); end uart_rcv; architecture behavioral_uart of uart_rcv is signal rcv_datareg:std_logic_vector(7 downto 0); signal rcv_shiftreg:std_logic_vector(7 downto 0);

signal sample_counter: integer range 0 to 8; signal bit_counter: integer range 0 to 8; type state is (idle,starting, recieving); signal pre_state,next_state: state; signal inc_bit_counter:std_logic; signal clr_bit_counter: std_logic; signal inc_sample_counter:std_logic; signal clr_sample_counter: std_logic; signal shift: std_logic; signal load: std_logic; begin process(pre_state,serial_in,sample_counter,bit_counter,inc_sample_counter, clr_sample_counter,inc_bit_counter,clr_bit_counter,shift) begin read_not_ready_out<='0'; clr_sample_counter<='0'; inc_sample_counter<='0'; clr_bit_counter<='0'; inc_bit_counter<='0'; shift<='0'; load<='0'; next_state<=pre_state; case pre_state is when idle => if serial_in='0' then next_state <= starting; end if; when starting => if serial_in ='1' then next_state<= idle; clr_sample_counter<='1'; elsif (sample_counter=4) then next_state<= recieving ;

clr_sample_counter<='1'; else inc_sample_counter<='1'; end if; when recieving=> if (sample_counter< 8) then inc_sample_counter<= '1'; else clr_sample_counter<='1'; if (sample_counter = 8) then shift<='1'; inc_bit_counter<= '1'; end if; end if; if (bit_counter = 8) then next_state<= idle; read_not_ready_out<='1'; clr_bit_counter<='1'; load<='1'; end if; end case; end process; process(sample_clk) begin if (reset='1') then pre_state<= idle; sample_counter<= 0; bit_counter<= 0; rcv_datareg <= "00000000"; rcv_shiftreg<= "00000000"; else pre_state <= next_state; if (clr_sample_counter= '1')then

sample_counter<= 0; elsif(inc_sample_counter='1') then sample_counter<=sample_counter + 1; end if; if (clr_bit_counter='1') then bit_counter<=0; elsif(inc_bit_counter='1') then bit_counter<=bit_counter + 1; end if; if (shift='1' )then rcv_shiftreg<=serial_in & rcv_shiftreg (7 downto 1); end if; if (load = '1') then rcv_datareg<= rcv_shiftreg; end if; end if; end process; end behavioral_uart;

UART receiver RTL view:-

UART receiver wave form:-

Device utilization summary:Device Utilization Summary (estimated values) Logic Utilization Number of Slices Number of Slice Flip Flops Number of 4 input LUTs Number of bonded IOBs Used 12 8 21 3 Available 768 1536 1536 124 Utilization 1% 0% 1% 2%

Timing summary:-

Speed Grade: -5 Minimum period: 2.739ns (Maximum Frequency: 365.043MHz) Minimum input arrival time before clock: No path found Maximum output required time after clock: 16.933ns Maximum combinational path delay: 15.429ns