Proceedings of the 2009 IEEE 9th Malaysia International Conference on Communications 15 -17 December 2009 Kuala Lumpur Malaysia

Design of BPSK Transmitter Using FPGA with DAC

Y. H. Chye1, M. F. Ain2, Norzihan M. Zawawi3
1, 2, 3

Communication Research Group, School of Electrical and Electronic Engineering, Engineering Campus, Universiti Sains Malaysia, 14300 Nibong Tebal, Pulau Pinang, Malaysia.
1

chyeyinhui1984@hotmail.com 2 mfadzil@eng.usm.my 3 nor_zihan@yahoo.com

Abstract In contrast to the sophisticated implementation of binary phase shift keying (BPSK) transmitter using application specific integrated circuit (ASIC), mixer, and local oscillator (LO) for carrier signal; software defined radio (SDR) provides a high performance, efficient, and re-configurable platform to integrate all these individual functions of BPSK transmitter. This paper presents a tutorial exploitation to design and implement BPSK transmitter using field programmable gate array (FPGA) for digital signal processing (DSP), and expansion P240 Analog Module for digital-to-analog (D/A) conversion. For simplicity, the period of carrier sinusoidal signal is designed as one cycle per bit for 5 Mbps input bit. The DSP-based BPSK transmitter is developed and compiled to Verilog HDL (Hardware Description Language) netlist. For proper interfacing D/A converter (DAC) with FPGA, a HDL module of configurations of P240 Analog Module and clock synthesizer is integrated with the HDL netlist of BPSK transmitter. Finally, the optimally synthesized netlist of the integrated design is implemented into Xilinx Virtex-4 FPGA MB development board with DAC. The verification of DAC output signal via oscilloscope shows the empirical real-time result similar to the simulated result. Further up-conversion for the BPSK transmitted signal to higher frequency can be done using external analog RF devices with some design modifications. Keywords BPSK, transmitter, software defined radio, FPGA, DAC.

of BPSK transmitter using FPGA is shown in Fig. 1. In BPSK baseband processing, the input bit with value of 0 or 1 is mapped to symbol with gain (Gb) of 1 or +1 respectively through polar conversion. At the same time, local oscillator (LO) generates carrier sinusoidal signal with frequency (fc) to be mixed with Gb by multiplier to produce BPSK transmitted signal (SBPSK). While clock with certain frequency (sampling rate) controls the timing of BPSK transmitter in FPGA.

Fig. 1 BPSK transmitter using FPGA

I. INTRODUCTION Since the advent of wireless communications such as 3G and 4G, software radio (SR) or software defined radio (SDR) becomes dominant due to its highly configurable hardware and software platforms, as compared to the sophisticated and complicated hardware platforms [1]. SDR performs various intermediate frequency (IF) and baseband signal processing functions by using Digital Signal Processing (DSP) and logic algorithms [2]. The commonly used silicon solutions for SDR implementation are field programmable gate arrays (FPGAs), digital signal processors (DSPs), general purpose processors (GPPs), and application-specific integrated circuits (ASICs). FPGA offers the best solution in IF stage and wideband (WB) modem processing because it provides high speed, high level of integration, high flexibility, and low development costs, though it may have high power consumption due to inefficient use of the FPGA logic elements (slices) [3]. In SDR system, BPSK is a simple one-dimensional (1D) modulation scheme that the phase of carrier sinusoidal signal changes abruptly by 1800 or radian for every transition of modulating binary sequence (input bit) [4]. The block diagram

Several researches on digital implementation of SDR-based BPSK have been done as in [5]-[8], but there still remain some critical issues of interfacing analog-to-digital converter (ADC) and digital-to-analog converter (DAC) with FPGA. This paper does not only present design and implementation of DSP-based BPSK transmitter using FPGA, but also HDL (Hardware Description Language) module of configurations of expansion P240 Analog Module (especially DAC) and clock synthesizer that controls FPGA system clock frequency. The implementation issues for integration of HDL netlist of BPSK transmitter and HDL module of setup configuration will also be addressed. Next, analysis reports for validating the timing and area constraints during processes of synthesis and FPGA implementation stage will be discussed. Lastly, the verification of real-time result (DAC output signal) is done via observation from oscilloscope. II. SYSTEM LEVEL DESIGN AND SIMULATION A. Design and Simulation Using DSP Design Tools The DSP-based design of BPSK transmitter is developed in user-friendly DSP Design Tools i.e. Xilinx System Generator in Matlab/Simulink environment [9]. The Graphical User Interface (GUI) of the design is model-based structure using Simulink and Xilinx specific blocksets as shown in Fig. 2. The functions and operations of each block or subsystem are discussed in the following descriptions under sub-headings.

978-1-4244-5532-4/09/$26.00 2009 IEEE

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Fig. 2 BPSK transmitter design using System Generator

5) Polar Conversion Subsystem: The subsystem shown in Fig. 4 uses selection method to map the Boolean value 0 or 1 of input bit to 1 or +1 respectively. The inputs rst and bit are concatenated (by Concat) to become 2-bit unsigned integer as input selection sel of multiplexer Mux. For input rst is 0, when input bit is 1, output polar is +1 (Constant1 value) via Mux and Register; otherwise 1 (Negate operation upon Constant1). When input rst is 1, disregarding input bit value, output polar is 0 (Constant2 value). The output polar is set to 2-bit unsigned integer (binary point: 0). Notice that the 1 sample delay (latency: 1) for Register operation is used to match the latency of 1 existing in Sin Generator subsystem.

1) System Generator Block: The token is used to set Simulink system period: 1, and FPGA clock period: 10 ns (100 MSps sampling rate). It is used to generate Verilog HDL netlist of BPSK transmitter with its test-bench file [9]. 2) Constant Block: Simulink source block that acts as input reset signal (0 or 1) with sample time 1 unit. It is set to 0 to deactivate the system reset function in this case. 3) Reset Block: Xilinx Gateway In port that acts as input port of FPGA. It samples incoming signal from Constant block at 1 unit sample time, and yield Boolean output to input reset rst of the PR Bit Generator, Polar Conversion, and Sin Generator subsystems. 4) PR Bit Generator Subsystem: The subsystem shown in Fig. 3 uses pseudo-random (PR) concept [10] to generate random input bit source to BPSK transmitter system. Bits 1, 5, 6, and 7 (output q of Register1, 5, 6, 7) are XORed (by Logical) together and the result is shifted to input d of Register7, while output q of Register1 is shifted out to become output of PR Bit Generator. The sample time is set as 1 unit and 20 units (samples) represent each generated bit. The initial condition of registers (Register1-7) is 1101001. The Assert re-emphasize output of Logical as Boolean type at 1 unit sample time to input d of Register7. The shift register loop is enabled at every sample interval when output out of Counter (count 0-19 at 1 unit sample time periodically) equals to 19 (Constant1 value) through comparison (by Relational). When reset rst is 0, output bit is output q of Register1 via multiplexer Mux; otherwise 0 (Constant2 value). The bit rate is 5 Mbps for 100 MSps sampling rate.
Fig. 4 Polar Conversion subsystem

6) Sin Generator Subsystem: The subsystem as shown in Fig. 5 uses look-up table (LUT) method to generate a digitally sine wave that functions as carrier sinusoid for 1 sample delay (latency: 1). The ROM (Read-Only Memory) acts as LUT to store the M-depth values of the sine sequence for n-th sample which are determined by the following equations [11]:

2 n x [ n ] = sin . M n = 0, 1, 2, ..., M 1 .

(1) (2)

The number of samples per cycle for carrier sinusoid is set to M = 20 (= number of samples per bit generated from PR Bit Generator subsystem), thus cycle of carrier sinusoid per input bit: 1. The values of sine sequence x[n] for 20-depth ROM are listed in Table I. The input addr of ROM is 5-bit unsigned integer (binary point: 0), while output of ROM is 16-bit signed fixed-point value with binary point: 14. When reset rst is 0, output sin is output of ROM, as Counter counts 0-19 at 1 unit sample time periodically; otherwise 0. The generated carrier frequency is 5 MHz (= input bit rate).

Fig. 5 Sin Generator subsystem

Fig. 3 PR Bit Generator subsystem

7) Multiplier Block: This block mixes signals of polar bit and carrier sinusoid from Polar Conversion and Sin Generator subsystems respectively by using arithmetic multiplication for 3 samples delay (latency: 3). The output (ab) of Multiplier is set to 16-bit signed fixed-point value with binary point: 13.

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TABLE I SINE SEQUENCE VALUES STORED IN ROM

Tables II and III. The configurations of ADC and DAC are set through Serial Programming Interface (SPI).
TABLE II REQUIRED PINS OF ADS5500 FOR FPGA ([12], [13])

Address n 0 1 2 3 4 5 6 7 8 9

Sine Sequence x[n] 0 0.309017 0.587785 0.809017 0.951057 1 0.951057 0.809017 0.587785 0.309017

Address n 10 11 12 13 14 15 16 17 18 19

Sine Sequence x[n] 0 -0.309017 -0.587785 -0.809017 -0.951057 -1 -0.951057 -0.809017 -0.587785 -0.309017

ADC Pin Name ADC_RESET ADC_OE ADC_SEN 1 ADC_SDATA 1 ADC_SCLK 1 ADC_IN[13:0] ADC_CLKOUT

Descriptions Reset ADC (active high). Enable ADC output (active high). Enable serial shift of data bits (active low). Serial data bits latched into ADC. Load serial data bits at falling edge. 14-bit ADC data output to FPGA. Synchronize FPGA clock to ADC output data, i.e. FPGA master clock.

8) BPSK Signal Block: Xilinx Gateway Out port that acts as output port of FPGA. It also translates the incoming fixedpoint signal (from Multiplier) in to double precision value that will be displayed in Scope block. 9) Scope Block: Simulink sink block that displays the simulation results of input bit, polar bit (latency: 1), and BPSK transmitted signal (latency: 4), as shown in Fig. 6.

TABLE III REQUIRED PINS OF DAC5687 FOR FPGA ([12], [14])

DAC Pin Name DAC_RESETB DAC_TXENABLE DAC_SDENB 1 DAC_SDIO 1 DAC_SCLK 1 DAC_DA[15:0] DAC_DB[15:0]

Descriptions Reset DAC (active low). Enable DAC output (active high). Enable serial shift of data bits (active low). Serial data bits latched into DAC. Load serial data bits at rising edge. 16-bit data output from FPGA to DAC Channel A. 16-bit data output from FPGA to DAC Channel B.

The following SPI timing requirements of ADS5500 [13] and DAC5687 [14] must be met for valid configurations: 1) ADC SPI Register Write: Delay from ADC_RESET disabled to ADC_SEN active, t3 2 s. 2) ADC SPI Clock: ADC_SCLK period, tSCLK 50 ns; ADC_SCLK duty cycle: 25% tWCLK 75%. 3) ADC SPI Loading: ADC_SEN to ADC_SCLK setup time, tSLOADS 8 ns; ADC_SCLK to ADC_SEN hold time, tSLOADH 6 ns.
Fig. 6 Simulation result displayed in Scope block

4) ADC SPI Data: ADC_SDATA hold time, tDH 6 ns; ADC_SDATA setup time, tDS 8 ns. 5) DAC SPI Clock: DAC_SCLK period, tSCLK 100 ns; DAC_SCLK high time, tSCLKH 40 ns; DAC_SCLK low time, tSCLKL 40 ns. 6) DAC SPI Loading: DAC_SDENB to DAC_SCLK setup time, tS(SDENB) 20 ns. 7) DAC SPI Data: DAC_SDIO hold time, tH(SDIO) 5 ns; DAC_SDIO setup time, tS(SDIO) 10 ns. In order to synchronize the ADC_SCLK and DAC_SCLK, clock for both SPI processes must not exceed 20 MHz (within 40-60% duty cycle). Thus, LVTTL (Low Voltage TransistorTransistor Logic) 100 MHz oscillator [15] is used to generate 20 MHz (50% duty cycle) clock for the SPI process.
1

B. HDL Design of Setup Configuration The Avnet expansion P240 Analog Module has 2 analog input and 2 analog output channels [12]. The analog input channel consists of 2 sets of THS4509 WB differential amplifier, low-pass 7th order RLC anti-alias filter, and Texas Instrument (TI) ADS5500 (14-bit, 125 MSps) ADC; while the analog output channel consists of one TI DAC5687 (16-bit, 500 MSps, 2x-8x interpolation) dual-channel DAC, 2 lowpass 5th order RLC reconstruction filters, and two 50-ohm coupled transformers. The CDCP1803 clock buffer on P240 supplies one quarter (1/4) of source clock to each of two ADS5500 ADCs and 1 source clock to DAC5687 CLK2 [12]. The pins of ADS5500 ([12], [13]) and DAC5687 ([12], [14]) required for the Xilinx Virtex-4 FPGA application are listed in

Serial Programming Interface (SPI)

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The SPI codes (2-byte) for ADS5500 [13] are: 1) Clock DLL (Delay Locked Loop): 1101000000000000; 100 MSps clock speed. 2) Test Mode: 1110000000000000; normal operation. 3) Power Down: 1111000000000000; normal operation. The SPI code (2 bytes) for DAC5687 [14] consists of instruction (first byte) and data code (second byte). The instruction code is set to transfer 1 byte (bit 6-5) data code to certain register address (bit 4-0) for each write operation (bit7). The required SPI codes for DAC5687 [14] are: 1) CONFIG2: 0000001100000000; for disabled NCO (Numerically-Controlled Oscillator). 2) CONFIG1: 0000001000110000; for Dual Clock Mode (CLK1/C from FPGA as input data rate and CLK2/C from CDCP1803 as DAC output sample rate), and 2s complement input data interpretation. 3) CONFIG0: 0000000100000110; for 4 mode of FIR (Finite Impulse Response) interpolation, disabled PLL (Phase Locked Loop), and enabled FIFO (First In, First Out). The Virtex-4 FPGA on-board ICS8442 Programmable LVDS (Low Voltage Differential Signaling) clock synthesizer provides clock signal to CDCP1803 via external connection of 2 SMA (Sub-Miniature Version A) cables. The required pins of ICS8442 [15] are listed in Table IV. The clock source is set to 25 MHz crystal (thus SYNTH_TEST is ignored) and internal PLL is enabled. The ICS8442 output clocks (FOUT[0:1]) are generated based on formula [15]:
FOUT [0:1] = 25 M / N (MHz) (3)

C. Integration of DSP Design and Setup Configuration The Verilog HDL module of setup configuration and Verilog HDL netlist of BPSK transmitter are verified firstly before combining both to become HDL module of integrated design. Both the simulation results in ModelSim environment [16] are shown in Fig. 7 and 8 respectively. Obviously, the HDL simulation result of BPSK transmitter netlist (Fig. 8) is similar to the one in System Generator design (Fig. 6).

Fig. 7 HDL simulation result of setup configuration

Fig. 8 HDL simulation result of BPSK transmitter netlist

where 8 M 28; N = 1, 2, 4, and 8. SYNTH_SLOAD, SYNTH_SDATA, and SYNTH_SCLK are unused due to parallel mode configuration. Two FPGA on-board black DIP switches are used to set M (9-bit) and N (2-bit) values. The HDL module of setup configuration includes all the ADC, DAC, and clock synthesizer configurations as described above.
TABLE IV REQUIRED PINS OF ICS8442 CLOCK SYNTHESIZER ([9])

ICS8442 Pin Name SYNTH_RESET SYNTH_PLOAD 2 SYNTH_SLOAD 3 SYNTH_SDATA 3 SYNTH_SCLK 3 SYNTH_TEST SYNTH_VCOSEL SYNTH_XTALSEL

Descriptions Reset synthesizer (active high). Load parallel M and N values at rising edge. Enable serial shift of data input (active high). Serial data input of M and N values. Load serial M and N values at rising edge. External test clock input. Enable internal PLL (active high). Select on-board crystal when set, otherwise test clock input as clock source.

Considering the real-time implementation of integrated design of BPSK transmitter and setup configuration using FPGA and P240 Analog Module, the ADC and DAC in P240 should be configured first prior to the running of DSP design, in order to avoid instability of ADC and DAC that can produce undesired outputs to or from FPGA during process of configuring ADC and DAC. Thus, the clock enable (ce) of FPGA design is disabled during the transfer of SPI codes to ADC and DAC in P240. Controlling the main ce would be easier rather than clock enable clear (ce_clr) which requires additional logics to adjust sampling phase of all the multisample data when it is de-asserted [9]. The HDL simulation result of integrated design in ModelSim environment [16] is shown in Fig. 9. D. Synthesis of Integrated Design Although Xilinx ISE suite has its own synthesis tool Xilinx Synthesis Technology (XST), but it can only synthesize HDL netlist generated from System Generator. Therefore, Synplify Pro software is used to perform logic synthesis for the HDL module of integrated design in 2 stages of logic compilation and optimization, and technology mapping [17]. Before doing the final stage of synthesis, FPGA pins (pad locations) have to be assigned accordingly to user guide of [15]. Notice that the

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Parallel Mode Configuration Serial Mode Configuration

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final synthesis for the integrated design would ignore the pin assignment of ADC_IN [13:0] and DAC_DB [15:0] since no analog input is involved in BPSK transmitter, and only one DAC analog output is used for BPSK transmitted signal.

To implement the synthesized design into Virtex-4 FPGA development board, Xilinx ISE performs the steps [18] below: 1) Translate: Convert netlist of integrated design in EDIF format to NGD (Native Generic Database) file that contains logical description of hierarchical components and Xilinx primitives by using NGDBuild program. 2) Map: Perform logical DRC (Design Rule Check) on the NGD file, and then map the design logic to slices and I/O cells in Virtex-4 FPGA to create Native Circuit Description (NCD) file. The area constraints can be sized properly using PACE (Pin-out Area Constraints Editor); then re-run Map. 3) Place and Route (PAR): Place and route the design in mapped NCD file into Virtex-4 FPGA based on timing constraints using Timing Analysis tools. The output is fully routed NCD file. 4) Bit Generation: Translate the fully routed NCD file to configuration bit-stream (.BIT) file using BitGen program. 5) Program Download: Download the bit-stream file into Virtex-4 FPGA via JTAG cable using iMPACT program. The device utilization for Virtex-4 xc4vsx35-10ff668 FPGA after Map process is shown in Fig. 10. As shown in the post PAR (final) static timing report in Table VI, the positive worst case slacks (constrained period best case required period) fulfill the timing requirement. The maximum allowable sampling rate for BPSK transmitter used in Virtex-4 xc4vsx35-10ff668 FPGA is 206.6543 MSps (= 1/4.839 ns). However, the maximum sampling rate of LIO_CLKIN_1 from ADS5500 is 125 MSps; thus the maximum sampling rate of BPSK transmitter that can be used in Virtex-4 FPGA MB development board with P240 Analog Module is 125 MSps.

Fig. 9 HDL simulation result of integrated design

Timing characteristics is an important issue that will affect the performance of FPGA implementation. The required path delay (estimated period) for Xilinx FPGA element should be less than the requested (constrained) clock period. So, timing slack (requested period estimated period) should be positive value; otherwise the integrated design has to be reworked. The clock frequencies used for the ADC/DAC SPI process and BPSK transmitter i.e. CLK_100 and LIO_CLKIN_1 (or ADC_CLKOUT) are set to 100 MHz for both. The positive slack values in timing report of design synthesis in Table V meet the timing requirement. If any Xilinx IP (Intellectual Property) core is used in the integrated design, there will be another clock called System after clocks of CLK_100 and LIO_CLKIN_1 [17]. However, no Xilinx IP core is used for the developed integrated design.
TABLE V TIMING REPORT OF DESIGN SYNTHESIS

Constraint Clock CLK_100 LIO_CLKIN_1

Requested Frequency Period 100.0 MHz 10 ns 100.0 MHz 10 ns

Estimated Period 5.280 ns 4.404 ns

Slack 4.720 ns 5.596 ns

III. IMPLEMENTATIONS OF FPGA AND DAC A. Software Implementation of FPGA Design The synthesis output files required by Xilinx ISE software are in EDIF (Electronic Design Interface File) and UCF (User Constraints File) formats, which represent the optimally synthesized netlist of integrated design, and timing constraints and FPGA pin assignment respectively.
Fig. 10 Device utilization for Virtex-4 xc4vsx35-10ff668 FPGA

B. Hardware Implementation and Result The FPGA on-board black DIP switches [15] are set to M[8:0] = 000110000 and N[1:0] = 00, in order to generate 400 MHz clock from ICS8442 to CDCP1803, by using (3). Then, the sampling rate of LIO_CLKIN_1 is 100 MHz (= 400/4).

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TABLE VI POST-PAR STATIC TIMING REPORT

Constraint Clock Name CLK_100 LIO_CLKIN_1 Period 10 ns 10 ns

Worst Case Slack (ns) Setup Hold 5.684 0.534 5.161 0.452

Best Case Required Period 4.316 ns 4.839 ns

Error 0 0

matching should be concerned in-depth if the input bit is coming from external source which is different from the presented design. Inserting pulse-shaping filtering between polar conversion and mixer can further reduce inter-symbol interference (ISI) to enhance the receiver performance. Precoding like source and channel coding can also be added in BPSK transmitter for error checking and control. ACKNOWLEDGMENT Special thanks to Mr. Mazlaini Yahaya from TMRD (Telekom Malaysia Research and Development) for giving precious guidance and information related to Xilinx FPGA implementation. This paper was supported in part by the Malaysia Communication and Multimedia Commission (MCMC) SCIENCE FUND grants and Universiti Sains Malaysia (USM) Fellowship. REFERENCES
[1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] J. Mitola, The Software Radio Architecture, IEEE Commun. Mag., vol. 33, no. 5, pp. 26-38, May 1995. J. E. Gunn, K. S. Barron, and W. Ruczczyk, A Low-Power DSP CoreBased Software Radio Architecture, IEEE J. Sel. Areas Commun., vol. 17, no. 4, Apr. 1999. M. S. Safadi and D. L. Ndzi, Digital Hardware Choices for Software Radio (SDR) Baseband Implementation, in Proc. 2nd ICTTA06, 2006, vol. 2, pp. 2623-2628. J. G. Proakis, Digital Communications, 5th ed., New York: McGrawHill, 2008. F. Ahamed and F. A. Scarpino, An Educational Digital Communications Project Using FPGAs to Implement a BPSK Detector, IEEE Trans. Edu., vol. 48, no. 1, Feb 2005. K. E. Mohamed and B. M. Ali, Digital Design of DS-CDMA Transmitter Using VHDL and FPGA, in Proc. Jointly Held with 7th MICC and 13th ICON, 2005, vol. 2, pp. 632-636. F. M. Demir, U. Kafadar, S. Dikmese, and H. Dincer, FPGA Based Implementation of Communication Modulation, in Proc. 15th Signal Process. & Commun. Appl., 2007, pp. 1-4. Y. Tachwali and Hazem, Implementation of a BPSK Transceiver on Hybrid Software Defined Radio Platforms, in Proc. 3rd ICTTA, 2008, pp.1-5. System Generator for DSP User Guide, Release 9.2.01, Xilinx, Inc., Oct. 2007. N. P. Cagigal and S. Bracho, Algorithmic determination of linearfeedback in a shift register for pseudorandom binary sequence generation, IEE Proc., vol. 133, Pt. G, No. 4, pp. 191-194, Aug. 1986. A. V. Oppenheim and R. W. Schafer, Discrete-time Signal Processing, 2nd ed., Upper Saddle River, New Jersey: Prentice-Hall, 1999. P240 Analog Module User Guide, Rev 1.0, Avnet Inc., May 2006. [Online]. Available: http://www.files.em.avnet.com/files/177/p240_analog-ug.pdf ADS5500: 14-bit, 125 Msps, Analog-to-Digital Converter data sheet, Texas Instruments Inc., Feb. 2007. [Online]. Available: http://focus.ti.com/lit/ds/symlink/ads5500.pdf DAC5687: 16-bit, 500 Msps, 2x-8x, Interpolation Dual-Channel Digital-to-Analog Converter (DAC) data sheet, Texas Instrument Inc., June 2005. [Online]. Available: http://focus.ti.com/lit/ds/symlink/dac5687.pdf Virtex-4 MB Development Board User Guide, Ver. 3, Avnet Memec, Dec. 2005. [Online]. Available: http://www.files.em.avnet.com/files/177/v4mb_user_guide_3_0.pdf ModelSim SE Users Manual, Ver. 6.2c. Mentor Graphics Corp., 2006. Synplicity FPGA Synthesis Reference Manual, Synplicity Inc., 2007. Xilinx ISE 9.2i Software Manuals: Constraints Guide, and Development System Reference Guide, Xilinx Inc., 2007.

The DAC Channel A output from P240 Analog Module is connected to oscilloscope in order to display real-time result in analog domain. By observing the real-time result of BPSK transmitted signal as shown in Fig. 11, the measured time difference between 2 adjacent positive peaks (t) is 200 ns. Thus, the measured carrier frequency of real-time result is 5 MHz (= 1/200 ns) which is equal to the expected values as described in Sin Generator subsystem under section II. The minor difference of amplitudes (V = 0.04V) for the first peak (1 V) and second peak (0.96 V) is because of limitation of the 50-ohm transmission coupled transformer after DAC in P240 Analog Module [12]. Nevertheless, comparison of the empirical real-time result (Fig. 11) and simulated results (Figs. 6 and 8) for BPSK transmitted signal has shown equivalence in time domain and significant phase shift of 1800 or radian.

Fig. 11 Real-time result of BPSK transmitted signal

[12] [13] [14]

IV. CONCLUSION This paper has presented a detailed guideline to design and implement the BPSK transmitter in Virtex-4 FPGA MB development board with DAC in P240 Analog Module. Many software and design tools have been used to verify the design output in terms of behavior, functionality, synthesis, timing, and area constraints. The similarity of empirical real-time and simulated results shows the success of FPGA and DAC implementations that would be further processed by external analog RF devices for complete wireless SDR system. On the other hand, timing issues such as sample rate, constraints, and

[15] [16] [17] [18]

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