Abstract An analytical extrinsic gate capacitance model based on threedimensional numerical simulations for Triple Gate FinFET, was

s developed. The model considers the source/drain electrode and contact areas. It is compound for 9 capacitance components which describes the different fringing electrical couplings that appears inside the FinFET structure. The analytical model accurately calculates the total extrinsic gate capacitance as function of main geometrical parameters of Triple-Gate FinFET. Index Terms FinFETs, Extrinsic Capacitance, Fringing Gate Capacitance, Fringing Electric Field. I. INTRODUCTION The last years, FinFET has demonstrated be a promising candidate to carry on with downscaling of CMOS technology, due to his superior control of the short channel effects (SCE). Nevertheless, since their three-dimensional structure, FinFETs show high parasitic resistances and capacitances which lead to strong degradation of their analog and RF performance [1][2]. Improvements can be reached, especially concerning to reduction of the total extrinsic gate capacitance (Cgge). The FinFETs RF model is based on the well-known small-signal equivalent circuit (SS-EC) and implies an accurate determination both intrinsic and extrinsic parameters. Thus, a compact model which determine the DC and intrinsic RF parameters was demonstrated [3]. To complete the SS-EC, is requiered an accurate extrinsic capacitance model which are strongly dependent on the FinFET geometry. Recently, Wu and

Chan [1] developed a semi-analytical model to describe total extrinsic gate capacitance of double-gate FinFETs. Fig. 1a shows a schematic representation of the structure used and identifies the main FinFET geometrical parameters. Three capacitance components associated to the FinFET structure were considered, as Figs. 1b to 1d

Figure 1 Fi FET h i i i h 2 schematic representations of the different capacitance components associated to the 3-D structure.

the gate electrode to the internal side of h S/D fi x i I h the S/D electrode regions are not considered and thus some important parasitic capacitances are not modeled while they are not negligible. In this paper, based on 3-D numerical simulations, a semi-analytical model for the extrinsic gate capacitances for TripleGate FinFETs is presented. This model includes the S/D electrode and contact areas and the interactions between gates in order to overcome the limitations of previous models and thus provide a complete and accurate modeling of the total extrinsic gate capacitance valid for

a wide range of FinFET geometries.

II. THE COMPACT MODEL

In a tridimensional FinFET structure there are some typical capacitor structures like: (I) parallel plate capacitor, (II) perpendicular plate capacitor, (III) flat plate non parallel capacitor, (IV) fringing field capacitive component, (V) Capacitancia de una lnea bifilar monofsica
Structure Expresion (I)

c)

d)

e)

f)

g)

h)

(II) ( (III) ( (IV) ( ) (V) ( )

Table 1. Simple capacitance expressions Figure 2. Schematic representations of the five capacitance components, C1-C9, considered in our proposed compact model.

)
i)

Including the S/D contact reas and the capacitance effects between gates, based on the classical capacitance formulations presented in Table I, we propose a compac model with nine extrinsic capacitance components as illustrated Figure 2.

The first component C1 (Fig. 2a) can be represented as flat-plate nonparallel structure, exhibing dependence with Lfin, Lext, Wfin, Tpoly, and tox, and can be expressed as:
(1) ( ( ( ) ) ( ))

a)

b)

( (

) )

)) (

( ( )

))

(4)

we divide these components in two cases, for inner case (between gates) was developed C1i and for the outer case C1e (for FinFET end) C2 component (Fig 2b), depends of Lext, Wfin, Tpoly, and tox, similarly to C1 have two cases and its base on perpendicular

C5 was obtained with perpendicular

plate capacitor case, thos component correspond from the side of the gate electrode located above the fin spacing and the top of the S/D contact regin
( ( ( ) )) (5)

plate capacitor case.

(2) ( ( ( ( ) ) ( ( )) ))

Four cases were developed considering that there are capacitive effect between the gates. The first one Considering a parallel plate capacitor we derive C6 component, which depends of separation between gates (2(Lext)+Wcon) with lenght Sfin+Wfin and high Tpoly+tox.
( )( ) (6)

( ( ( (

) )

( ( ))

))

C3 component was developed taking on account that both capacitances parallel plate and perpendicular plate occurs at the same time, showing dependance of Hfin, Sfin, Lext and tox
(3) ( ) ( )

For C7 component was based (V) case, by not considering cilinders, neglecting and taking r as gate width
( ( ) ) (7)

C4 come in to a flat plate non parallel

C8 and C9 component was developed observing that wasnt previously considered the effect of the gate side (Tpoly) to the internal contact portion and the lower adjacent gate
(8) ( ( )) ( (9) )

capacitance, which corresponds to the capacitance from the top of the gate electrode to the top the S/D contact regin and exhibits dependences with of Tpoly, Lext, Sfin and Wcon

( (

))

Because RF transistors consist of multi-fin devices, the total gate capacitance per gate finger is defined by the sum of the whole components expressed by (1)-(9), considering that we develop the model with inner and outer components we add the components as:
( ( ( ) ( ) ( ) [( ) ) ( ( )] ) )

Wcon, Sfin, Wfin, Lfin and Hfin. The compact model has been validated for a wide range of FinFETs dimensions. Simulation results show optimization paths to decrease the impact of extrinsic capacitances, such as the reduction of fin spacing Sfin, the S/D fin extension Lext as well as by increasing the fin aspect ratio (Hfin/Wfin). The proposed compact model is of great interest for designers considering FinFET technology for highspeed digital and RF applications. REFERENCES 1 M Ch A y i f geometry-dependent parasitics in multifin Double-G Fi FET IEEE TED v 54, no. 4, pp. 692-698, April 2007. 2 J C Ti I f extrinsic capacitances on FinFETs RF f i 2012 12 h SiRF 7376. 3 J Av Sig M f 8th ICCDCS. C S RF Fi FET i 2012

III. SIMULATIONS
Tridimensional finite element numerical simulations were performed in order to verify the developed compact. Simple structures were used to analyze each capacitance component, finally the full FinFET structure was used to verify the total gate capacitance.

IV. RESULTS

4 D G O -chip interconnectaware design and modeling methodology, based on high bandwidth transmission i vi i 2003 41 DAC 724727.

V. CONCLUSION
An analytical model for extrinsic gate capacitance for Triple-Gate FinFET is presented. The model considers he S/D contact region and includes five capacitance components. It is based on simple capacitor structures and describes the dependences with the main geometrical FinFET parameters: Lext,