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Lesson 2

Digital Control of Three -Phase DC/AC Converters : Space Vector Modulation

September 1999

Lesson 2

Voltage Space Vector Modulation


A three three- phase inverter can generate three independent twotwo -level phase voltages. voltages . Eight different instantaneous inverter configurations (states states) ) are available available. . By suitably switching ( (modulation modulation strategy) strategy) among these states it is possible to generate any triplet of average phase voltages V1avg, V2avg, V3avg ranging from +E/2 to -E/2, where E is the DC link voltage voltage. .
September 1999 Lesson 2 2

Voltage Space Vector Modulation


When the load is connected with insulated neutral, it is only sensitive to line line-to-to-line line voltages. voltages . The neutral voltage doesnt have any effect on it. it . Any voltage triplet can be schematically represented as a vector laying on a plane ( (bi bidimensional representation representation). ). In general, the information about the value of the instantaneous neutral voltage ( (the the third dimension!) dimension !) cannot be represented and gets lost. lost .
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Voltage Space Vector Modulation

+ E v1 v2 v3
ThreeThree -phase Voltage Source Inverter
September 1999 Lesson 2 4

Voltage Space Vector Modulation


The voltage vector representing the triplet v1, v2, v3, can be drawn by summing three vectors (lenght proportional to amplitude) directed as three 120 shifted axes (a, b, c).

V1 V2 V3

b V3 V1 V a

V2 c
Lesson 2

September 1999

Voltage Space Vector Modulation

We therefore defined a

Direct Vector Transformation


between the triplet v1, v2, v3, and vector V. A similar transformation can be defined for inverter currents ....

September 1999

Lesson 2

Voltage Space Vector Modulation


The direct transformation can be analytically formulated referring to a couple of orthogonal axes and ( usually coincident with axis a).

V V V = V1 2 3 2 2 V =
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V3

V
V1 V

3 (V V3 ) 2 2
Lesson 2

V2

Voltage Space Vector Modulation


The reverse vector transformation can be achieved starting from a 2/3 V long vector and projecting it on the three axes a, b, c.

2 V 3 2 3 V V2 = V 3 2 2 V1 =

V3

2/3 V

V a

2 3 V V3 = V 3 2 2 c
September 1999 Lesson 2

V2

V1

Voltage Space Vector Modulation


The inverter states can also be represented as voltage vectors. vectors. As an example: example :

State 100:

V1=E V2=0 V 3=0


V 010 V110 V100 V011 V001 V101
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+ E -

V1 V2 V3

September 1999

Lesson 2

Voltage Space Vector Modulation


The zero vector can be generated in two equivalent ways: ways:

State 111:

V1=E V2=E V 3=E

+ E -

V1 V2 V3

V111

but also ...


September 1999 Lesson 2 10

Voltage Space Vector Modulation State 000: V1=0 V2=0 V 3=0

+ E -

V1 V2 V3

V000

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Voltage Space Vector Modulation


Space Vector Modulation (SVM) is performed by generating generating, , within the switching period, period, a sequence of different inverter states states. . The sequence normally consists of three vectors, vectors , one of which is the zero vector. The durations of the three inverter states have to satisfy the following constraint constraint: :

1+2+ 3=1
where i is the duty duty-cycle on phase i.
September 1999 Lesson 2 12

Voltage Space Vector Modulation

V110 V111 V* V100

To generate a triplet V1avg, V2avg , V3avg (average voltages) voltages) in a switching period, period, vector V*, the transformation of the triplet, triplet, is considered. considered. The two adjacent vectors and a zero vector are applied successively. successively.

September 1999

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Voltage Space Vector Modulation


V110

The projections of V* on the adjacent vectors determine the respective duty duty- cycles cycles. . The zero vector duty dutycycle is determined from the relation: relation:

1V110 3V111

V* V100

2V100

1+2+3=1,
if possible. possible.
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September 1999

Lesson 2

Voltage Space Vector Modulation


Vectors V* which can be generated with this technique are the ones included in the hexagon [1]. It is possible to select different orders of application for the three vectors. vectors .
Lesson 2 15

V110 V111 V* V 100

September 1999

Voltage Space Vector Modulation


E E

V1 V2

V3 V100

2T
T

V110

V111

1T

3T

2T

V100

V110 V111

1T

3T

A possible vector sequence sequence: : we can do better than that ...


September 1999 Lesson 2 16

Voltage Space Vector Modulation


E E

V1 V2

V3 V100 2T
T

V110

V111 V111 1 T 3T 3T

V110 1T
T

V100 2T

This choice reduces the number of switchings


September 1999 Lesson 2 17

Voltage Space Vector Modulation


E E

V1 V2

V3

3 T/2 2T

V000 V100
T

V110

1T

V111 V110

3 T T 1

V100
T

2T 3 T/2

V 000

This choice minimizes the current ripples amplitude


September 1999 Lesson 2 18

Voltage Space Vector Modulation


The effect of the last strategy is to achieve centered voltage pulses. This is the same effect achieved with a conventional sinesine triangle modulator having a 2T period period. . The difference is in the dutyduty- cycles achieved cycle by cycle. cycle . With vector modulation an inherent third harmonic injection is implemented ( (the the base vectors do not lay on the , plane). This allows the maximum modulation index to be equal to 1.15.
September 1999 Lesson 2 19

Voltage Space Vector Modulation


SineSine - triangle modulation
+A

V1 *

V2 *

V3 *

-A

V10avg
E

V10
0 E

V20avg

V20
0 E

V30avg

V30
0
September 1999 Lesson 2 20

Voltage Space Vector Modulation


Neutral Voltage Variation
V 10 V
N0

20

N0

30

V V
23

N0

12

31

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Voltage Space Vector Modulation


Third Harmonic Injection
V 10 V 20

V 30 V N0 V 23 V 12 V 31

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Voltage Space Vector Modulation


Third Harmonic Injection

E E/2 0

1.15 E V N0 V 10

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Voltage Space Vector Modulation


By explicitly calculating [2] the instantaneous dutyduty -cycles for pulse centered space vector modulation strategy, strategy , it can be demonstrated that the process is equivalent to conventional modulation where to all dutyduty- cycle a common component is added, added , which is equal to: -0.5[ max max( (1, 2, 3) + min( 1,2, 3) ]. The waveform corresponding to the above relation is very close to a sinusoidal third harmonic. harmonic . This also allows the maximum modulation index to be equal to 1.15.
September 1999 Lesson 2 24

Voltage Space Vector Modulation


Another widely adopted modulation strategy is the soso-called flat flat-top top. . A variable common component is added to each dutyduty -cycle so that the modulation requires only two phases for each 60 interval of the fundamental period period, , while the third is not used (no switchings take place). place ). The trick is to saturate the maximum ( (or or minimum) minimum ) duty duty-cycle in every swiching period period. . This also allows the maximum modulation index to be equal to 1.15.
September 1999 Lesson 2 25

Voltage Space Vector Modulation


+2E 0 +2E 0 +2E 0 +2E 0 V23 V12 VN0 V31 V10

FlatFlat - top

V 20 V 30

September 1999

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Voltage Space Vector Modulation


Instantaneous and average phase voltage with flatflat -top modulation. modulation. Each phase switches only in 2/3 of the fundamental period period. .

2E V10avg

V10

0
September 1999 Lesson 2 27

Voltage Space Vector Modulation


Summing to each dutyduty-cycle the same common component, component , constant or variable: variable : the instantaneous phase voltages change change; ; the average phase to neutral voltages change accordingly; accordingly ; the average phase to phase voltages do not change; change ; if the neutral wire is insulated insulated, , the voltage on the load (Y) does not change change. .
September 1999 Lesson 2 28

Voltage Space Vector Modulation


The calculations needed to implement the SVM concept are very effectively performed by means of C and DSPs. DSPs. The pulse generation strategy adopted by the embedded PWM modulators is normally the one corresponding to minimum ripple. ripple . The SVM strategy is very widely used in modern digitally controlled three three-phase VSIs. VSIs .
September 1999 Lesson 2 29

Digital Implementation of SVM


Modern Cs and also some DSPs greatly simplify the implementation of SVM: the PWM units automatically centre the pulses within the modulation period; period ; the duty duty-cycles have to be provided to the PWM unit by a suitable algorithm; algorithm ; the direct implementation of Space Vector Modulation including , transform is often the preferred choice; choice ; sometimes post post- processing of the duty dutycycles can be adopted. adopted .
September 1999 Lesson 2 30

Digital Implementation of SVM


SVM is normally the inner routine in the digital control of a VSI; external current loops typically provide the set set-point for the modulator: modulator: in the a, b, c fixed reference frame ( (the the three dutyduty -cycles are given given); ); in the , fixed reference frame ( bi bi-dimensional -dimensional control: control : the average voltage vector components are given given); ); In the former case the duty duty-cycles can be modified by injecting a third harmonic component component. . The latter case is suited for direct SVM implementation implementation. .
September 1999 Lesson 2 31

Direct Implementation of SVM


Given the , components of the setset- point V*, the digital modulator has to compute the projections of the reference vector V* on the adjacent inverter states states. . If a floating point processor is available, available, this is not a problem problem. . If this is not the case, a lot of different algorithms can be applied. applied . An example of SVM algorithm is reported in [3]. Another example is described in the following. following.
September 1999 Lesson 2 32

Direct Implementation of SVM


Z1y Z2y Z2x Z3x

Z1x

Z3y

{ , } { {Z Zix, Ziy}
1 1 3 M1 = 2 0 3
September 1999

1 M2 = 1
Lesson 2

1 3 1 3

2 0 3 M3 = 1 1 3
33

Direct Implementation of SVM


Some regularities in the transform matrixes Mi can be exploited to rapidly calculate the Zix ix,y ,y components of the voltage vector V*: tmp Z1x Z2y Z1y Z3x Z2x Z3y
September 1999

= V* / sqrt sqrt(3); (3); = V* - tmp tmp; ; = - Z1x; = 2 tmp tmp; ; = Z 1y; = V* + tmp tmp; ; = - Z2x;
Lesson 2 34

Direct Implementation of SVM


Once the Zix ix,y ,y components of the voltage vector V* are known it is easy to determine the sector V* lies in in, , e.g.: Z1x Z1y < 0 ? yes Z2x Z2y < 0 ? yes Z3x Z3y < 0 ? ... ...
September 1999

no Z1x > 0 ? yes 1st no 4th

no Z2x > 0 ? yes no 2nd 5th


Lesson 2

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Direct Implementation of SVM


Given the sector, sector , it is immediate to determine which inverter voltage vectors have to be generated and consequently the required switching sequence. sequence . The durations of the two required inverter states V1 and V2 are proportional to the Zix and Z iy components of the average vector V* respectively respectively. . According to what was previously explained, explained , the zero vector V0 duration is given by the following: following :

T1+T2+T0=T,
unless saturation occurs. occurs.
September 1999 Lesson 2 36

Direct Implementation of SVM


In the presence of saturation, saturation , i. e. when the required average voltage vector V* lies outside the hexagon, hexagon, different strategies can be adopted. adopted . A possibility is to reduce the voltage vector V* amplitude, while keeping its phase, phase, so as to put it on the hexagon border. border . This well exploits the inverter capability and is easy to implement implement: : Tisat = T Ti/(T 1+T2), i = 1, 2
September 1999

V*

V* sat

Lesson 2

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Direct Implementation of SVM


A rough alternative which does not require troublesome calculations, calculations, is to reduce the smaller vector component enough to put the vector on the hexagon border: border: This solution implies an V* unavoidable error both in the amplitude and in the V* sat phase of the generated vector.

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Direct Implementation of SVM


If deep saturation occurs occurs, , i. e. at least one of the two components Vi of vector V* is is, , by itself, itself, outside the hexagon, hexagon , another saturation strategy is normally adopted. adopted . The nearest inverter state is steadily generated for the complete switching period T. This leads the converter to six six-step mode of operation. operation . In the SVM algorithm the transition from light saturation to deep saturation can be suitably managed
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Direct Implementation of SVM

Light saturation areas

Deep saturation areas, areas , extending also outside the circle

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Final Remarks
SVM is very commonly adopted in modern digital control of power converters ( (especially especially in drive applications). applications ). The implementation of SVM by means of Cs or DSPs is easy to achieve both directly ( (if if the required computational power is available) available ) and indirectly, indirectly , by post post-processing the phase dutydutycycles with a suitable harmonic injection. injection . In any case converter saturation must be considered and suitably dealt with. with.
September 1999 Lesson 2 41

References
[1] J. Holtz Holtz, , W. Lotzkat Lotzkat, , A. Khambadkone Khambadkone, , On Continuous Control of PWM Inverters in the Overmodulation Range Including the SixSix- Step Mode Mode , International Conference on Industrial Electronics Control and Instrumentation (IECON), 1992, pp pp. . 307-312. [2] H. W. Van Der Broeck Broeck, , H. C. Skudenly Skudenly, , G. V. Stanke Stanke, , Analysis and Realization of a Pulsewidth Modulator Based on Voltage Space Vectors, Vectors , IEEE Trans Trans. . on Industry Applications, Applications, Vol Vol. . 24, No. 1, Jan/ Jan /Feb Feb, , 1988, pp pp. . 142-150. [3] Zhenyu Yu , Space Space-Vector -Vector PWM With TMS320C24x/F24x Using Hardware and Software Determined Switching Patterns, Patterns , Application Report SPRA524, Texas Instruments Instruments. .

September 1999

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