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# Recitation 25 CMOS Cascade Amplier 6.

## 012 Spring 2009

Last week, we talked about a particular example of multi-stage amplier: CS-CB cascode
amplier. We used BJT/CMOS in the circuit (BICMOS)
Today we will look at the CMOS cascode amplier with some specic requirement on R
out
,
and see how to generate I
sup
and V
B
This is a CS-CG CMOS cascode amplier. It has
R
in

R
out
very high (compare to CS only)
Very good frequency response (close to CG, better than CS)
1
Recitation 25 CMOS Cascade Amplier 6.012 Spring 2009
Example: Device Data
V
Tp
= 1 V
p
C
ox
= 25 A/V
2

p
= 0.02 V
1
V
Tn
= 1 V
n
C
ox
= 50 A/V
2
,
n
= 0.05 V
1
, L = 2 m
Goal:
design transconductance amplier with G
m
= 1 mS, R
out
10 M, R
in
= .
With 5 V power supply, 2 m CMOS process.
output drives other CMOS (capacitive load).
Use I
sup
= 100 A.
Small signal model of the circuit
R
in
=
R
out
2
=
oc
||(
o2
+
o2
g
m
R
s
) =
oc
||(
o2
g
m2

o1
))
_ _
R
s
=
o1
Overall G
m
=
v
out
=
i
in2
=
g
m1
v
gs1

o1

o1
+
1
g
m2
= g
m1
G
m
=
v
s
v
s
g
m1
= 1 mS =
v
s
g
m1
=
_
2
_
w
L
_
1

n
C
ox
I
D
= 1 mS
Solve for w
1
, w
1
=
g
2
m1
L
1
2I
D

n
C
ox
=
(1 mS)
2
(2 m)
2 100 A 50 A/V
2
= 200 m
This is design on M1.
2
Recitation 25 CMOS Cascade Amplier 6.012 Spring 2009
M2: output resistance requirement determines size of M2
R
out

oc
||(g
m2

o2

o1
) 10 M
Assume both
oc
, g
m2

o2

o1
are on the same order,

oc
g
m2

o2

o1
= g
m2

o1

o2
20 M
1 1

n
= 0.05 V
1
=
o1
=
o2
= = = 200 k

n
I
D
(0.05 V
1
)(100 A)
g
m2
(200 k)(200 k) 20 M = g
m2
5 10
4
S = 0.5 mS
_
_

_ _ _
w w
g
m2
= 2I
D

n
C
ox
= = 25, w
2
= 50 m
L 2

L 2
Current Source Design
Now how to design current source I
sup
so that
oc
20 M? Yesterday we talked about
simple MOS current source
= need to cascode circuit for current source. Add a current buer (CG) for high R
out

## Source resistance of current supply

3
_ _
Recitation 25 CMOS Cascade Amplier 6.012 Spring 2009
R
current source
= R
out
of CG
= (g
m4

o4
)
o3

..
Rs
= g
m4
500 k 500 k 20 M
Need g
m4
, which is determined by size M4
Size of M3 and M4 is related to V
G3
and V
G4
to bias these gates, M3 and M4 need to be in
saturation regime:
V
SD
> V
SG
+V
Tp
ChooseV
SG
= 1.5 V = minimumV
SD
= (1.5 1), V = 0.5 V
(If we choose smaller V
SG
, we will need larger device
w
to carry 100 A)
L
with V
SG
= 1.5 V = V
G
3
= 3.5 Vand V
G4
= 2 V
Since |I
DP
|
2
w
L

p
C
ox
(V
SG
+V
Tp
)
2
= 100 A
=
2|I
Dp
|
= 32 =
64
L 3,4
p
C
ox
(V
SG
+V
Tp
)
2
2
w
g
m4
=
p
C
ox
(V
SG
+V
Tp
) = 0.4 mS
L
(Size of M3B & M4B should be the same as for M4 and M3, helps in matching current
ow). Then
R
currentsource
= g
m4

o4

o3
= (0.4 mS)(500 k)(500 k)
= 100 M > 20 M
4
Recitation 25 CMOS Cascade Amplier 6.012 Spring 2009
What does the design look like so far?
= Need voltage source for V
B
. Use diode connected NMOS (M2B) between I
REF
and
PMOS
5
_ _

Recitation 25 CMOS Cascade Amplier 6.012 Spring 2009
w
L
w
Make M2B same size as M2,
2B
= 50/2 and:
2I
REF
V
GS
2
= V
GS
2B
= V
Tn
+ _ _ = 1.4 V

n
C
ox
2 L
6
Recitation 25 CMOS Cascade Amplier 6.012 Spring 2009
Output Voltage Swing
upswing : M4 must stay in saturation regime
V
SD
4
V
SG
4
+V
Tp
= V
SD
4
1.5 V 1 V = 0.5 V
Since V
S
4
= 3.5 V = V
D
4
3 V
down swing : M2 must stay in saturation regime
V
DS
2
V
GS
2
V
Tn
, V
DS
2
1.4 V 1.0 V = 0.4 V
Since V
S
2
= 0.6 V, V
D
2
1 V
= Swing is 1.0 V V
out
3.0 V
7
MIT OpenCourseWare
http://ocw.mit.edu
6.012 Microelectronic Devices and Circuits
Spring 2009